Making Analog Circuit Generators Usable

John Crossley, Kwangmo Jung, Elad Alon

Dept. of EECS and BWRC UC Berkeley

Modern SOC Design – Apple A5

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Personal Example #1: Digital PLL

Integral Path

Regulator

PFD/DCO

Coarse Control

Path

Supply Noise Gen/Test

BBPD

÷N

150 um

170 umCdecap

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Potential Design Solutions for “Non-Critical” Blocks

4 [indiejourno.com]

•  Outsourcing – i.e., pay someone else to do it –  Either by hiring spice monkeys or buying IP –  May not get precisely what you want, and still need to verify

Potential Design Solutions for “Non-Critical” Blocks

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•  Design re-use –  Great when specs/

process don’t change

–  New process/specs à need to re-design/re-verify

[muneda.com]

•  Outsourcing

Potential Design Solutions for “Non-Critical” Blocks

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•  Outsourcing •  Design re-use

•  What we really want: Automatically repeat (expert) designer’s procedure •  Including circuit sizing, layout generation, and

verification

Berkeley Analog Generator (BAG)

SimulationSettingsLayout

Process Information

Sized Schematic

Circuit Architecture

VerificationConditions

Layout

Process Information

Sized Schematic

Circuit Architecture

VerificationConditions

SimulationSettings

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•  Goal: codify analog designer’s methodology –  So that analog designer’s output isn’t one instance –  But is instead a generator of that block

•  BAG: hierarchical, Python-based framework –  Allows specification of design and layout procedure

Background Note •  Capturing designer’s methodology not a new

idea [1]

•  Considered impractical because of: [2]

–  Lack of flexibility –  Extra effort to introduce new circuit architectures

•  Initial design time perceived to be higher in order to come up with a “general” solution

•  Not yet widely adopted…

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[1] R. Harjani, R.A. Rutenbar, L.R. Carley, IEEE TCAD, 1989 [2] R.A. Rutenbar, G.G.E. Gielen, J. Roychowdhury, Proceedings of the IEEE, 2007

Why We Should Try Again

•  Times have changed – Designs: more complex mixed-signal SoC’s

– Tools: better auto-layout and optimization

– Designers: (1) circuits very well-understood (2) “it’s a dark art” is just an excuse (3) more familiar with programming

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Typical Generator Writer’s Flow

Schematic Template

[1] Dean Liu Ph.D. Thesis, Stanford, 2003 11

• Parameterization • Annotate schematic with design intent [1]

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Typical Generator Writer’s Flow Python Code

Sized Schematic

Sim. Results

Strategy for Incorporating Layout

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[ciranova.com]

•  Leverage existing tools

–  Exploring Ciranova Helix and PyCells

•  Translate design intent & specs into geometric constraints

•  Work in progress

Don’t Over-Generalize

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•  Designers don’t try to address every possible usage scenario with one design –  So why should we?

•  Let designers decide what generators to write and use

Current and Future Work

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•  Alpha release of BAG being deployed for: –  Bias DACs –  Comparators –  Linear regulators –  Oscillators –  SC DC-DC converter

•  Just the beginning of the story –  Analog designers should by

default use BAG-like approaches