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EE2324/ Microprocessors & Microcontrollers Department of EEE 1

MAHALAKSHMI

ENGINEERING COLLEGE

TIRUCHIRAPALLI-621213.

QUESTION BANK

DEPARTMENT: EEE YR/ SEM:III/ VI

SUB CODE: EE2324 SUB NAME: MICROPROCESSORS & MICROCONTROLLERS

UNIT 2- PROGRAMMING OF 8085 MICROPROCESSORS

PART A (2 Marks)

1. What are the types of addressing modes in 8085 microprocessor? (AUC MAY 2012)

1. Immediate Addressing

2. Direct Addressing

3. Register Addressing

4. Register Indirect Addressing

5. Implied Addressing

2. What is the use of branching instruction? Give examples. (AUC MAY 2012)

Branching instruction helps us to change the program execution sequence

(JMP)

Helps us to call a subroutine in the main program.(CALL, RET)

Program execution is changed depending on the flag condition (JC, JNC, JZ,

JNZ)

3. Why do we need lookup table? (AUC NOV 2011)

Lookup table is an array that replaces runtime computation with a simpler array

indexing operation. The savings in terms of processing time can be significant, since

retrieving a value from memory is often faster than undergoing an 'expensive'

computation or input/output operation.[1] The tables may be precalculated and stored

in static program storage, calculated (or "pre-fetched") as part of a program's

initialization phase (memorization), or even stored in hardware in application-specific

http://en.wikipedia.org/wiki/Array_data_structurehttp://en.wikipedia.org/wiki/Input/outputhttp://en.wikipedia.org/wiki/Lookup_table#cite_note-1http://en.wikipedia.org/wiki/Static_memory_allocationhttp://en.wikipedia.org/wiki/Prefetcher


platforms. Lookup tables are also used extensively to validate input values by

matching against a list of valid (or invalid) items in an array and, in some

programming languages, may include pointer functions (or offsets to labels) to

process the matching input.

4. How are 8085 instructions classified according to the functional categories? (AUC

NOV 2011)

Instruction set of 8085 is classified as

Data transfer or copy instructions

Arithmetic instructions

Logical instructions

Branching instructions

Machine Control instructions

5. State the function of given 8085 instructions: JP, JPE, JPO, JNZ. (AUC MAY 2011)

JP ADDRESS - Jump on positive – jump to the specified address location if the sign

flag is 0

JPE ADDRESS – Jump on parity even- jump to the specified address location if the

parity flag is 1

JPO ADDRESS – Jump on parity odd – jump to the specified address location if the

parity flag is 0

JNZ ADDRESS – Jump on Non Zero- jump to the specified address location if the

zero flag is 1

6. How is PUSH B instruction executed? Find the status after execution. (AUC MAY

2011)

PUSH B instruction stores the data in the B register. The stack pointer stores a

address. The data in the specified address location is stored in the B register. So

after execution of this instruction , the data in the address specified by the stack

pointer is stored in the B register.


PART B (8, 16Marks)

1. Describe the addressing modes of 8085 microprocessor with suitable instructions.

(AUC MAY 2012)

ADDRESSING MODES

Every instruction of a program has to operate on a data. The method of

specifying the data to be operated by the instruction is called Addressing. The

8085 has the following 5 different types of addressing.

4. Immediate Addressing

5. Direct Addressing

6. Register Addressing

6. Register Indirect Addressing

7. Implied Addressing

1. Immediate Addressing:

In immediate addressing mode, the data is specified in the instruction itself.

The data will be a part of the program instruction.

EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI

SP, 2700H.

2. Direct Addressing:

In direct addressing mode, the address of the data is specified in the

instruction. The data will be in memory. In this addressing mode, the program

instructions and data can be stored in different memory.

EX. LDA 1050H - Load the data available in memory location 1050H in to

accumulator; SHLD 3000H

3. Register Addressing:

In register addressing mode, the instruction specifies the name of the register

in which the data is available.

EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

In register indirect addressing mode, the instruction specifies the name of the

register in which the address of the data is available. Here the data will be in

memory and the address will be in the register pair.


EX. MOV A, M - The memory data addressed by H L pair is moved to A

register. LDAX B.

5. Implied Addressing:

In implied addressing mode, the instruction itself specifies the data to be

operated.

EX. CMA - Complement the content of accumulator; RAL

2. Describe with suitable example the operation of stack. (AUC MAY 2012)

The Stack

•The stack is an area of memory identified by the programmer for temporary storage

of information.

•The stack is a LIFO structure. Last In First Out.

• The stack normally grows backwards into memory. In other words, the programmer

defines the bottom of the stack and the stack grows up into reducing address range.


Given that the stack grows backwards into memory, it is customary to place the

bottom of the stack at the end of memory to keep it as far away from user programs

as possible.

•In the 8085, the stack is defined by setting the SP (Stack Pointer) register.

•LXI SP, FFFFH

•This sets the Stack Pointer to location FFFFH (end of memory for the 8085).

•The Size of the stack is limited only by the available memory.

Saving Information on the Stack

•Information is saved on the stack by PUSHing it on.It is retrieved from the stack by

POPing it off.

•The 8085 provides two instructions: PUSH and POP for storing information on the

stack and

retrieving it back.Both PUSH and POP work with register pairs ONLY

The PUSH Instruction

PUSH B (1 Byte Instruction)

– Decrement SP

– Copy the contents of register B to the memory location pointed to by SP

– Decrement SP

– Copy the contents of register C to the memory location pointed to by SP


The POP Instruction

POP D (1 Byte Instruction)

– Copy the contents of the memory location pointed to by the SP to register E

– Increment SP

– Copy the contents of the memory location pointed to by the SP to register D

– Increment SP

Operation of the Stack

• During pushing, the stack operates in a “decrement then store” style.

– The stack pointer is decremented first, then the information is placed on the stack.

• During poping, the stack operates in a “use then increment” style.

–The information is retrieved from the top of the the stack and then the pointer is

incremented.

• The SP pointer always points to “the top of the stack”.

LIFO

•The order of PUSHs and POPs must be opposite of each other in order to retrieve

information back into it s original location.

PUSH B

PUSH D

...

POP D


POP B

•Reversing the order of the POP instructions will result in the exchange of the

contents of BC and DE.

The PSW Register Pair

•The 8085 recognizes one additional register pair called the PSW (Program Status

Word).

–This register pair is made up of the Accumulator and the Flags registers.

•It is possible to push the PSW onto the stack, do whatever operations are needed,

then POP it off of the stack.

–The result is that the contents of the Accumulator and the status of the Flags are

returned to what they were before the operations were executed.

PUSH PSW Register Pair

• PUSH PSW (1 Byte Instruction)

–Decrement SP

–Copy the contents of register A to the memory location pointed to by SP

–Decrement SP

–Copy the contents of Flag register to the memory location pointed to by SP

Pop PSW Register Pair

• POP PSW (1 Byte Instruction)


–Copy the contents of the memory location pointed to by the SP to Flag register

–Increment SP

–Copy the contents of the memory location pointed to by the SP to register A

–Increment SP

3. Describe with suitable examples the data transfer, loading & storing instructions.

(AUC MAY 2012)

Instruction set of 8085 is classified as

Data transfer or copy instructions

Arithmetic instructions


Logical instructions

Branching instructions

Machine Control instructions

DATA TRANSFER INSTRUCTIONS

Move 8 bit Register

MOV Rd, Rs: This instruction copies the contents of the source M, Rs register

into the destination register; the contents of Rd, M the source register are not

altered. If one of the operands is a memory location, its location is specified by

the contents of the HL registers.

Example: MOV B, C or MOV B, M

Move immediate 8-bit

MVI Rd, data: The 8-bit data is stored in the destination register or M, data

memory. If the operand is a memory location, its location is specified by the

contents of the HL registers.

Example: MVI B, 57H or MVI M, 57H

Load accumulator

LDA 16-bit address: The contents of a memory location, specified by a 16-bit

address in the operand, are copied to the accumulator. The contents of the

source are not altered.

Example: LDA 2034H

Load accumulator indirect

LDAX B/D Reg. pair: The contents of the designated register pair point to a

memory location. This instruction copies the contents of that memory location

into the accumulator. The contents of either the register pair or the memory

location are not altered.

Example: LDAX B

Load register pair immediate

LXI Reg. pair, 16-bit data: The instruction loads 16-bit data in the register pair

designated in the operand.

Example: LXI H, 2034H or LXI H, XYZ

Load H and L registers direct

LHLD 16-bit address: The instruction copies the contents of the memory

location pointed out by the 16-bit address into register L and copies the


contents of the next memory location into register H. The contents of source

memory locations are not altered.

Example: LHLD 2040H

Store accumulator direct

STA 16-bit address: The contents of the accumulator are copied into the

memory location specified by the operand. This is a 3-byte instruction, the

second byte specifies the low-order address and the third byte specifies the

high-order address.

Example: STA 4350H

Store accumulator indirect

STAX Reg. pair: The contents of the accumulator are copied into the memory

location specified by the contents of the operand (register pair). The contents of

the accumulator are not altered.

Example: STAX B

Store H and L registers direct

SHLD 16-bit address: The contents of register L are stored into the memory

location specified by the 16-bit address in the operand and the contents of H

register are stored into the next memory location by incrementing the operand.

The contents of registers HL are not altered. This is a 3-byte instruction, the

second byte specifies the low-order address and the third byte specifies the

high-order address.

Example: SHLD 2470H

Exchange H and L with D and E

XCHG none: The contents of register H are exchanged with the contents of

register D, and the contents of register L are exchanged with the contents of

register E.

Example: XCHG

Copy H and L registers to the stack pointer

SPHL none: The instruction loads the contents of the H and L registers into the

stack pointer register, the contents of the H register provide the high-order

address and the contents of the L register provide the low-order address. The

contents of the H and L registers are not altered.

Example: SPHL

Exchange H and L with top of stack


XTHL none: The contents of the L register are exchanged with the stack

location pointed out by the contents of the stack pointer register. The contents

of the H register are exchanged with the next stack location (SP+1); however,

the contents of the stack pointer register are not altered.

Example: XTHL

Push register pair onto stack

PUSH Reg. pair: The contents of the register pair designated in the operand

are copied onto the stack in the following sequence. The stack pointer register

is decremented and the contents of the high order register (B, D, H, A) are

copied into that location. The stack pointer register is decremented again and

the contents of the low-order register (C, E, L, flags) are copied to that location.

Example: PUSH B or PUSH A

Pop off stack to register pair

POP Reg. pair: The contents of the memory location pointed out by the stack

pointer register are copied to the low-order register (C, E, L, status flags) of the

operand. The stack pointer is incremented by 1 and the contents of that

memory location are copied to the high-order register (B, D, H, A) of the

operand. The stack pointer register is again incremented by 1.

Example: POP H or POP A

Output data from accumulator to a port with 8-bit address

OUT 8-bit port address: The contents of the accumulator are copied into the

I/O port specified by the operand.

Example: OUT F8H

IN 8-bit port address: Input data to accumulator from a port with 8-bit address

The contents of the input port designated in the operand are read and loaded

into the accumulator.

Example: IN 8CH

ARITHMETIC INSTRUCTIONS

Add register or memory to accumulator

ADD R: The contents of the operand (register or memory) are M added to the

contents of the accumulator and the result is stored in the accumulator. If the


operand is a memory location, its location is specified by the contents of the HL

registers. All flags are modified to reflect the result of the addition.

Example: ADD B or ADD M

Add register to accumulator with carry

ADC R: The contents of the operand (register or memory) and M the Carry flag

are added to the contents of the accumulator and the result is stored in the

accumulator. If the operand is a memory location, its location is specified by the

contents of the HL registers. All flags are modified to reflect the result of the

addition.

Example: ADC B or ADC M

Add immediate to accumulator

ADI 8-bit data: The 8-bit data (operand) is added to the contents of the

accumulator and the result is stored in the accumulator. All flags are modified to

reflect the result of the addition.

Example: ADI 45H

Add immediate to accumulator with carry

ACI 8-bit data: The 8-bit data (operand) and the Carry flag are added to the

contents of the accumulator and the result is stored in the accumulator. All flags

are modified to reflect the result of the addition.

Example: ACI 45H

Add register pair to H and L registers

DAD Reg. pair: The 16-bit contents of the specified register pair are added to

the contents of the HL register and the sum is stored in the HL register. The

contents of the source register pair are not altered. If the result is larger than 16

bits, the CY flag is set. No other flags are affected.

Example: DAD H

Subtract register or memory from accumulator

SUB R: The contents of the operand (register or memory) are M subtracted

from the contents of the accumulator, and the result is stored in the

accumulator. If the operand is a memory location, its location is specified by the

contents of the HL registers. All flags are modified to reflect the result of the

subtraction.

Example: SUB B or SUB M

Subtract source and borrow from accumulator


SBB R: The contents of the operand (register or memory ) and M the Borrow

flag are subtracted from the contents of the accumulator and the result is

placed in the accumulator. If the operand is a memory location, its location is

specified by the contents of the HL registers. All flags are modified to reflect the

result of the subtraction.

Example: SBB B or SBB M

Subtract immediate from accumulator

SUI 8-bit data: The 8-bit data (operand) is subtracted from the contents of the

accumulator and the result is stored in the accumulator. All flags are modified to

reflect the result of the subtraction.

Example: SUI 45H

Subtract immediate from accumulator with borrow

SBI 8-bit data: The 8-bit data (operand) and the Borrow flag are subtracted

from the contents of the accumulator and the result is stored in the

accumulator. All flags are modified to reflect the result of the subtraction.

Example: SBI 45H

Increment register or memory by 1

INR R: The contents of the designated register or memory) are M incremented

by 1 and the result is stored in the same place. If the operand is a memory

location, its location is specified by the contents of the HL registers.

Example: INR B or INR M

Increment register pair by 1

INX R: The contents of the designated register pair are incremented by 1 and

the result is stored in the same place.

Example: INX H

Decrement register or memory by 1

DCR R: The contents of the designated register or memory are M decremented

by 1 and the result is stored in the same place. If the operand is a memory

location, its location is specified by the contents of the HL registers.

Example: DCR B or DCR M

Decrement register pair by 1

DCX R: The contents of the designated register pair are decremented by 1 and

the result is stored in the same place.

Example: DCX H


Decimal adjust accumulator

DAA none : The contents of the accumulator are changed from a binary value

to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that

uses the auxiliary flag to perform the binary to BCD conversion, and the

conversion procedure is described below. S, Z, AC, P, CY flags are altered to

reflect the results of the operation. If the value of the low-order 4-bits in the

accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the

low-order four bits. If the value of the high-order 4-bits in the accumulator is

greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order

four bits.

Example: DAA

BRANCHING INSTRUCTIONS

Jump unconditionally

JMP 16-bit address: The program sequence is transferred to the memory

location

specified by the 16-bit address given in the operand.

Example: JMP 2034H or JMP XYZ

Jump conditionally Operand 16-bit address:

The program sequence is transferred to the memory location specified by the

16-bit address given in the operand based on the specified flag of the PSW as

described below.

Example: JZ 2034H or JZ XYZ

Opcode Description Flag Status

JC Jump on Carry CY = 1

JNC Jump on no Carry CY = 0

JP Jump on positive S = 0

JM Jump on minus S = 1

JZ Jump on zero Z = 1

JNZ Jump on no zero Z = 0

JPE Jump on parity even P = 1

JPO Jump on parity odd P = 0

Unconditional subroutine call

CALL 16-bit address: The program sequence is transferred to the memory

location specified by the 16-bit address given in the operand. Before the


transfer, the address of the next instruction after CALL (the contents of the

program counter) is pushed onto the stack.

Example: CALL 2034H or CALL XYZ

Call conditionally Operand 16-bit address

The program sequence is transferred to the memory location specified by the

16-bit address given in the operand based on the specified flag of the PSW as

described below. Before the transfer, the address of the next instruction after

the call (the contents of the program counter) is pushed onto the stack.

Example: CZ 2034H or CZ XYZ


CC Call on Carry CY = 1

CNC Call on no Carry CY = 0

CP Call on positive S = 0

CM Call on minus S = 1

CZ Call on zero Z = 1

CNZ Call on no zero Z = 0

CPE Call on parity even P = 1

CPO Call on parity odd P = 0

field flag of the PSW as described below. The two bytes from the top of the

stack are copied into the program counter, and program execution begins at the

new address. Example: RZ


RC Return on Carry CY = 1

RNC Return on no Carry CY = 0

RP Return on positive S = 0

RM Return on minus S = 1

RZ Return on zero Z = 1

RNZ Return on no zero Z = 0

RPE Return on parity even P = 1

RPO Return on parity odd P = 0

Load program counter with HL contents


PCHL none: The contents of registers H and L are copied into the program

counter. The contents of H are placed as the high-order byte and the contents

of L as the low-order byte.

Example: PCHL

Restart

RST 0-7: The RST instruction is equivalent to a 1-byte call instruction to one of

eight memory locations depending upon the number. The instructions are

generally used in conjunction with interrupts and inserted using external

hardware. However these can be used as software instructions in a program to

transfer program execution to one of the eight locations. The addresses are:

Instruction Restart Address

RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

The 8085 has four additional interrupts and these interrupts generate RST

instructions internally and thus do not require any external hardware. These

instructions and their Restart addresses are:

Interrupt Restart Address TRAP 0024H

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

LOGICAL INSTRUCTIONS

Compare register or memory with accumulator

CMP R: The contents of the operand (register or memory) are M compared with

the contents of the accumulator. Both contents are preserved. The result of the

comparison is shown by setting the flags of the PSW as follows:

if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set

if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M


Compare immediate with accumulator

CPI 8-bit data: The second byte (8-bit data) is compared with the contents of

the accumulator. The values being compared remain unchanged. The result of

the comparison is shown by setting

the flags of the PSW as follows: if (A) < data: carry flag is set

if (A) = data: zero flag is set

if (A) > data: carry and zero flags are reset

Example: CPI 89H

Logical AND register or memory with accumulator

ANA R: The contents of the accumulator are logically ANDed with M the

contents of the operand (register or memory), and the result is placed in the

accumulator. If the operand is a memory location, its address is specified by the

contents of HL registers. S, Z, P are modified to reflect the result of the

operation. CY is reset. AC is set.

Example: ANA B or ANA M

Logical AND immediate with accumulator

ANI 8-bit data :The contents of the accumulator are logically ANDed with the 8-

bit data (operand) and the result is placed in the accumulator. S, Z, P are

modified to reflect the result of the operation. CY is reset. AC is set.

Example: ANI 86H

Exclusive OR register or memory with accumulator

XRA R: The contents of the accumulator are Exclusive ORed with M the

contents of the operand (register or memory), and the result is placed in the



operation. CY and AC are reset.

Example: XRA B or XRA M

Exclusive OR immediate with accumulator

XRI 8-bit data: The contents of the accumulator are Exclusive ORed with the 8-


modified to reflect the result of the operation. CY and AC are reset.

Example: XRI 86H

Logical OR register or memory with accumulator


ORA R:The contents of the accumulator are logically ORed with M the contents

of the operand (register or memory), and the result is placed in the



operation. CY and AC are reset.

Example: ORA B or ORA M

Logical OR immediate with accumulator

ORI 8-bit data The contents of the accumulator are logically ORed with the 8-


modified to reflect the result of the operation. CY and AC are reset.

Example: ORI 86H

Rotate accumulator left

RLC none: Each binary bit of the accumulator is rotated left by one position. Bit

D7 is placed in the position of D0 as well as in the Carry flag. CY is modified

according to bit D7. S, Z, P,AC are not affected.

Example: RLC

Rotate accumulator right

RRC none: Each binary bit of the accumulator is rotated right by one position.

Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified

according to bit D0. S, Z, P,AC are not affected.

Example: RRC

Rotate accumulator left through carry

RAL none: Each binary bit of the accumulator is rotated left by one position

through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is

placed in the least significant position D0. CY is modified according to bit D7. S,

Z, P, AC are not affected.

Example: RAL

Rotate accumulator right through carry

RAR none: Each binary bit of the accumulator is rotated right by one position

through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is

placed in the most significant position D7. CY is modified according to bit D0. S,

Z, P, AC are not affected.

Example: RAR

Complement accumulator


CMA none: The contents of the accumulator are complemented. No flags are

affected.

Example: CMA

Complement carry

CMC none: The Carry flag is complemented. No other flags are affected.

Example: CMC

Set Carry

STC none: The Carry flag is set to 1. No other flags are affected.

Example: STC

CONTROL INSTRUCTIONS

No operation

NOP none: No operation is performed. The instruction is fetched and decoded.

However no operation is executed.

Example: NOP

Halt and enter wait state

HLT none: The CPU finishes executing the current instruction and halts any

further execution. An interrupt or reset is necessary to exit from the halt state.

Example: HLT

Disable interrupts

DI none: The interrupt enable flip-flop is reset and all the interrupts except the

TRAP are disabled. No flags are affected.

Example: DI

Enable interrupts

EI none: The interrupt enable flip-flop is set and all interrupts are enabled. No

flags are affected. After a system reset or the acknowledgement of an interrupt,

the interrupt enable flipflop is reset, thus disabling the interrupts. This

instruction is necessary to reenable the interrupts (except TRAP).

Example: EI

4. Write an assembly language program for arranging an array of 8 bit unsigned

number in ascending order. (AUC MAY 2012)

Program to sort the numbers in ascending order

Explanation :


Consider that a block of N words is present. Now we have to arrange these N

words in ascending order, Let N = 4 for

example. We will use HL as pointer to point the block of N words.

Initially in the first iteration we compare first number with the second

number. If first number < second number, don’t interchange the contents,

otherwise if first number > second number swap the contents.

In the next iteration we go on comparing the first number with third number.

If first number < third number, don’t inter

change the contents. If first number

> third number then swapping will be done.

Since the first two numbers are in ascending order the third number will go to

first place, first number in second place and second number will come in third

place in the seco

nd iteration only if first number > third number.

In the next iteration first number is compared with fourth number. So

comparisons are done till all N numbers are arranged in ascending order. This

method requires approximately n comparisons.

Algorithm

Step I : Initialize the number of elements counter.

Step II : Initialize the number of comparisons counter.

Step III : Compare the elements. If first element < second element goto

step VIII else goto step V for(ASC). If first element > second element goto step

VIII else goto step V for (DES)

Step IV : Swap the elements.

Step V : Decrement the comparison counter.

Step VI : Is count = 0 ? if yes goto step VIII else goto step IV.

Step VII : Insert the number in proper position

Step VIII : Increment the number of elements counter.

Step IX : Is count = N ? If yes, goto step XI else goto step II

Step X : Store the result.

Step XI : Stop.

Ascending order Program:

Instruction Comment


MVI B, 09 ; Initialize counter 1

START: LXI H, D000H ; Initialize memory pointer

MVI C, 09H ; Initialize counter 2

BACK: MOV A, M ; Get the number in accumulator

INX H ; Increment memory pointer

CMP M ; Compare number with next number

JC SKIP ; If less, don’t interchange

JZ SKIP ; If equal, don’t interchange

MOV D, M ; Otherwise swap the contents

MOV M, A ; Interchange numbers

DCX H

MOV M, D

INX H ; Increment pointer to next memory location

SKIP: DCR C ; Decrement counter 2

JNZ BACK ; If not zero, repeat

DCR B ; Decrement counter 1

JNZ START ; If not zero, repeat

HLT ; Terminate program execution

5. Write a program to count from 0 to 9 with one second delay between each count.

At the count of 9, the counter should reset itself to 0 and repeat the sequence

continuously. Assume the clock frequency is 1 MHz. (AUC NOV 2011)

6. Write a program with a flow chart to multiply two 8 bit numbers. (AUC NOV 2011)

7. Compare the similarities & differences of CALL & RET instructions with PUSH &

POP instructions. (AUC NOV 2011)

8. Sixteen bytes are scored in memory locations at XX50h to XX5Fh. Transfer the

entire block of data to new memory locations starting at XX70h. (AUC NOV 2011)

9. Describe the instruction format & addressing modes of 8085 microprocessor.

(AUC MAY 2011)

10. Write an assembly language program based on 8085 microprocessor instruction

set to search the smallest data in a set. (AUC MAY 2011)


11. With suitable example, discuss about 8085 microprocessor instructions used for

data manipulation. (AUC MAY 2011)

12. Write an assembly language program based on 8085 microprocessor instruction

set to find the square root of data from 1 to n using lookup table. (AUC MAY

2011)

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