mac7200 microcontroller family reference manual · 2018. 12. 17. · mac7200 microcontroller family...

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor i

MAC7200RMRev. 2

04/2007

MAC7200 Microcontroller FamilyReference Manual

Devices Supported:PAC7202 PAC7212

MAC7242

PAC7201 PAC7211MAC7241

This document covers the following mask sets:

MAC72x2 – 0M34A, 1M34A, 0M84D, 1M84D

MAC72x1 – 0M19G


ii Freescale Semiconductor

Contents

Figures .............................................................................................................................. xliTables................................................................................................................................ liii

Preface

Document Structure ......................................................................................................... lxvHow To Use This Document............................................................................................ lxvConventions .................................................................................................................... lxviTerminology.................................................................................................................... lxviRegister Descriptions .................................................................................................... lxxiii

Revision History

Content Changes by Document Version ...................................................................... lxxvii

Chapter 1 Introduction

1.1 Overview..............................................................................................................................11.2 Features ................................................................................................................................11.2.1 Performance Summary ....................................................................................................81.3 Modes of Operation .............................................................................................................91.3.1 Single Chip mode (Unsecured)......................................................................................101.3.2 Single Chip mode (Secured) ..........................................................................................101.3.3 PBL Chip mode (Secured).............................................................................................101.3.4 PBL Chip mode (Unsecured).........................................................................................111.3.5 Expanded Chip mode (Secured) ....................................................................................111.3.6 Expanded Chip mode (Unsecured) ................................................................................111.3.7 Low Power Modes .........................................................................................................111.3.8 Debug Mode ..................................................................................................................121.4 Block Diagram...................................................................................................................131.5 System Memory Map.........................................................................................................14

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Chapter 2 Modes of Operation

2.1 Introduction........................................................................................................................152.2 MCU Hardware Configuration Summary..........................................................................152.3 Security ..............................................................................................................................152.3.1 Operation of the Secured Microcontroller .....................................................................162.3.1.1 Single Chip Secured Mode ........................................................................................162.3.1.2 Executing from External Memory .............................................................................162.3.2 Securing the Microcontroller .........................................................................................162.3.3 Unsecuring the Microcontroller.....................................................................................162.3.3.1 Software Unsecure.....................................................................................................172.3.3.2 JTAG Lockout Recovery ...........................................................................................172.4 MCU Mode Selection ........................................................................................................172.4.1 Normal Single Chip Mode.............................................................................................182.4.2 Secured Single Chip Mode ............................................................................................182.4.3 Normal Primary Bootloader Mode ................................................................................192.4.4 Secured Primary Bootloader Mode................................................................................192.4.5 Normal Expanded Mode................................................................................................192.4.6 Secured Expanded Mode ...............................................................................................202.5 Oscillator Type Selection...................................................................................................202.6 Nexus Port Selection..........................................................................................................202.7 External Bus Configuration ...............................................................................................212.8 Low Power Modes .............................................................................................................212.8.1 Doze ...............................................................................................................................222.8.2 Run.................................................................................................................................222.9 Debug Mode ......................................................................................................................22

Chapter 3 Low Power Modes

3.1 Low Power Modes Introduction ........................................................................................233.2 Run Mode ..........................................................................................................................233.3 Doze Mode.........................................................................................................................233.4 Disabled Mode...................................................................................................................243.5 System Wakeup..................................................................................................................253.6 Low Power Mode Differences from MAC71xx ................................................................253.7 Low Power Mode Summary ..............................................................................................263.8 Special Notes on Entering and Exiting Power Modes .......................................................26

Chapter 4 Signal Description

4.1 Device Pinout.....................................................................................................................29


iv Freescale Semiconductor

4.2 Signal Properties Summary ..............................................................................................334.3 Detailed Signal Descriptions .............................................................................................394.3.1 EXTAL, XTAL — Oscillator Pins.................................................................................394.3.2 RESET — External Reset Pin .......................................................................................394.3.3 XFC — PLL Loop Filter Pin .........................................................................................394.3.4 TDI — Test Data In Pin.................................................................................................404.3.5 TDO — Test Data Output Pin........................................................................................404.3.6 TCK — Test Clock Pin..................................................................................................404.3.7 TMS — Test Mode Pin..................................................................................................404.3.8 PA[0:7] / DATA[0:7] — Port A I/O Pins and external Databus ....................................404.3.9 PA[8] / DATA[8] / PCS[4] — Port A I/O Pin, External Databus, and DSPI_B............404.3.10 PA[9] / DATA[9] / PCS[3] / NEX1EVTI — Port A I/O Pin, External Databus,

DSPI_B and Nexus Primary ......................................................................................414.3.11 PA[10:15] / DATA[10:15] — Port A I/O Pins and external Databus ............................414.3.12 PB[0] / SDA / NEX1MCKO — Port B I/O Pin, IIC and Nexus Primary .....................414.3.13 PB[1] / SCL / NEX1EVTO — Port B I/O Pin, IIC and Nexus Primary .......................414.3.14 PB[2] / SIN_A / NEX1MSEO — Port B I/O Pin, DSPI_A and Nexus Primary...........414.3.15 PB[3] / SOUT_A / NEX1RDY — Port B I/O Pin, DSPI_A and Nexus Primary .........424.3.16 PB[4] / SCK_A — Port B I/O Pin and DSPI_A............................................................424.3.17 PB[5] / PCS[0] / SS[0] — Port B I/O Pin and DSPI_A ................................................424.3.18 PB[6:7] / PCS[1:2] — Port B I/O Pin and DSPI_A ......................................................424.3.19 PB[8] / PCS[5] / PCSS — Port B I/O Pin and DSPI_A ................................................424.3.20 PB[9] / PCS0 / SS[1] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..434.3.21 PB[10] / PCS[5] / PCSS — Port B I/O Pin and DSPI_B ..............................................434.3.22 PB[11] / PCS[2] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..........434.3.23 PB[12] / PCS[1] — Port B I/O Pin and DSPI_B...........................................................434.3.24 PB[13] / SCK_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary .........444.3.25 PB[14] / SOUT_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary.......444.3.26 PB[15] / SIN_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary...........444.3.27 PC[0:2] / ADDR[0:2] — Port C I/O Pins and External address bus .............................444.3.28 PC[3] / ADDR[3] / NEX2EVTI — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................444.3.29 PC[4] / ADDR[4] / NEX2MCKO — Port C I/O Pins, External Address Bus and

Nexus Secondary .......................................................................................................454.3.30 PC[5] / ADDR[5] / NEX2EVTO — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................454.3.31 PC[6] / ADDR[6] / NEX2MSEO — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................454.3.32 PC[7] / ADDR[7] / NEX2RDY — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................454.3.33 PC[8:15] / ADDR[8:15] / MDO[0:7] — Port C I/O Pins, External Address Bus and

Nexus Secondary .......................................................................................................464.3.34 PD[0] / BWE[0] / MODB — Port D I/O Pin, External Bus Control & Mode

Selection ....................................................................................................................46


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4.3.35 PD[1] / BWE[1] / MODA — Port D I/O Pin, External Bus Control & Mode Selection ....................................................................................................................46

4.3.36 PD[2] / CLKOUT / XCLKS — Clock Out and Oscillator Selection ............................464.3.37 PD[3] / XIRQ / NMI — Port D I/O Pin, High Priority Interrupt and Non-maskable

Interrupt .....................................................................................................................474.3.38 PD[4] / IRQ — Port D I/O Pin, and Maskable Interrupt ...............................................474.3.39 PD[5:10] / ADDR[16:21] — Port D I/O Pins and External Address Bus.....................474.3.40 PD[11] / OE — Port D I/O Pin and External Bus Control ............................................474.3.41 PD[12] / Burst — Port D I/O Pin and External Bus Control.........................................474.3.42 PD[13] / TA — Port D I/O Pin and External Bus Control ............................................474.3.43 PD[15] / CS0 — Port D I/O Pin and External Bus Control...........................................484.3.44 PD[15] / R/W — Port D I/O Pin and External Bus Control ..........................................484.3.45 PE[0:15] / AN_A[00:15]— Port E I/O Pins and ATD_A..............................................484.3.46 PF[0] / EMIOS[0] / NEXPS — Port F I/O Pins, eMIOS Channels and Nexus Port

Selection ....................................................................................................................484.3.47 PF[1] / EMIOS[1] / NEXPR — Port F I/O Pins, eMIOS Channels and Nexus Present

Selection ....................................................................................................................484.3.48 PF[2] / EMIOS[2] / AUTOACK — Port F I/O Pins, eMIOS Channels and FlexBus

Ack Selection.............................................................................................................494.3.49 PF[3] / EMIOS[3] / AUTOACK — Port F I/O Pins, eMIOS Channels and FlexBus

Port Size.....................................................................................................................494.3.50 PF[4:7] / EMIOS[4:7] — Port F I/O Pins and eMIOS Channels ..................................494.3.51 PF[8] / PCS[5] / PCSS — Port F I/O Pin and DSPI_C .................................................494.3.52 PF[9] / PCS[3] — Port F I/O Pin and DSPI_C..............................................................504.3.53 PF[10] / PCS[2] — Port F I/O Pin and DSPI_C............................................................504.3.54 PF[11] / SCK_C — Port F I/O Pin and DSPI_C ...........................................................504.3.55 PF[12] / PCS[1] — Port F I/O Pin and DSPI_C............................................................504.3.56 PF[13] / SOUT_C — Port F I/O Pin and DSPI_C ........................................................504.3.57 PF[14] / PCS[0] / SS[0] — Port F I/O Pin and DSPI_C ...............................................504.3.58 PF[15] / SIN_C — Port F I/O Pin and DSPI_C ............................................................514.3.59 PG[0] / RXD_B — PORT G I/O Pin and ESCI_B........................................................514.3.60 PG[1] / TXD_B — PORT G I/O Pin and ESCI_B........................................................514.3.61 PG[2] / RXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus Primary.......514.3.62 PG[3] / TXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus Primary.......514.3.63 PG[4] / TCNTX_A / NEX1MDO[2] — PORT G I/O Pin, FlexCAN_A and Nexus

Primary ......................................................................................................................524.3.64 PG[5] / CNRX_A — PORT G I/O Pin and FlexCAN_A..............................................524.3.65 PG[6] / CNTX_B — PORT G I/O Pin and FlexCAN_B ..............................................524.3.66 PG[7] / CNRX_B — PORT G I/O Pin and FlexCAN_B ..............................................524.3.67 PG[8] — PORT G I/O Pin .............................................................................................524.3.68 PG[9] — PORT G I/O Pin .............................................................................................534.3.69 PG[10] — PORT G I/O Pin ...........................................................................................534.3.70 PG[11] — PORT G I/O Pin ...........................................................................................534.3.71 PG[12] / PCS[4] — Port G I/O Pin and DSPI_A ..........................................................534.3.72 PG[13] / PCS[3] — Port G I/O Pin and DSPI_A ..........................................................53


vi Freescale Semiconductor

4.3.73 PG[14] / PCS[4] — Port G I/O Pin and DSPI_B ..........................................................534.3.74 PG[15] / PCS[3] — Port G I/O Pin and DSPI_B ..........................................................544.4 Power Supply Pins .............................................................................................................544.4.1 VPP — Power For Flash Program and Erase ................................................................544.4.2 VDDX1-4,6-11, VSSX1-11 (except VDDX5) — Power and Ground Pins for

I/O Drivers .................................................................................................................544.4.3 VDDX5 /VDDAPASS — Power Pin for I/O Drivers and Control Voltage for Internal

Pass Transistors..........................................................................................................544.4.4 VDDR/VREGEN — Power Pin for the Internal Voltage Regulator .............................544.4.5 VDD15a, VSS15a — Core Power Pins .........................................................................554.4.6 VDD15c/VDDF, VSS15c/VSSF — Core and Flash Logic Power Pins........................554.4.7 VDD33/VFLASH, VSS33 — Flash and I/O Pre-Driver Power Pins............................554.4.8 VDDA, VSSA — Power Supply Pins for ATD and Voltage Regulator Control...........554.4.9 VRH, VRL — ATD Reference Voltage Input Pins .......................................................564.4.10 REFBYPC — ATD Reference Voltage Bypass Capacitor ............................................564.4.11 VDDPLL, VSSPLL — Power Supply Pins for PLL.....................................................564.4.12 VSS-TEST — Power Supply Pin ..................................................................................56

Chapter 5 System Clock Description

5.1 Clocks Introduction............................................................................................................595.2 Clock Generation ...............................................................................................................615.2.1 Clock Source Selection..................................................................................................635.2.1.1 ALC 1:1 Mode...........................................................................................................645.2.1.2 ALC PLL Mode.........................................................................................................645.2.1.3 External Clock 1:1 Mode...........................................................................................655.2.1.4 External Clock PLL Mode.........................................................................................665.2.2 Self Clock Mode (SCM)................................................................................................675.2.3 Crystal Monitor..............................................................................................................675.2.4 Clock Quality Checker...................................................................................................675.3 Clock Usage.......................................................................................................................675.4 Clock Gating ......................................................................................................................685.5 Oscillator............................................................................................................................69

Chapter 6 Resets

6.1 Resets Introduction ............................................................................................................716.2 Power On Reset (POR) ......................................................................................................736.3 System Reset......................................................................................................................736.4 Debug Reset .......................................................................................................................736.5 Software Reset ...................................................................................................................746.6 Reset Implementation ........................................................................................................74


Freescale Semiconductor vii

6.7 Effects of Reset ..................................................................................................................756.7.1 Hardware Configuration ................................................................................................756.7.2 Register States................................................................................................................756.7.3 Peripheral Disabled State...............................................................................................756.7.4 I/O pins ..........................................................................................................................766.7.5 Memories .......................................................................................................................766.8 System Configuration at Reset ..........................................................................................766.9 Resets Differences from MAC71xx...................................................................................77

Chapter 7 Exceptions

7.1 Introduction........................................................................................................................797.2 Exception Handling ...........................................................................................................797.2.1 Reset...............................................................................................................................807.2.2 Undefined Instruction ....................................................................................................807.2.3 Software Interrupt ..........................................................................................................807.2.4 Prefetch (Instruction) Abort...........................................................................................807.2.5 Data Abort......................................................................................................................817.2.6 IRQ.................................................................................................................................817.2.7 FIQ.................................................................................................................................817.3 Interrupts ............................................................................................................................827.3.1 Interrupt Clearing...........................................................................................................867.3.2 XIRQ and IRQ...............................................................................................................867.3.3 PIT RTI and Timer 4......................................................................................................867.3.4 Non-Maskable Interrupt (NMI) .....................................................................................867.4 Exceptions Differences from the MAC71xx .....................................................................90

Chapter 8 Debug

8.1 Debug Introduction ............................................................................................................918.2 Debug Features ..................................................................................................................918.3 Debug Protocol ..................................................................................................................918.4 Debug Implementation ......................................................................................................918.4.1 JTAG Interface...............................................................................................................918.4.1.1 TCK Routing .............................................................................................................938.4.1.2 TMS Routing .............................................................................................................938.4.1.3 TDI Routing...............................................................................................................938.4.1.4 TDO Routing .............................................................................................................948.4.2 Synchronization .............................................................................................................958.4.3 Debug Reset...................................................................................................................978.5 Debug External Pins ..........................................................................................................978.6 Debug Bus Aborts..............................................................................................................97


viii Freescale Semiconductor

8.7 Debug Differences from MAC71xx ..................................................................................978.8 Debug Application Usage ..................................................................................................978.8.1 ARM Debug Overview..................................................................................................988.8.2 Entering Debug mode ....................................................................................................998.8.3 Exiting Debug mode ....................................................................................................1008.8.4 Nexus Low Power State...............................................................................................1008.8.5 Debug Shift Register SC4............................................................................................1018.8.6 Using the JTAG Interface ............................................................................................1018.8.7 JTAG Pad Control........................................................................................................1018.8.8 Resetting Debug Logic ................................................................................................102

Chapter 9 Device Memory Map

9.1 Memory Map Example ....................................................................................................1049.2 Normal Single Chip Mode ...............................................................................................1059.3 Normal Primary Bootloader Mode ..................................................................................1079.4 Normal Expanded Mode ..................................................................................................1089.5 Secured Single Chip Mode ..............................................................................................1099.6 Secured Primary Bootloader Mode..................................................................................1109.7 Secured Expanded Mode .................................................................................................1109.8 Accessing registers ..........................................................................................................1129.8.1 32-bit Register Accesses..............................................................................................1129.8.2 16-bit Register Accesses..............................................................................................1129.8.3 8-bit register accesses ..................................................................................................1139.9 Peripheral Bus Memory Map...........................................................................................1139.10 SRAM Memory Map .......................................................................................................1149.11 FlexBus Memory Map .....................................................................................................1159.12 Flash Main Array Memory Map......................................................................................1159.13 Shadow Block Memory Map...........................................................................................1179.14 Boot Assist Module (BAM) Memory Map......................................................................1189.15 Exception Table Memory Map ........................................................................................1189.16 Memory Map Relocation .................................................................................................1199.16.1 System Memory Map Combinations ...........................................................................1199.16.2 Changing Chip Modes .................................................................................................1209.16.3 Resource Relocation Summary....................................................................................1209.16.3.1 FlexBus ....................................................................................................................1209.16.3.2 Flash Main Array.....................................................................................................1209.16.3.3 Shadow Block..........................................................................................................1209.16.3.4 SRAM......................................................................................................................1219.16.4 Programming the AAMR register in the MCM...........................................................1219.17 Exception Table ...............................................................................................................1229.18 System Boot Sequence.....................................................................................................1239.18.1 Programming with a Bootloader..................................................................................123


Freescale Semiconductor ix

9.18.2 “Normal” Boot with a Bootloader ...............................................................................124

Chapter 10 ARM7TDMI-S Core

10.1 Introduction......................................................................................................................12710.2 ARM7 Features................................................................................................................12710.3 ARM7 Implementation ....................................................................................................12710.4 ARM7 External Pins ........................................................................................................12810.5 ARM7 Bus Aborts ...........................................................................................................12810.6 ARM7 Application Usage ...............................................................................................12810.6.1 Register Bank Initialization .........................................................................................128

Chapter 11 A7S Nexus3 Module

11.1 Introduction......................................................................................................................12911.1.1 A7S Nexus3 Overview ................................................................................................13011.1.2 Nexus Feature List .......................................................................................................13011.1.3 Modes of Operation .....................................................................................................13111.1.3.1 Reset ........................................................................................................................13111.1.3.2 Normal .....................................................................................................................13111.1.3.3 Disabled ...................................................................................................................13111.1.4 TCODEs supported......................................................................................................13111.2 Nexus Protocol.................................................................................................................13511.3 Nexus Implementation.....................................................................................................13511.3.1 Nexus Port Replacement..............................................................................................13611.3.2 TAP Controller Encodings...........................................................................................13611.4 Nexus Integration.............................................................................................................13711.4.1 Nexus Integration and SoC Security............................................................................13811.4.2 Nexus Integration and FlexBus Port Sizing.................................................................13811.4.3 Nexus Integration and Port Control .............................................................................13811.5 Nexus External Pins.........................................................................................................13911.5.1 MDO - Message Data (Output) ...................................................................................13911.5.2 MSEO - Message Start/End (Active low output) ........................................................13911.5.3 EVTI - Event In (Active low input).............................................................................13911.5.4 EVTO - Event Out (Active low output).......................................................................13911.5.5 RDY - DMA Ready (Active low output).....................................................................14011.5.6 MCKO - Message Clock (Output)...............................................................................14011.6 Nexus Bus Aborts ............................................................................................................14011.7 Nexus Differences from MAC71xx.................................................................................14011.8 Nexus Application Usage ................................................................................................14011.8.1 Nexus Configuration....................................................................................................14011.8.2 Programming the PCR Register...................................................................................141


x Freescale Semiconductor

11.8.3 Resetting Nexus ...........................................................................................................14111.8.4 Enabling Nexus............................................................................................................14111.8.5 Disabling Nexus...........................................................................................................14111.8.6 Nexus Development Status (DS) Register...................................................................14211.8.7 Unintended Activation of Nexus .................................................................................14211.9 External Signal Description .............................................................................................14311.9.1 Functional Description.................................................................................................14311.9.2 Pins Implemented ........................................................................................................14311.9.3 Pin Protocol..................................................................................................................14411.9.4 Rules for Output Messages ..........................................................................................14611.9.5 Examples......................................................................................................................14611.10 A7S Nexus3 Programmers Model ...................................................................................14811.10.1 JTAG ID Register ........................................................................................................14811.10.2 Nexus3 Register Map...................................................................................................15011.10.3 A7S Nexus3 Register Definitions................................................................................15111.10.3.1 Client Select Control (CSC) ....................................................................................15111.10.3.2 Development Control (DC) .....................................................................................15111.10.3.3 Development Status (DS) ........................................................................................15211.10.3.4 User Base Address (UBA).......................................................................................15311.10.3.5 Read/Write Access Control/Status (RWCS)............................................................15411.10.3.6 Read/Write Access Data (RWD) .............................................................................15511.10.3.7 Read/Write Access Address (RWA) ........................................................................15611.10.3.8 Watchpoint Trigger (WT) ........................................................................................15611.10.3.9 Data Trace Control (DTC).......................................................................................15711.10.3.10 Data Trace Start Address (DTSA1, DTSA2)...........................................................15811.10.3.11 Data Trace End Address (DTEA1, DTEA2) ...........................................................15911.10.3.12 Breakpoint / Watchpoint Control (BWC1, BWC2) .................................................16011.10.3.13 Breakpoint / Watchpoint Control (BWC3-6)...........................................................16111.10.3.14 Breakpoint / Watchpoint Address (BWA1-6) ..........................................................16111.10.3.15 Breakpoint / Watchpoint Address Mask (BWAM1, BWAM2)................................16211.10.3.16 Breakpoint / Watchpoint Data (BWD1, BWD2) .....................................................16211.10.3.17 Breakpoint / Watchpoint Data Mask (BWDM1, BWDM2) ....................................16211.10.3.18 Port Configuration (PCR) ........................................................................................16311.10.4 Nexus Register Access via JTAG ................................................................................16411.10.5 Programming Considerations (RESET).......................................................................16611.11 Functional Description.....................................................................................................16611.11.1 Ownership Trace..........................................................................................................16611.11.1.1 Ownership Trace Messaging (OTM).......................................................................16611.11.1.2 OTM Error Messages ..............................................................................................16611.11.1.3 OTM Flow ...............................................................................................................16711.11.2 Program Trace..............................................................................................................16711.11.2.1 Branch Trace Messaging (BTM) .............................................................................16711.11.2.1.1 ARM7 Indirect Branch Message Instructions .....................................................16811.11.2.1.2 ARM7 Direct Branch Message Instructions........................................................16811.11.2.1.3 BTM in ARM mode ............................................................................................169


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11.11.2.1.4 BTM in Thumb mode ..........................................................................................16911.11.2.2 Branch Trace Message Formats (History and Traditional)......................................16911.11.2.2.1 Indirect Branch Messages (History) ....................................................................16911.11.2.2.2 Indirect Branch Messages (Traditional) ..............................................................17011.11.2.2.3 Direct Branch Messages (Traditional).................................................................17011.11.2.2.4 Resource Full Messages ......................................................................................17011.11.2.2.5 Program Correlation Messages............................................................................17111.11.2.2.6 BTM Overflow Error Messages ..........................................................................17111.11.2.2.7 Program Trace Synchronization Messages..........................................................17111.11.2.3 BTM Operation........................................................................................................17311.11.2.3.1 Enabling Program Trace ......................................................................................17311.11.2.3.2 Addressing ...........................................................................................................17411.11.2.3.3 Branch/Predicate Instruction History (HIST)......................................................17411.11.2.3.4 Sequential Instruction Count (I-CNT).................................................................17511.11.2.3.5 Program Trace Queueing .....................................................................................17511.11.2.4 Program Trace Timing Diagrams (2 MDO / 1 MSEO configuration).....................17511.11.3 Data Trace....................................................................................................................17611.11.3.1 Data Trace Messaging (DTM).................................................................................17611.11.3.2 DTM Message Formats ...........................................................................................17711.11.3.2.1 Data Write Messages ...........................................................................................17711.11.3.2.2 Data Read Messages ............................................................................................17711.11.3.2.3 DTM Overflow Error Messages ..........................................................................17711.11.3.2.4 Data Trace Synchronization Messages ................................................................17811.11.3.3 DTM Operation .......................................................................................................17911.11.3.3.1 Enabling Data Trace Messaging..........................................................................17911.11.3.3.2 DTM Queueing....................................................................................................17911.11.3.3.3 Relative Addressing.............................................................................................18011.11.3.3.4 Data Trace Windowing ........................................................................................18011.11.3.3.5 ARM7 Bus Cycle Cases ......................................................................................18011.11.3.4 Data Trace Timing Diagrams (8 MDO / 2 MSEO configuration)...........................18011.11.4 Watchpoint Units .........................................................................................................18111.11.4.1 Watchpoint Generation ............................................................................................18111.11.4.1.1 Internal Watchpoint Units 1 and 2 .......................................................................18111.11.4.1.2 Internal Watchpoint Units 3 - 6 ...........................................................................18211.11.4.1.3 ARM7 Watchpoints .............................................................................................18211.11.4.2 Processor Breakpoints .............................................................................................18211.11.4.3 Watchpoint Messaging (WPM) ...............................................................................18211.11.4.3.1 Watchpoint Message............................................................................................18211.11.4.4 Watchpoint Error Message.......................................................................................18311.11.4.5 Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration)............................18411.11.5 Read/Write Access.......................................................................................................18411.11.5.1 Functional Description.............................................................................................18411.11.5.2 Read/Write Access to Internal Nexus Registers ......................................................18411.11.5.3 Memory Mapped Register Access via JTAG ..........................................................18511.11.5.3.1 Single Write Access.............................................................................................185


xii Freescale Semiconductor

11.11.5.3.2 Block Write Access .............................................................................................18611.11.5.3.3 Single Read Access .............................................................................................18711.11.5.3.4 Block Read Access ..............................................................................................18711.11.5.4 Error Handling .........................................................................................................18811.11.5.4.1 AHB Read/Write Error ........................................................................................18811.11.5.4.2 Access Termination .............................................................................................18811.11.5.4.3 Read/Write Access Error Message ......................................................................18811.11.5.5 Timing Diagram.......................................................................................................18911.11.6 System Status ...............................................................................................................18911.11.6.1 Debug Status Messages ...........................................................................................18911.12 IEEE 1149.1 State Machine and RD/WR Sequences ......................................................19011.12.1 JTAG State Machine ....................................................................................................19011.12.2 JTAG Sequence for Accessing Internal Nexus Registers ............................................19111.12.3 JTAG Sequence for Read Access of Memory-Mapped Resources .............................19111.12.4 JTAG Sequence for Write Access of Memory-Mapped Resources.............................191

Chapter 12 Enhanced DMA Controller (eDMA) Module

12.1 Overview of the MAC7200 Implementation ...................................................................19312.1.1 eDMA Features............................................................................................................19312.1.2 eDMA Implementation ................................................................................................19412.1.3 eDMA External Pins....................................................................................................19512.1.4 eDMA Bus Aborts .......................................................................................................19512.1.5 eDMA Differences from MAC71xx............................................................................19512.1.6 eDMA Application Usage ...........................................................................................19512.1.6.1 Enabling the DMA...................................................................................................19512.1.6.2 General Operation of the DMA ...............................................................................19612.1.6.3 Configuring the DMA..............................................................................................19612.1.6.3.1 Arbitration and System Loading..........................................................................19612.1.6.3.2 Error Signalling ...................................................................................................19712.1.6.3.3 DEBUG Mode Behavior .....................................................................................19812.1.6.3.4 Transfer Control Descriptor (TCD) .....................................................................19812.1.6.3.5 Channel Completion ............................................................................................19812.1.6.3.6 Channel Activation Method.................................................................................19812.1.6.4 Using the DMA........................................................................................................19912.1.6.5 TCD Memory Initialization .....................................................................................20012.2 The SPP DMA Controller Module (SPP_DMA2)...........................................................20012.2.1 Overview......................................................................................................................20112.2.2 Features........................................................................................................................20212.2.3 External Signal Description.........................................................................................20712.2.4 Memory Map/Register Definition ...............................................................................20712.2.4.1 Register Descriptions...............................................................................................20912.2.4.1.1 DMA Control Register (DMACR) ......................................................................209


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12.2.4.1.2 DMA Error Status (DMAES) ..............................................................................21012.2.4.1.3 DMA Enable Request (DMAERQH, DMAERQL) ............................................21212.2.4.1.4 DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) .....................................21412.2.4.1.5 DMA Set Enable Request (DMASERQ).............................................................21512.2.4.1.6 DMA Clear Enable Request (DMACERQ).........................................................21512.2.4.1.7 DMA Set Enable Error Interrupt (DMASEEI)....................................................21612.2.4.1.8 DMA Clear Enable Error Interrupt (DMACEEI)................................................21712.2.4.1.9 DMA Clear Interrupt Request (DMACINT) .......................................................21712.2.4.1.10 DMA Clear Error (DMACERR) .........................................................................21812.2.4.1.11 DMA Set START Bit (DMASSRT) ....................................................................21812.2.4.1.12 DMA Clear DONE Status (DMACDNE)............................................................21912.2.4.1.13 DMA Interrupt Request (DMAINTH, DMAINTL) ............................................22012.2.4.1.14 DMA Error (DMAERRH, DMAERRL) .............................................................22112.2.4.1.15 DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63}...............................22212.2.4.1.16 Transfer Control Descriptor (TCD) .....................................................................22312.2.5 DMA Performance.......................................................................................................23212.2.6 Initialization/Application Information.........................................................................23512.2.6.1 DMA Initialization...................................................................................................23512.2.6.2 DMA Programming Errors ......................................................................................23512.2.6.3 DMA Arbitration Mode Considerations..................................................................23512.2.6.3.1 Fixed Channel Arbitration ...................................................................................23512.2.6.3.2 Round Robin Channel Arbitration.......................................................................23612.2.6.4 DMA Transfer..........................................................................................................23612.2.6.4.1 Single request ......................................................................................................23612.2.6.4.2 Multiple requests .................................................................................................23712.2.6.5 TCD Status...............................................................................................................23812.2.6.5.1 Minor loop complete ...........................................................................................23812.2.6.5.2 Active channel TCD reads...................................................................................23912.2.6.5.3 Preemption status.................................................................................................23912.2.6.6 Channel Linking ......................................................................................................24012.2.6.7 Dynamic Programming............................................................................................24012.2.6.7.1 Dynamic priority changing..................................................................................24012.2.6.7.2 Dynamic channel linking and dynamic scatter/gather.........................................24112.2.6.8 Hardware Request Release Timing..........................................................................242

Chapter 13 Miscellaneous Control Module (MCM)

13.1 Introduction......................................................................................................................24313.1.1 Overview......................................................................................................................24313.1.2 Features........................................................................................................................24313.2 Memory Map/Register Definition ...................................................................................24313.2.1 Memory Map ...............................................................................................................24413.2.2 Register Descriptions...................................................................................................245


xiv Freescale Semiconductor

13.2.2.1 Processor Core Type (PCT) .....................................................................................24513.2.2.2 Revision (REV) .......................................................................................................24613.2.2.3 AXBS Master Configuration (AMC) ......................................................................24613.2.2.4 AXBS Slave Configuration (ASC)..........................................................................24713.2.2.5 IPS Module Configuration (IMC) ...........................................................................24713.2.2.6 Miscellaneous Reset Status Register (MRSR) ........................................................24813.2.2.7 Miscellaneous Wakeup Control Register (MWCR) ................................................24913.2.2.8 Miscellaneous Software Watchdog Timer Control Register (MSWTCR) ..............25013.2.2.9 Miscellaneous Software Watchdog Timer Service Register (MSWTSR) ...............25213.2.2.10 Miscellaneous Interrupt Register (MIR)..................................................................25313.2.2.11 AXBS Address Map Register (AAMR) ..................................................................25413.2.2.12 Miscellaneous User-Defined Control Register (MUDCR)......................................25513.2.2.13 NMI Control Register (NMICR) .............................................................................25613.2.2.14 Peripheral Power Management Registers (PPMR)..................................................25713.2.2.14.1 Peripheral Power Management Set Register (PPMRS).......................................25713.2.2.14.2 Peripheral Power Management Clear Register (PPMRC)...................................25813.2.2.14.3 Peripheral Power Management Set Register 1 (PPMRS1)..................................25913.2.2.14.4 Peripheral Power Management Clear Register 1 (PPMRC1)..............................25913.2.2.14.5 Peripheral Power Management Register (PPMR{H,L}).....................................26013.2.2.14.6 Peripheral Power Management Register 1 (PPMR1{H,L})................................26113.2.2.15 ECC Registers..........................................................................................................26313.2.2.15.1 ECC Configuration Register (ECR) ....................................................................26313.2.2.15.2 ECC Status Register (ESR) .................................................................................26513.2.2.15.3 ECC Error Generation Register (EEGR).............................................................26613.2.2.15.4 Flash ECC Address Register (FEAR) .................................................................26913.2.2.15.5 Flash ECC Master Number Register (FEMR).....................................................27013.2.2.15.6 Flash ECC Attributes Register (FEAT) ...............................................................27113.2.2.15.7 Flash ECC Data Register (FEDR) .......................................................................27213.2.2.15.8 RAM ECC Address Register (REAR).................................................................27213.2.2.15.9 RAM ECC Syndrome Register (RESR)..............................................................27313.2.2.15.10 RAM ECC Master Number Register (REMR)....................................................27413.2.2.15.11 RAM ECC Attributes Register (REAT) ..............................................................27513.2.2.15.12 RAM ECC Data Register (REDR) ......................................................................27613.2.2.16 Core Data Fault Recovery Registers........................................................................27713.2.2.16.1 Core Fault Address Register (CFADR) ...............................................................27713.2.2.16.2 Core Fault Location/Interrupt Enable Register (CFLOC1).................................27813.2.2.16.3 Core Fault Location Register (CFLOC) ..............................................................27913.2.2.16.4 Core Fault Attributes Register (CFATR) .............................................................27913.2.2.16.5 Core Fault Data Register (CFDTR).....................................................................28013.3 MCM as Implemented on MAC7200 ..............................................................................28113.3.1 MCM Introduction.......................................................................................................28113.3.2 MCM Features .............................................................................................................28213.3.2.1 Processor Core Type (PCT) .....................................................................................28213.3.2.2 Revision ID (REV) ..................................................................................................28313.3.2.3 AXBS Master/Slave Configuration .........................................................................283


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13.3.2.4 Misc. Reset Status Register (MRSR).......................................................................28313.3.2.5 Misc. Wakeup Control Register (MWCR) ..............................................................28313.3.2.6 Software Watchdog Timer (SWT) ...........................................................................28313.3.2.7 AXBS Address Map Register (AAMR) ..................................................................28413.3.2.8 Misc. User-Defined Control Register (MUDCR)....................................................28413.3.2.9 ECC..........................................................................................................................28413.3.2.10 Fault Registers .........................................................................................................28413.3.2.11 Non-Maskable Interrupt (NMI) ...............................................................................28413.3.3 MCM External Pins .....................................................................................................28413.3.4 MCM Bus Aborts.........................................................................................................28413.3.5 MCM Differences from MAC71xx .............................................................................28513.3.6 MCM Application Usage.............................................................................................28613.3.6.1 Enabling the MCM ..................................................................................................28613.3.6.2 ECC..........................................................................................................................28613.3.6.3 Flash.........................................................................................................................28613.3.6.4 AAMR .....................................................................................................................28613.3.6.5 NMI..........................................................................................................................28613.3.6.6 REV Register ...........................................................................................................286

Chapter 14 SPP Interrupt Controller Module for ARM (SPP_INTC_ARM)

14.1 Introduction......................................................................................................................28714.1.1 Overview......................................................................................................................28714.2 INTC Features..................................................................................................................28714.3 INTC External Pins..........................................................................................................28814.4 INTC Bus Aborts .............................................................................................................28814.5 INTC Differences from MAC71xx..................................................................................28814.6 INTC Application Usage .................................................................................................28914.6.1 Enabling the INTC.......................................................................................................29014.7 The Interrupt Controller Module (INTC) ........................................................................29014.7.1 Review of ARM Interrupt Architecture.......................................................................29114.8 Memory Map/Register Definition ...................................................................................29214.8.1 Register Descriptions...................................................................................................29414.8.1.1 IPR[63:0] - Interrupt Pending Register (IPRH, IPRL) ............................................29414.8.1.2 IMR[63:0] - Interrupt Mask Register (IMRH, IMRL) ............................................29614.8.1.3 INTFRC[63:0] - Force Interrupt Register (INTFRCH, INTFRCL) ........................29714.8.1.4 Interrupt Configuration (ICONFIG) Register..........................................................29914.8.1.5 Set Interrupt Mask (SIMR) Register........................................................................30014.8.1.6 Clear Interrupt Mask (CIMR) Register....................................................................30114.8.1.7 Current Level Mask (CLMASK) Register ..............................................................30214.8.1.8 Saved Level Mask (SLMASK) Register .................................................................30314.8.1.9 Interrupt Control Register n (ICRn), n = 0, 1, 2,..., 63 ............................................30414.8.1.10 IRQ Interrupt Acknowledge Register (IRQIACK)..................................................304


xvi Freescale Semiconductor

14.8.1.11 FIQ Interrupt Acknowledge Register (FIQIACK) ..................................................30514.9 Functional Description.....................................................................................................30614.9.1 Interrupt Controller Theory of Operation ....................................................................30614.9.1.1 Interrupt Recognition...............................................................................................30714.9.1.2 Interrupt Prioritization and Level Masking .............................................................30714.9.1.3 Vector Generation during IACK..............................................................................30714.9.1.4 Multiple Controller Requirements...........................................................................30814.9.2 Performance .................................................................................................................30914.10 Initialization/Application Information.............................................................................31014.10.1 Initialization .................................................................................................................31014.10.2 Typical Applications ....................................................................................................31014.10.3 Interrupt Service Routines ...........................................................................................311

Chapter 15 MAC7200 Crossbar Switch (AXBS)

15.1 Introduction......................................................................................................................31315.1.1 Overview......................................................................................................................31415.1.2 Features........................................................................................................................31415.1.3 AXBS Integration ........................................................................................................31415.1.4 Modes of Operation .....................................................................................................31515.2 External Signal Description .............................................................................................31515.3 Memory Map Definition ..................................................................................................31515.4 Register Descriptions .......................................................................................................31615.4.1 Priority Register..........................................................................................................31615.4.2 Control Register...........................................................................................................31715.5 Functional Description.....................................................................................................31915.5.1 Arbitration....................................................................................................................31915.5.1.1 Fixed Priority Operation ..........................................................................................31915.5.1.2 Round-Robin Priority Operation .............................................................................32015.5.2 Priority Assignment .....................................................................................................32015.6 Initialization/Application Information.............................................................................32015.7 AXBS Bus Aborts............................................................................................................32015.7.1 IPI Register Interface ...................................................................................................32015.7.2 Master/Slave Interface .................................................................................................32215.8 AXBS Differences from MAC71xx ................................................................................322

Chapter 16 AHB to IPI Bridge (AIPS)

16.1 Introduction......................................................................................................................32316.1.1 Features........................................................................................................................32316.1.2 General Operation........................................................................................................32416.2 AIPS Protocol ..................................................................................................................325


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16.2.1 8/16/32--bit accesses....................................................................................................32516.3 External Signal Description .............................................................................................32916.4 Memory Map/Register Definition ...................................................................................32916.4.1 Overview......................................................................................................................33016.4.2 Control Registers .........................................................................................................33016.4.3 Register Descriptions...................................................................................................33116.4.3.1 Master Privilege Registers (MPROT) .....................................................................33116.4.3.2 Peripheral Access Control Registers (PACR)..........................................................33216.4.3.3 Off-Platform Peripheral Access Control Registers (OPACRs) ...............................33316.5 Functional Description.....................................................................................................33316.5.1 AIPS Scalability...........................................................................................................33316.5.1.1 Peripheral Presence..................................................................................................33316.5.1.2 Registers ..................................................................................................................33416.5.2 Access Protections .......................................................................................................33416.5.3 Access Support ............................................................................................................33416.5.4 Read Cycles .................................................................................................................33416.5.5 Write Cycles.................................................................................................................33416.5.6 Aborted Cycles ............................................................................................................33416.6 Initialization/Application Information.............................................................................33516.7 AIPS Bus Aborts..............................................................................................................33516.7.1 IPI Register Interface ...................................................................................................33516.7.2 IPI Bridge Interface .....................................................................................................33516.8 AIPS Differences from MAC71xx ..................................................................................336

Chapter 17 External Bus Interface (FlexBus)

17.1 Introduction......................................................................................................................33917.1.1 Block Diagram.............................................................................................................34017.1.2 Features........................................................................................................................34017.1.3 FlexBus Implementation..............................................................................................34117.1.4 FlexBus Memory Map Relocation...............................................................................34117.2 External Signals ...............................................................................................................34117.2.1 Chip-Select (CS[2:0]) ..................................................................................................34217.2.2 Address Bus (ADDR[21:0]) ........................................................................................34217.2.3 Data Bus (DATA[15:0])...............................................................................................34217.2.4 Read/Write (R/W)........................................................................................................34217.2.5 Transfer Burst (TBST).................................................................................................34217.2.6 Byte Write Enable/Byte Select (BWE[1:0]) ...............................................................34217.2.7 Output Enable (OE) .....................................................................................................34217.2.8 Transfer Acknowledge (TA) ........................................................................................34317.3 Chip-Select Operation......................................................................................................34317.3.1 General Chip-Select Operation....................................................................................34317.3.1.1 8-bit and 16-bit Port Sizing......................................................................................343


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17.3.1.2 Global Chip-Select Operation..................................................................................34417.3.2 Chip-Select Registers...................................................................................................34417.3.2.1 Chip-Select Address Registers (CSAR0–CSAR2)..................................................34517.3.2.2 Chip-Select Mask Registers (CSMR0–CSMR2).....................................................34517.3.2.3 Chip-Select Control Registers (CSCR0–CSCR2) ...................................................34717.4 Functional Description.....................................................................................................34917.4.1 Data Transfer Operation ..............................................................................................34917.4.2 Data Byte Alignment and Physical Connections.........................................................34917.4.3 Bus Cycle Execution....................................................................................................35017.4.3.1 Data Transfer Cycle States.......................................................................................35017.5 FlexBus Bus Aborts .........................................................................................................35117.5.1 IPI Register Interface ...................................................................................................35117.5.2 FlexBus Interface.........................................................................................................35217.6 FlexBus Differences from MAC71xx..............................................................................35217.7 FlexBus Application Usage .............................................................................................35317.7.1 Enabling the FlexBus...................................................................................................35317.7.2 Global Chip Select Mode.............................................................................................35317.7.3 FlexBus speed ..............................................................................................................35417.7.4 How to use the external bus in Expanded Secured/Unsecured Mode .........................35417.7.5 How to Use the External Bus in Single Chip Unsecured Mode ..................................35517.7.6 Enabling and Disabling CLKOUT ..............................................................................356

Chapter 18 FLASH (H7Fb) and FLASH Controller (PFLASH)

18.1 Introduction......................................................................................................................35718.2 Flash Features ..................................................................................................................35818.2.1 General Features ..........................................................................................................35818.2.2 Main Array Features ....................................................................................................35818.2.3 Shadow Block Features ...............................................................................................35818.2.4 Flash Modes.................................................................................................................35818.3 Flash Implementation ......................................................................................................35818.3.1 MAC72x1 Flash...........................................................................................................35818.3.2 MAC72x2 Flash...........................................................................................................36018.4 Flash External Pins ..........................................................................................................36118.5 PFLASH Bus Aborts .......................................................................................................36118.5.1 IPI Register Interface ...................................................................................................36118.5.2 Flash Array Interface ...................................................................................................36118.6 PFLASH Differences MAC72x2 from MAC71xx ..........................................................36118.7 PFLASH Application Usage............................................................................................36218.7.1 Flash Terminology .......................................................................................................36218.7.2 Enabling the PFLASH .................................................................................................36318.7.3 Flash Array Memory Map ...........................................................................................36318.7.4 Flash Registers.............................................................................................................363


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18.7.4.1 Flash Block User Registers......................................................................................36318.7.4.1.1 PFCR1 - PFLASH Configuration Register 1 ......................................................36418.7.4.1.2 PFAPR - PFLASH Access Protection Register ...................................................36618.7.4.1.3 PFCR2 - PFLASH Configuration Register 2 ......................................................36718.7.4.1.4 PFSACC - PFLASH Supervisor/user ACCess....................................................36718.7.4.1.5 PFDACC - PFLASH Data/instruction ACCess...................................................36718.7.4.2 Flash MCM Registers ..............................................................................................36818.7.4.2.1 PFWACC - PFLASH Write ACCess ...................................................................36818.7.5 Flash Access Protection ...............................................................................................36818.7.6 Flash Program/Erase Protection and Selection............................................................37218.7.7 Flash Programming Word Size ....................................................................................37418.7.8 Read-while-Write (RWW) ...........................................................................................37418.7.9 Flash Security ..............................................................................................................37418.7.9.1 Securing the device..................................................................................................37418.7.9.2 Unsecuring the device..............................................................................................37518.7.10 Flash Timing ................................................................................................................375

Chapter 19 SRAM and SRAM Controller

19.1 SRAM ..............................................................................................................................37719.1.1 SRAM Features............................................................................................................37719.1.2 SRAM Protocol............................................................................................................37719.1.3 SRAM External Pins....................................................................................................37719.1.4 SRAM Bus Aborts .......................................................................................................37719.1.5 SRAM Differences from MAC71xx............................................................................37719.1.6 SRAM Application Usage ...........................................................................................37819.1.6.1 SRAM Initialization.................................................................................................37819.1.6.2 SRAM Address Mirroring .......................................................................................37819.2 Platform RAM Array Controller (PRAM_CTL) .............................................................37819.2.1 Introduction..................................................................................................................37819.2.2 PRAM_CTL Interface Description..............................................................................38119.2.2.1 Overview..................................................................................................................38119.2.2.2 Detailed Signal Descriptions ...................................................................................38219.2.3 Functional Description.................................................................................................38519.2.3.1 Error Correcting Code (ECC)..................................................................................38519.2.3.1.1 Overview .............................................................................................................38519.2.3.2 Max Address............................................................................................................38719.2.3.3 Read / Write Introduction ........................................................................................38719.2.3.4 Reads........................................................................................................................38819.2.3.4.1 Unaligned Reads..................................................................................................38819.2.3.5 Writes.......................................................................................................................38819.2.3.5.1 32-bit / 64-bit Writes............................................................................................38819.2.3.5.2 Less than 32-bit Writes ........................................................................................39019.2.3.5.3 Unaligned Writes .................................................................................................39119.2.3.6 Late Write Hits.........................................................................................................392


xx Freescale Semiconductor

19.2.3.7 ECC Events on Reads..............................................................................................39419.2.3.7.1 Single Bit Errors ..................................................................................................39419.2.3.7.2 Mulitiple Bit Errors .............................................................................................39419.2.4 Initialization/Application Information.......................................................

mac7200 microcontroller family reference manual · 2018. 12. 17. · mac7200 microcontroller family...

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