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M5271EVB

User’s Manual

M5271EVBUMRev. 1.105/2006

EMC Information on M5271EVB

1. This product as shipped from the factory with associated power supplies and cables, has been tested and meets with requirements of EN5022 and EN 50082-1: 1998 as a CLASS A product.

2. This product is designed and intended for use as a development platform for hardware or software in an educational or professional laboratory.

3. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.

4. Anti-static precautions must be adhered to when using this product.5. Attaching additional cables or wiring to this product or modifying the products operation from the

factory default as shipped may effect its performance and also cause interference with other apparatus in the immediate vicinity. If such interference is detected, suitable mitigating measures should be taken.

WARNINGThis board generates, uses, and can radiate radio frequency energy and, if not installed properly, may cause interference to radio communications. As temporarily permitted by regulation, it has not been tested for compliance with the limits for class a computing devices pursuant to Subpart J of Part 15 of FCC rules, which are designed to provide reasonable protection against such interference. Operation of this product in a residential area is likely to cause interference, in which case the user, at his/her own expense, will be required to correct the interference.

M5271EVB User’s Manual, Rev. 1.1

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Table of Contents

Chapter 1 M5271EVB Introduction

1.1 MCF5271 Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.2 System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.2.1 External Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61.2.2 SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.2.3 ASRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.2.4 Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.2.5 M5271EVB Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.2.6 Reset Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3 Support Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91.3.1 Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91.3.2 Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.3.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.3.4 Exception Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.3.5 TA Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-121.3.6 User’s Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.4 Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131.4.1 UART0, UART1, UART2 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131.4.2 10/100T Ethernet Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131.4.3 BDM/JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-141.4.4 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-151.4.5 QSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.5 Connectors and User Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161.5.1 Daughter Card Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161.5.2 Reset Switch (SW3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-201.5.3 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-201.5.4 Other LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Chapter 2 Initialization and Setup

2.1 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2 Installation and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.1 Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.2.2 Preparing the Board for Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.2.3 Providing Power to the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.2.4 Power Switch (SW1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

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2.2.5 Power Status LEDs and Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.6 Selecting Terminal Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.7 The Terminal Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.8 Connecting the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.9 Using a Personal Computer as a Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3 System Power-up and Initial Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82.4 Using The BDM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Chapter 3 Using the Monitor/Debug Firmware

3.1 What Is dBUG? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.2 Operational Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2.1 System Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.2.2 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.2.1 External RESET Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43.2.2.2 ABORT Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43.2.2.3 Software Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3 Command Line Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43.4 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

ASM Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7BC Block Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8BF Block Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9BM Block Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10BR Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11BS Block Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12DC Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13DI Disassemble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14DL Download Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15DLDBUG Download dBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16DN Download Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17FL Flash Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18GO Execute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19GT Execute To . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20IRD Internal Register Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21IRM Internal Register Modify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22HELP Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23LR Loop Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24LW Loop Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25MD Memory Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26MM Memory Modify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27MMAP Memory Map Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28RD Register Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29RM Register Modify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30RESET Reset the Board and dBUG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

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SD Stack Dump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32SET Set Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33SHOW Show Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34STEP Step Over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35SYMBOL Symbol Name Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36TRACE Trace Into . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37UP Upload Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38VERSION Display dBUG Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39

3.5 TRAP #15 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403.5.1 OUT_CHAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403.5.2 IN_CHAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413.5.3 CHAR_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413.5.4 EXIT_TO_dBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42

Appendix A Configuring dBUG for Network Downloads

A.1 Required Network Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1A.2 Configuring dBUG Network Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2A.3 Troubleshooting Network Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Appendix B Schematics

B.1 MCF5271EVM Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Appendix C M5271EVB BOM

C.1 M5271EVB BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

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List of Figures

Figure 1-1 M5271EVB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Figure 1-2 MCF5271 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Figure 1-3 External Memory Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Figure 1-4 J1- BDM Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Figure 2-1 Minimum System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2Figure 2-2 2.1mm Power Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4Figure 2-3 2-Lever Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4Figure 2-4 Pin Assignment for Female (Terminal) Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6Figure 2-5 Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Figure 3-1 Flow Diagram of dBUG Operational Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

MCF5271EVM Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

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List of Tables

Table 1-1 M5270/71 Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1Table 1-2 The M5271EVB Default Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Table 1-3 D[20:19] External Boot Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Table 1-4 SW4-1 RCON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Table 1-5 SW4-2 JTAG_EN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Table 1-6 SW4-[4:3] Encoded Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9Table 1-7 SW4-5 Chip Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10Table 1-8 SW4-[7:6] Boot Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10Table 1-9 SW4-8 Bus Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10Table 1-10 SW4-[10:9] Address/Chip Select Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10Table 1-11 M5271EVB Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11Table 1-12 J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16Table 1-13 J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17Table 1-14 J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18Table 1-15 J6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19Table 1-16 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20Table 1-17 LED Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Table 2-1 Power LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5Table 2-2 Pin Assignment for Female (Terminal) Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 3-1 dBUG Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Table C-1 M5271EVB BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

List of Tables


x Freescale Semiconductor


Freescale Semiconductor 1-1

Chapter 1 M5271EVB IntroductionThis document details the setup and configuration of the ColdFire M5271EVB evaluation board (hereafter referred to as the EVB). The EVB is intended to provide a mechanism for easy customer evaluation of the MCF5270 and MCF5271 ColdFire microprocessors and to facilitate hardware and software development. The EVB can be used by software and hardware developers to test programs, tools, or circuits without having to develop a complete microprocessor system themselves. All special features of the MCF5270 and MCF5271 are supported.

The heart of the evaluation board is the MCF5271, the MCF5270 has a subset of the MCF5271 specification and can therefore be fully emulated using the MCF5271 device. Table 1-1 details the two devices.

NOTEAll of the devices in the same package are pin compatible.

The EVB provides for low cost software testing with the use of a ROM resident debug monitor, dBUG, programmed into the external Flash device. Operation allows the user to load code in the on-board RAM, execute applications, set breakpoints, and display or modify registers or memory. No additional hardware or software is required for basic operation.

Specifications:• Freescale MCF5271 Microprocessor (100MHz max core frequency)• External Clock source: 25MHz • Operating temperature: 0°C to +70°C• Power requirement: 6 – 14V DC @ 300 ma Typical• Power output: 5V, 3.3V and 1.5V regulated supplies• Board Size: 8.00 x 5.40 inches, 8 layers

Table 1-1. M5270/71 Product Family

Part Number Package FEC CRYPTO

MCF5270AB100 160 QFP Yes No

MCF5270VM100 196 MAPBGA Yes No

MCF5271CAB100 160 QFP Yes Yes

MCF5271CVM100 196 MAPBGA Yes Yes

M5271EVB Introduction


1-2 Freescale Semiconductor

Memory Devices:• 16-Mbyte SDRAM• 2-Mbyte (512K x 16) Page Mode FLASH or 4-Mbyte (512K x 32) Page mode FLASH• 1-Mbyte ASRAM (footprint only)• 64-Kbyte SRAM internal to MCF5271 device

Peripherals:• Ethernet port 10/100Mb/s (Dual-Speed Fast Ethernet Transceiver, with MII)• UART0 (RS-232 serial port for dBUG firmware)• UART1 (auxiliary RS-232 serial port)• UART2 (auxiliary RS-232 serial port)• I2C interface• QSPI interface to ADC• BDM/JTAG interface

User Interface:• Reset logic switch (debounced)• Boot logic selectable (dip switch)• Abort/IRQ7 logic switch (debounced)• PLL Clocking options - Oscillator, Crystal or SMA for external clocking signals• LEDs for power-up indication, general purpose I/O, and timer output signals• Expansion connectors for daughter card

Software:• Resident firmware package that provides a self-contained programming and operating

environment (dBUG)




Figure 1-1. M5271EVB Block Diagram

1.1 MCF5271 MicroprocessorThe microprocessor used on the EVB is the highly integrated Freescale MCF5271 32-bit ColdFire variable-length RISC processor. The MCF5271 implements a ColdFire Version 2 core with a maximum core frequency of 100MHz and external bus speed of 50MHz. Features of the MCF5271 include:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 96 Dhrystone 2.1MIPS @ 100MHz

• 64 Kbytes of internal SRAM• External bus speed of one half the CPU operating frequency (50MHz bus @ 100Mhz core)• 10/100 Mbps bus-mastering Ethernet controller• 8 Kbytes of configurable instruction/data cache• Three universal asynchronous receiver/transmitters (UARTs) with DMA support• Inter-integrated circuit (I2C) bus controller• Queued serial peripheral interface (QSPI) module

ColdFire MCF5271

Per

iphe

ral S

igna

ls

Dat

a [3

1:0]

Add

ress

[23:

0]

Con

trol

Sig

nals

RJ-45Connector

EthernetTransceiver

25-MHzOscillator

26-Pin Debug Header

RS232Transceivers (3)

DB-9Connectors (3)

SDRAM16 MBytes

Flash2–4 MBytes

ASRAM1 MByte

60-Pin Daughter CardExpansion Connectors (4)




• Hardware cryptography accelerator (optional)— Random number generator— DES/3DES/AES block cipher engine— MD5/SHA-1/HMAC accelerator

• Four channel 32-bit direct memory access (DMA) controller• Four channel 32-bit input capture/output compare timers with optional DMA support• Four channel 16-bit periodic interrupt timers (PITs)• Programmable software watchdog timer• Interrupt controller capable of handling up to 126 interrupt sources• Clock module with Phase Locked Loop (PLL)• External bus interface module including a 2-bank synchronous DRAM controller• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode FLASH

memories

The MCF5271 communicates with external devices over a 32-bit wide data bus, D[31:0]. The MCF5271 can address a 32 bit address range. However, only 24 bits are available on the external bus A[23:0]. There are internally generated chip selects to allow the full 32 bit address range to be selected. There are regions that can be decoded to allow supervisor, user, instruction, and data each to have the 32-bit address range.

All the processor's signals are available via daughter card expansion connectors. Refer to the schematic (Appendix B) for their pin assignments.

The MCF5271 processor has the capability to support both BDM and JTAG. These ports are multiplexed and together. In BDM mode it can be used with third party tools to allow the user to download code to the board. In JTAG mode it can be used for boundary scan operations. The board is configured to boot up in the normal/BDM mode of operation. The BDM signals are available at the port labeled BDM.

Figure 1-2 shows the MCF5271 processor block diagram.




Figure 1-2. MCF5271 Block Diagram

64 KbytesSRAM

(8Kx16)x4

EIM

V2 ColdFire CPU

INTC0

Watchdog

PIT0

JTAG

Tap

CACHE(1Kx32)x2

PIT1 PIT2 PIT3

4 CH DMA

UART0

UART1 I2C QSPI

DTIM0

DTIM1

DTIM2

DTIM3

TimerPA

DI –

Pin

Mux

ing

PLLCLKGEN

UART2

8 Kbytes

EdgePort

SDRAMC

Chip

EBI

Selects

(To/From PADI)

(To/From

FEC

TnIN

QSPI

PortsCIM(GPIO)

R/W

TA

TEA

DIV EMAC

DREQ[2:0]

INTC1Arbiter

(To/From SRAM Backdoor)

(To/From Arbiter)

SKHA

RNGA

MDHA

(To/From PADI)

Cryptography

DACK[2:0]

BD

M

(To/From INTC)

MU

X

PADI)

JTAG_EN

FastEthernetController

(FEC)




1.2 System MemoryThe following diagram shows the external memory implementation on the EVB.

Figure 1-3. External Memory Scheme

NOTEThe external bus interface signals to the external ASRAM and FLASH (and USB) are buffered. This is in order not to exceed the maximum output load capacitance of the microprocessor on the EVB.

The signals to the expansion connectors remain unbuffered to provide a “true” interface to the user.

1.2.1 External Flash

The EVB is fitted with a single 512K x 16 page-mode FLASH memory (U10) giving a total memory space of 2Mbytes. Alternatively a footprint is available for the EVB user to upgrade this device to a 512K x 32 page-mode FLASH memory (U11), doubling the memory size to 4Mbytes. Either U10 OR U11 should be fitted on the board - both devices cannot be populated at the same time. Refer to the specific device data sheet and sample software provided for configuring the FLASH memory.

Users should note that the debug monitor firmware is installed on this flash device. Development tools or user application programs may erase or corrupt the debug monitor. If the debug monitor becomes corrupted and it’s operation is desired, the firmware must be reprogrammed into the flash by using a development tool through the BDM port. Users should use caution to avoid this situation. The M5271EVB dBUG debugger/monitor firmware is programmed into the lower sectors of Flash (0xFFE0_0000 to 0xFFE3_FFFF for 2Mbytes of FLASH or 0xFFC0_0000 to 0xFFC3_FFFF for 4 Mbytes of FLASH).

When U11 is fitted on the EVB, jumper 5 (JP5) provides an alternative hardware mechanism for write protection. This feature is not available when U10 is populated.

MPU

Data

Buffers

SDRAM(16 MBytes)

ExpansionConnectors

ASRAM(1 MByte)

Flash(512K x 16)

or(512K x 32)

AddressControl




1.2.2 SDRAM

The EVB is populated with 16 Mbytes of SDRAM. This is done with two devices (Micron MT48LC4M16A2TG) each with a 16 bit data bus. Each device is organized as 1 Meg x 16 x 4 banks with a 16 bit data bus. One device stores the upper 16-bit word and the other the lower 16 bit word of the MCF5271 32 bit data bus.

1.2.3 ASRAM

The EVB has a footprint for two 512K x 16 Asynchronous SRAM devices (Cypress Semiconductor - CY7C1041CV3310ZC). These memory devices (U1 and U2) may be populated by the user for benchmarking purposes.

Also see Section 1.2.5, “M5271EVB Memory Map”.

1.2.4 Internal SRAM

The MCF5271 processor has 64-KBytes of internal SRAM memory which may be used as data or instruction memory. This memory is mapped to 0x2000_0000 and configured as data space but is not used by the dBUG monitor except during system initialization. After system initialization is complete, the internal memory is available to the user. The memory is relocatable to any 32-KByte boundary within the processor’s four gigabyte address space.

1.2.5 M5271EVB Memory Map

Interface signals to support the interface to external memory and peripheral devices are generated by the memory controller. The MCF5271 supports 8 external chip selects, CS[1:0] are used with external memories, and CS[7:2] are easily accessible to users via the daughter card expansion connectors. CS[0] also functions as the global (boot) chip-select for booting out of external flash.

Since the MCF5271 chip selects are fully programmable, the memory banks may be located at any 64-KByte boundary within the processor’s four gigabyte address space.

The default memory map for this board as configured by the Debug Monitor located in the external FLASH bank can be found in Table 1-2. The internal memory space of the MCF5271 is detailed further in the MCF5271 Users Manual. Chip Selects 0 and 1 can be changed by user software to map the external memory in different locations but the chip select configuration such as wait states and transfer acknowledge for each memory type should be maintained.

Chip Select usage:External FLASH Memory CS0External ASRAM Memory CS1




Table 1-2 shows the M5271EVB memory map.

1.2.6 Reset Vector Mapping

Asserting the reset input signal to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.

The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero (0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.

Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault halted state.

The Memory that the MCF5271 accesses at address 0 is determined at reset by sampling D[20:19].

Table 1-2. The M5271EVB Default Memory Map

Address Range Signal and Device

0x0000_0000–0x00FF_FFFF 16 Mbyte SDRAM

0x2000_0000–0x2000_FFFF 64 Kbytes Internal SRAM

0x3000_0000–0x300F_FFFF External ASRAM (not fitted)

0xFFE0_0000–0xFFFF_FFFFor0xFFC0_0000–0xFFFF_FFFF

2 Mbytes External Flash (U10)or4 Mbytes External Flash (U11)

Table 1-3. D[20:19] External Boot Chip Select Configuration

D[20:19] Boot Device/Data Port Size

00 External (32-bit)


10 External (8-bit)





1.3 Support Logic

1.3.1 Reset Logic

Reset occurs during power-on or via assertion of the signal RESET which causes the MCF5271 to reset. RESET is triggered by the reset switch (SW3) which resets the entire processor/system.

The dBUG Firmware configures the MCF5271 microprocessor internal resources during initialization. The contents of the exception table are copied to address 0x0000_0000 in the SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers are placed in a stop condition. A memory map for the entire board can be seen in Table 1-2.

If the external RCON pin is asserted (SW4-1 ON) during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. See tables below on settings for reset configurations.

If the RCON pin is not asserted (SW4-1 OFF) during reset, the chip configuration and the reset configuration pin functions after reset are determined by the RCON register or fixed defaults, regardless of the states of the external data pins.

Table 1-4. SW4-1 RCON

SW4–1 Reset Configuration

OFF RCON not asserted, Default Chip configuration or RCON register settings

ON RCON is asserted, Chip functions, including the reset configuration after reset, are configured according to the levels driven onto the external data pins.

Table 1-5. SW4-2 JTAG_EN

SW4–2 JTAG Enable

OFF JTAG interface enabled

ON BDM interface enabled

Table 1-6. SW4-[4:3] Encoded Clock Mode

SW4–3 SW4–4 Clock Mode

OFF OFF External clock mode (PLL disabled)

OFF ON 1:1 PLL

ON OFF Normal PLL mode with external clock reference

ON ON Normal PLL mode w/crystal oscillator reference




Table 1-7. SW4-5 Chip Configuration Mode

SW4–5 RCON (SW4–1) Mode

OFF ON Reserved

ON ON Master

X OFF Master

Table 1-8. SW4-[7:6] Boot Device

SW4–6 SW4–7 RCON (SW4–1) Boot Device

OFF OFF ON External (32-bit)

OFF ON ON External (8-bit)

ON OFF ON External (16-bit)

ON ON ON External (32-bit)

X X OFF External (32-bit)

Table 1-9. SW4-8 Bus Drive Strength

SW4–8 RCON (SW4–1) Drive Strength

OFF ON Partial Bus Drive

ON ON Full Bus Drive

X OFF Partial Bus Drive

Table 1-10. SW4-[10:9] Address/Chip Select Mode

SW4–9 SW4–10 RCON (SW4–1) Mode

OFF OFF ON PF[7:5] = /CS[6:4]

OFF ON ON PF[7] = /CS6, PF[6:5] = A[22:21]

ON OFF ON PF[7:6] = /CS[6:5], PF[5] = A21

ON ON ON PF[7:5] = A[23:21]

X X OFF PF[7:5] = A[23:21]




1.3.2 Clock CircuitryThe are three options to provide the clock to the CPU. These options can be configured by setting JP[10:12]. See Table 1-11.

The 25MHz oscillator (U15) also feeds the Ethernet chip (U9).

1.3.3 Watchdog TimerThe dBUG Firmware does NOT enable the watchdog timer on the MCF5271.

1.3.4 Exception SourcesThe ColdFire® family of processors can receive seven levels of interrupt priorities. When the processor receives an interrupt which has a higher priority than the current interrupt mask (in the status register), it will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the device should provide the proper vector number to indicate where the service routine for this interrupt level is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as an autovector interrupt which directs the processor to a predefined entry in the exception table (refer to the MCF5271 User's Manual).

The processor goes to an exception routine via the exception table. This table is stored in the Flash EEPROM. The address of the table location is stored in the VBR. The dBUG ROM monitor writes a copy of the exception table into the RAM starting at $00000000. To set an exception vector, the user places the address of the exception handler in the appropriate vector in the vector table located at $00000000 and then points the VBR to $00000000.

The MCF5271 microprocessor has seven external interrupt request lines IRQ[7:1]. The interrupt controller is capable of providing up to 63 interrupt sources. These sources are:

• External interrupt signals IRQ[7:1] (EPORT)• Software watchdog timer module• Timer modules• UART modules 0, 1 and 2• I2C module• DMA module• QSPI module• FEC module• PIT• Security module

Table 1-11. M5271EVB Clock Source Selection

JP10 JP11 JP12 Clock Selection

1–2 1–2 ON 25MHz Oscillator (default setting)

2–3 1–2 ON 25MHz External Clock

X 2–3 OFF 25MHz Crystal (not populated)




All external interrupt inputs are edge sensitive. The active level is programmable. An interrupt request must be held valid until an IACK cycle starts to guarantee correct processing. Each interrupt input can have it’s priority programmed by setting the xIPL[2:0] bits in the Interrupt Control Registers.

No interrupt sources should have the same level and priority as another. Programming two interrupt sources with the same level and priority can result in undefined operation.

The M5271EVB hardware uses IRQ7 to support the ABORT function using the ABORT switch (SW2). This switch is used to force an interrupt (level 7, priority 3) if the user's program execution should be aborted without issuing a RESET (refer to Chapter 2 for more information on ABORT). Since the ABORT switch is not capable of generating a vector in response to a level seven interrupt acknowledge from the processor, the dBUG programs this interrupt request for autovector mode.

Refer to MCF5271 User’s Manual for more information about the interrupt controller.

1.3.5 TA Generation

The processor starts a bus cycle by asserting CSx with the other control signals. The processor then waits for a transfer acknowledgment (TA) either from within (Auto acknowledge - AA mode) or from the externally addressed device before it can complete the bus cycle. -TA is used to indicate the completion of the bus cycle. It also allows devices with different access times to communicate with the processor properly asynchronously. The MCF5271 processor, as part of the chip-select logic, has a built-in mechanism to generate TA for all external devices which do not have the capability to generate this signal. For example the Flash ROM cannot generate a TA signal. The chip-select logic is programmed by the dBUG ROM Monitor to generate TA internally after a pre-programmed number of wait states. In order to support future expansion of the M5271EVB, the TA input of the processor is also connected to the Processor Expansion Bus. This allows any expansion boards to assert this line to provide a TA signal to the processor. On the expansion boards this signal should be generated through an open collector buffer with no pull-up resistor; a pull-up resistor is included on this board. All TA signals from expansion boards should be connected to this line.

1.3.6 User’s Program

JP6 on the 16Mbit FLASH (U10) or JP7 if using 32Mbit FLASH (U11) allows users to test code from boot/POR without having to overwrite the ROM Monitor.

When the jumper is set between pins 1 and 2, the behavior of the system is normal, dBUG boots and then runs from 0xFFE00000 (0xFFC00000). When the jumper is set between pins 2 and 3, the board boots from the top half of the FLASH (0xFFF00000).

Procedure:1. Compile and link as though the code was to be placed at the base of the flash.2. Set up the jumper JP6 (JP7 for U11) for Normal operation, pin1 connected to pin 2. 3. Download to SDRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM via

a wiggler cable, download first, then start ROM Monitor by pointing the program counter (PC) to 0xFFE00400(0xFFC00400) and run.)

4. In the ROM Monitor, execute the 'FL write <dest> <src> <bytes>' command.




5. Move jumper JP6 (JP7 for U11) to pin 2 connected to pin 3 and push the reset button (SW3). User code should now be running from reset/POR.

1.4 Communication PortsThe EVB provides external communication interfaces for three UART serial ports, QSPI, I2C port, 10/100T ethernet port, and BDM/JTAG port.

1.4.1 UART0, UART1, UART2 Ports

The MCF5271 device has three built in UARTs, each with its own software programmable baud rate generator. These UART interfaces are brought out to RS232 transceivers. One channel is the ROM Monitor to Terminal output and the other two are available to the user. The ROM Monitor programs the interrupt level for UART0 to Level 3, priority 2 and autovector mode of operation.

Refer to the MCF5271 User’s Manual for programming the UART’s and their register maps.

1.4.2 10/100T Ethernet Port

The MCF5271 device performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The MCF5271 Ethernet Controller requires an external interface adaptor and transceiver function to complete the interface to the ethernet media. The MCF5271 Ethernet module also features an integrated fast (100baseT) Ethernet media access controller (MAC).

The Fast Ethernet controller (FEC) incorporates the following features:• Support for three different Ethernet physical interfaces:

— 100-Mbps IEEE 802.3 MII— 10-Mbps IEEE 802.3 MII— 10-Mbps 7-wire interface (industry standard)

• IEEE 802.3 full duplex flow control• Programmable max frame length supports IEEE 802.1 VLAN tags and priority• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of

50MHz• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25

MHz• Retransmission from transmit FIFO following a collision (no processor bus utilization)• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address

recognition rejects (no processor bus utilization)• Address recognition

— Frames with broadcast address may be always accepted or always rejected— Exact match for single 48-bit individual (unicast) address— Hash (64-bit hash) check of individual (unicast) addresses— Hash (64-bit hash) check of group (multicast) addresses— Promiscuous mode




For more details see the MCF5271 Users manual. The on board ROM MONITOR is programmed to allow a user to download files from a network to memory in different formats. The current compiler formats supported are S-Record, COFF, ELF or Image.

1.4.3 BDM/JTAG Port

The MCF5271 processor has a Background Debug Mode (BDM) port, which supports Real-Time Trace and Real-Time Debug. The signals which are necessary for debug are available at connector (J1). Figure 1-4 shows the (J1) Connector pin assignment.

Figure 1-4. J1- BDM Connector Pin Assignment

The BDM connector can also be used to interface to JTAG signals. On reset, the JTAG_EN signal selects between multiplexed debug module and JTAG signals. See Table 1-5.

1

3

5

7

9

11

13

15

17

19

21

23

25

2

4

6

8

10

12

14

16

18

20

22

24

26

BKPT

DSCLK

TCLK (only for JTAG)

DSI

DSO

PST3

PST1

DDATA3

DDATA1

GND

Freescale Reserved

PSTCLK

TA

GND

GND

RESET

GND

PST2

PST0

DDATA2

DDATA0

Freescale Reserved

GND

Core Voltage

Developer Reserved

I/O or Pad Voltage




1.4.4 I2C

The MCF5271’s I2C module includes the following features:• Compatibility with the I2C bus standard version 2.1• Multi master operation• Software programmable for one of 50 different clock frequencies• Software selectable acknowledge bit• Interrupt driven byte by byte data transfer• Arbitration-lost interrupt with automatic mode switching from master to slave• Calling address identification interrupt• Start and stop signal generation and detection• Repeated start signal generation• Acknowledge bit generation and detection• Bus busy detection

Please see the MCF5271 User’s Manual for more detail. The I2C signals from the MCF5271 device are brought out to expansion connector (J9).

1.4.5 QSPI

The QSPI (Queued Serial Peripheral Interface) module provides a serial peripheral interface with queued transfer capability. It will support up to 16 stacked transfers at one time, minimizing CPU intervention between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.

Functionality is very similar, but not identical, to the QSPI portion of the QSM (Queued Serial Module) implemented in the MC68332 processor.

• Programmable queue to support up to 16 transfers without user intervention• Supports transfer sizes of 8 to 16 bits in 1-bit increments• Four peripheral chip-select lines for control of up to 15 devices• Baud rates from 147.1-Kbps to 18.75-Mbps at 75MHz.• Programmable delays before and after transfers• Programmable QSPI clock phase and polarity• Supports wrap-around mode for continuous transfers

Please see the MCF5271 User’s Manual for more detail. The QSPI signals from the MCF5271 device are brought out to expansion connector (J8).




1.5 Connectors and User Components

1.5.1 Daughter Card Expansion Connectors

Four, 60-way SMT connectors (J7, J8, J9 and J10) provide access to all MCF5271 signals. These connectors are ideal for interfacing to a custom daughter card or for simple probing of processor signals. Below is a pinout description of these connectors.

Table 1-12. J3

Pin Signal Pin Signal

1 +5V 2 +5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7 GND 8 GND

9 ERXD0 10 NC

11 ETXD1 12 NC

13 ETXD2 14 NC

15 ETXCLK 16 NC

17 ERXER 18 NC

19 ETXEN 20 NC

21 ETXER 22 NC

23 ETXEN 24 GND

25 ETXD0 26 EMDIO

27 U2CTS 28 EMDC

29 I2C_SCL 30 I2C_SDA

31 QSPI_SCK 32 QSPI_DIN

33 BS3 34 QSPI_DOUT

35 BS2 36 QSPI_CS0

37 BS1 38 SD_SCKE

39 BS0 40 NC

41 U2RTS 42 U2RXD

43 QSPI_PCS1 44 U1CTS

45 U1RTS 46 NC

47 U1RXD 48 U2TXD

49 U1TXD 50 CS2

51 CS3 52 CS7

53 CS6 54 CS5

55 CS1 56 CS0

57 CS4 58 A23

59 GND 60 GND




Table 1-13. J4


1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 NC 6 NC

7 NC 8 NC

9 ERXD1 10 NC

11 ERXD3 12 NC

13 ERXD2 14 NC

15 ERXCLK 16 NC

17 ERXDV 18 NC

19 ECOL 20 NC

21 ECRS 22 GND

23 GND 24 U0CTS

25 U0RXD 26 DTOUT0

27 DTIN0 28 U0TXD

29 U0RTS 30 GND

31 CLKMOD0 32 +3.3V

33 CLKMOD1 34 GND

35 GND 36 D28

37 D30 38 D29

39 D31 40 D24

41 D26 42 D25

43 D27 44 D21

45 D23 46 D22

47 EXT_RSTIN 48 D19

49 GND 50 GND

51 D13 52 D20

53 D9 54 D17

55 D12 56 D18

57 D15 58 D16

59 GND 60 GND




Table 1-14. J5


1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 +3.3V 6 +3.3V

7 GND 8 GND

9 A21 10 A22

11 A19 12 A20

13 A17 14 A18

15 A16 16 A14

17 A15 18 A11

19 A13 20 GND

21 GND 22 A10

23 A12 24 A8

25 A9 26 A7

27 A6 28 A4

29 A5 30 GND

31 A2 32 A0

33 A3 34 A1

35 GND 36 GND

37 DTIN3 38 NC

39 DTOUT3 40 NC

41 TIP 42 TEA

43 TS 44 TA

45 NC 46 SD_WE

47 R/W 48 NC

49 SD_CAS 50 SD_CS0

51 CLKOUT 52 SD_RAS

53 SD_CS1 54 DDATA3

55 XTAL 56 EXTAL

57 GND 58 GND

59 GND 60 GND




Table 1-15. J6


1 +5V 2 +1.5V

3 +3.3V 4 +3.3V

5 D14 6 D10

7 D11 8 D6

9 D7 10 D8

11 D5 12 D4

13 GND 14 GND

15 D1 16 D2

17 D3 18 OE

19 D0 20 DTOUT1

21 DTIN1 22 +3.3V

23 +3.3V 24 IRQ6

25 IRQ7 26 TSIZ0

27 TSIZ1 28 IRQ2

29 IRQ3 30 IRQ4

31 IRQ5 32 TCLK/PSTCLK

33 DTOUT2 34 DTIN2

35 IRQ1 36 TDI/DSI

37 TDO/DSO 38 TMS/BKPT

39 TRST/DSCLK 40 GND

41 GND 42 PST3

43 PST1 44 PST2

45 PST0 46 DDATA0

47 DDATA2 48 DDATA1

49 GND 50 GND

51 JTAG_EN 52 RCON

53 GND 54 RSTOUT

55 GND 56 RESET

57 GND 58 GND

59 GND 60 GND




1.5.2 Reset Switch (SW3)

The reset logic provides system initilization. Reset occurs during power-on or via assertion of the signal RESET which causes the MCF5271 to perform a hardare reset. Reset is also triggered by the reset switch (SW3) which resets the entire processor/system.

A hard reset and voltage sense controller (U17) is used to produce an active low power-on RESET signal. The reset switch SW3 is fed into U17 which generates the signal which is fed to the MCF5271 reset, RESET. The RESET signal is an open collector signal and so can be wire OR’ed with other reset signals from additional peripherals. On the EVB, RESET is wire OR’d with the BDM reset signal and there is a reset signal brought out to the expansion connectors for use with user hardware.

dBUG configures the MCF5271 microprocessor internal resources during initialization. The instruction cache is invalidated and disabled. The Vector Base Register, VBR, contains an address which initially points to the Flash memory. The contents of the exception table are written to address $00000000 in the SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers are placed in a stop condition. The interrupt controller registers are initialized with unique interrupt level/priority pairs.

1.5.3 User LEDs

There are eight LEDs available to the user. Each of these LEDs are pulled to +3.3V through a 10 ohm resistor and can be illuminated by driving a logic “0” on the appropriate signal to “sink” the current. Each of these signals can be disconnected from it’s associated LED with a jumper.Table 1-16 details which MCF5271 signal is associated with which LED.

Table 1-16. User LEDs

LED MCF5271 Signal Jumper to Disconnect

D17 DTOUT0 JP13

D18 DTIN0 JP14

D19 DTOUT1 JP15

D20 DTIN1 JP16

D21 DTOUT2 JP17

D22 DTIN2 JP18

D23 DTOUT3 JP19

D24 DTIN3 JP20




1.5.4 Other LEDs

There are several other LED’s on the M5271EVB to signal to the user various board/processor/component state. Below is a list of those LEDs and their functions:

Table 1-17. LED Functions

LED Function

D1–D4 Ethernet Phy functionality

D6 +3.3V Power Good

D9 +5V Power Good

D13 +1.5V Power Good (NOTE:1.5V is not enough to turn this LED on, ignore this LED)

D15 Abort (IRQ7) asserted

D16 Reset (RSTI) asserted

D17–D24 User LEDs (see Table 1-16)



Chapter 2 Initialization and Setup

2.1 System ConfigurationThe M5271EVB board requires the following items for minimum system configuration:

• The M5271EVB board (provided).• Power supply, +6V to 14V DC with minimum of 300 mA.• RS232C compatible terminal or a PC with terminal emulation software.• RS232 Communication cable (provided).

Figure 2-1 displays the minimum system configuration.

Initialization and Setup



Figure 2-1. Minimum System Configuration

dBUG>

RS-232 Terminalor PC

+7 to 14VDCInput Power




2.2 Installation and SetupThe following sections describe all the steps needed to prepare the board for operation. Please read the following sections carefully before using the board. When you are preparing the board for the first time, be sure to check that all jumpers are in the default locations. Default jumper markings are documented on the master jumper table and printed on the underside of the board. After the board is functional in its default mode, the Ethernet interface may be used by following the instructions provided in Appendix A.

2.2.1 Unpacking

Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the following list and verify that all the items are present. You should have received:

• M5271EVB Single Board Computer• M5271EVB User's Manual (this document)• One RS232 communication cable• One BDM (Background Debug Mode) “wiggler” cable• MCF5271UM ColdFire Integrated Microprocessor User Manual • ColdFire® Programmers Reference Manual• A selection of Third Party Developer Tools and Literature

NOTEAvoid touching the MOS devices. Static discharge can and will damage these devices.

Once you have verified that all the items are present, remove the board from its protective jacket and anti-static bag. Check the board for any visible damage. Ensure that there are no broken, damaged, or missing parts. If you have not received all the items listed above or they are damaged, please contact Freescale Semiconductor immediately — for contact details please see the front of this manual.

2.2.2 Preparing the Board for Use

The board, as shipped, is ready to be connected to a terminal and power supply without any need for modification.Figure 2-5 shows the position of the jumpers and connectors.




2.2.3 Providing Power to the Board

The EVB requires an external supply voltage of 6-14V DC, minimum 300 mA. This is regulated on board using three switching voltage regulators to provide the necessary EVB voltages of 5V, 3.3V and 1.5V. There are two different power supply input connectors on the EVB. Connector P1 is a 2.1mm power jack (Figure 2-2), P3 a lever actuated connector (Figure 2-3).

Figure 2-2. 2.1mm Power Connector

Figure 2-3. 2-Lever Power Connector

2.2.4 Power Switch (SW1)

Slide switch SW1 can be used to isolate the power supply input from the EVB voltage regulators if required.

Moving the slide switch to the left (towards connector P2) will turn the EVB ON.

Moving the slide switch to the right (away from connector P2) will turn the EVB OFF.

V+ (7–14V)

GND

GND

V+ (7–14V)




2.2.5 Power Status LEDs and Fuse

When power is applied to the EVB, green power LEDs adjacent to the voltage regulators show the presence of the supply voltage as follows.

If no LEDs are illuminated when the power is applied to the EVB, it is possible that either power switch SW4 is in the “OFF” position or that the fuse F1 has blown. This can occur if power is applied to the EVB in reverse-bias where a protection diode ensures that the fuse blows rather than causing damage to the EVB. Replace F1 with a 20mm 1A fast blow fuse.

2.2.6 Selecting Terminal Baud Rate

The serial channel UART0 of the MCF5271 is used for serial communication and has a built in timer. This timer is used by the dBUG ROM monitor to generate the baud rate used to communicate with a serial terminal. A number of baud rates can be programmed. On power-up or manual RESET, the dBUG ROM monitor firmware configures the channel for 19200 baud. Once the dBUG ROM monitor is running, a SET command may be issued to select any baud rate supported by the ROM monitor.

2.2.7 The Terminal Character Format

The character format of the communication channel is fixed at power-up or RESET. The default character format is 8 bits per character, no parity and one stop bit with no flow control. It is necessary to ensure that the terminal or PC is set to this format.

2.2.8 Connecting the Terminal

The board is now ready to be connected to a PC/terminal. Use the RS-232 serial cable to connect the PC/terminal to the M5271EVB PCB. The cable has a 9-pin female D-sub terminal connector at one end and a 9-pin male D-sub connector at the other end. Connect the 9-pin male connector to connector P3 on the M5271EVB board. Connect the 9-pin female connector to one of the available serial communication channels normally referred to as COM1 (COM2, etc.) on the PC running terminal emulation software. The connector on the PC/terminal may be either male 25-pin or 9-pin. It may be necessary to obtain a 25pin-to-9pin adapter to make this connection. If an adapter is required, refer to Figure 2-4.

Table 2-1. Power LEDs

LED Function

D9 Indicates that the +5V regulator is working correctly

D6 Indicates that the +3.3V regulator is working correctly

D13 Indicates that the +1.5V regulator is working correctly (this LED will not light up with only 1.5V, normal operation is to have this LED off)




2.2.9 Using a Personal Computer as a Terminal

A personal computer may be used as a terminal provided a terminal emulation software package is available. Examples of this software are PROCOMM, KERMIT, QMODEM, Windows 95/98/2000/XP Hyper Terminal or similar packages. The board should then be connected as described in Section 2.2.8, “Connecting the Terminal.”

Once the connection to the PC is made, power may be applied to the PC and the terminal emulation software can be run. In terminal mode, it is necessary to select the baud rate and character format for the channel. Most terminal emulation software packages provide a command known as "Alt-p" (press the p key while pressing the Alt key) to choose the baud rate and character format. The character format should be 8 bits, no parity, one stop bit. (See section 1.9.5 The Terminal Character Format.) The baud rate should be set to 19200. Power can now be applied to the board.

Figure 2-4. Pin Assignment for Female (Terminal) Connector

Pin assignments are as follows:

Figure 2-5 on the next page shows the jumper locations for the board.

Table 2-2. Pin Assignment for Female (Terminal) Connector

DB9 Pin Function

1 Data Carrier Detect, Output (shorted to pins 4 and 6)

2 Receive Data, Output from board (receive refers to terminal side)

3 Transmit Data, Input to board (transmit refers to terminal side)

4 Data Terminal Ready, Input (shorted to pin 1 and 6)

5 Signal Ground

6 Data Set Ready, Output (shorted to pins 1 and 4)

7 Request to Send, Input

8 Clear to send, Output

9 Not connected

1

69

5




Figure 2-5. Jumper Locations




2.3 System Power-up and Initial OperationWhen all of the cables are connected to the board, power may be applied. The dBUG ROM Monitor initializes the board and then displays a power-up message on the terminal, which includes the amount of memory present on the board.

Hard Reset DRAM Size: 16MCopyright 1995-2004 Freescale, Inc. All Rights Reserved. ColdFire MCF5271 EVS Firmware v2e.1a.xx (Build XXX on XXX XX 20XX xx:xx:xx)Enter 'help' for help.

dBUG>

The board is now ready for operation under the control of the debugger as described in Chapter 2. If you do not get the above response, perform the following checks:

1. Make sure that the power supply is properly configured for polarity, voltage level and current capability (~1A) and is connected to the board.

2. Check that the terminal and board are set for the same character format and baud.3. Press the RESET button to insure that the board has been initialized properly.

If you still are not receiving the proper response, your board may have been damaged. Contact Freescale Semiconductor for further instructions, please see the beginning of this manual for contact details.

2.4 Using The BDM PortThe MCF5271 microprocessor has a built in debug module referred to as BDM (background debug module). In order to use BDM, simply connect the 26-pin debug connector on the board, J1, to the P&E BDM wiggler cable provided in the kit. No special setting is needed. Refer to the ColdFire® User's Manual BDM Section for additional instructions.

NOTEBDM functionality and use is supported via third party developer software tools. Details may be found on the CD-ROM included in this kit.



Chapter 3 Using the Monitor/Debug FirmwareThe M5271EVB single board computer has a resident firmware package that provides a self-contained programming and operating environment. The firmware, named dBUG, provides the user with monitor/debug interface, inline assembler and disassembly, program download, register and memory manipulation, and I/O control functions. This chapter is a how-to-use description of the dBUG package, including the user interface and command structure.

3.1 What Is dBUG?dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitive command line interface that can be used to download and execute code. It contains all the primary features needed in a debugger to create a useful debugging environment.

The firmware provides a self-contained programming and operating environment. dBUG interacts with the user through pre-defined commands that are entered via the terminal. These commands are defined in Section 3.4, “Commands”.

The user interface to dBUG is the command line. A number of features have been implemented to achieve an easy and intuitive command line interface.

dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to the debugger. For serial communications, dBUG requires eight data bits, no parity, and one stop bit (8-N-1) with no flow control. The default baud rate is 19200 but can be changed after power-up.

The command line prompt is “dBUG> ”. Any dBUG command may be entered from this prompt. dBUG does not allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80 columns or less. dBUG echoes each character as it is typed, eliminating the need for any “local echo” on the terminal side.

In general, dBUG is not case sensitive. Commands may be entered either in upper or lower case, depending upon the user’s equipment and preference. Only symbol names require that the exact case be used.

Most commands can be recognized by using an abbreviated name. For instance, entering “h” is the same as entering “help”. Thus, it is not necessary to type the entire command name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes this and allows for repeated execution of these commands with minimal typing. After a command is entered, simply press <RETURN> or <ENTER> to invoke the command again. The command is executed as if no command line parameters were provided.

An additional function called the "System Call" allows the user program to utilize various routines within dBUG. The System Call is discussed at the end of this chapter.

Using the Monitor/Debug Firmware



The operational mode of dBUG is demonstrated in Figure 3-1. After the system initialization, the board waits for a command-line input from the user terminal. When a proper command is entered, the operation continues in one of the two basic modes. If the command causes execution of the user program, the dBUG firmware may or may not be re-entered, at the discretion of the user’s program. For the alternate case, the command will be executed under control of the dBUG firmware, and after command completion, the system returns to command entry mode.

During command execution, additional user input may be required depending on the command function.

For commands that accept an optional <width> to modify the memory access size, the valid values are:• B 8-bit (byte) access• W 16-bit (word) access• L 32-bit (long) access

When no <width> option is provided, the default width is.W, 16-bit.

The core ColdFire® register set is maintained by dBUG. These are listed below:• A0-A7• D0-D7• PC• SR

All control registers on ColdFire® are not readable by the supervisor-programming model, and thus not accessible via dBUG. User code may change these registers, but caution must be exercised as changes may render dBUG inoperable.

A reference to “SP” (stack pointer) actually refers to general purpose address register seven, “A7.”

3.2 Operational ProcedureSystem power-up and initial operation are described in detail in Chapter 2, “Initialization and Setup”. This information is repeated here for convenience and to prevent possible damage.

3.2.1 System Power-up• Be sure the power supply is connected properly prior to power-up.• Make sure the terminal is connected to TERMINAL (P3) connector.• Turn power on to the board.

Figure 3-1 shows the dBUG operational mode.




Figure 3-1. Flow Diagram of dBUG Operational Mode

COMMAND LINEINPUT FROM TERMINAL

DOES COMMAND LINECAUSE USER PROGRAM

EXECUTION

NO

YES

YES

EXECUTE COMMANDFUNCTION

INITIALIZE

NO

JUMP TO USERPROGRAM AND

BEGIN EXECUTION




3.2.2 System Initialization

After the EVB is powered-up and initialized, the terminal will display:Hard ResetDRAM Size: 16M

ColdFire MCF5271 on the M5271EVBFirmware vXX.XX.XX (Build X on XXXX)Copyright 1995-2004 Freescale, Inc. All Rights Reserved.

Enter 'help' for help.

dBUG>

Other means can be used to re-initialize the M5271EVB firmware. These means are discussed in the following paragraphs.

3.2.2.1 External RESET Button

External RESET (SW3) is the red button. Depressing this button causes all processes to terminate, resets the MCF5271 processor and board logic and restarts the dBUG firmware. Pressing the RESET button would be the appropriate action if all else fails.

3.2.2.2 ABORT Button

ABORT (SW2) is the button located next to the RESET button. The abort function causes an interrupt of the present processing (a level 7 interrupt on MCF5271) and gives control to the dBUG firmware. This action differs from RESET in that no processor register or memory contents are changed, the processor and peripherals are not reset, and dBUG is not restarted. Also, in response to depressing the ABORT button, the contents of the MCF5271 core internal registers are displayed.

The abort function is most appropriate when software is being debugged. The user can interrupt the processor without destroying the present state of the system. This is accomplished by forcing a non-maskable interrupt that will call a dBUG routine that will save the current state of the registers to shadow registers in the monitor for display to the user. The user will be returned to the ROM monitor prompt after exception handling.

3.2.2.3 Software Reset Command

dBUG does have a command that causes the dBUG to restart as if a hardware reset was invoked. The command is “RESET”.

3.3 Command Line UsageThe user interface to dBUG is the command line. A number of features have been implemented to achieve an easy and intuitive command line interface.

dBUG assumes that an 80x24 ASCII character dumb terminal is used to connect to the debugger. For serial communications, dBUG requires eight data bits, no parity, and one stop bit (8-N-1). The baud rate default




is 19200 bps — a speed commonly available from workstations, personal computers and dedicated terminals.

The command line prompt is: dBUG>

Any dBUG command may be entered from this prompt. dBUG does not allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80 columns or less. dBUG echoes each character as it is typed, eliminating the need for any local echo on the terminal side.

The <Backspace> and <Delete> keys are recognized as rub-out keys for correcting typographical mistakes.

Command lines may be recalled using the <Control> U, <Control> D and <Control> R key sequences. <Control> U and <Control> D cycle up and down through previous command lines. <Control> R recalls and executes the last command line.

In general, dBUG is not case-sensitive. Commands may be entered either in uppercase or lowercase, depending upon the user’s equipment and preference. Only symbol names require that the exact case be used.

Most commands can be recognized by using an abbreviated name. For instance, entering h is the same as entering help. Thus it is not necessary to type the entire command name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. dBUG recognizes this and allows for repeated execution of these commands with minimal typing. After a command is entered, press the <Return> or <Enter> key to invoke the command again. The command is executed as if no command line parameters were provided.

3.4 CommandsThis section lists the commands that are available with all versions of dBUG. Some board or CPU combinations may use additional commands not listed below.

Table 3-1. dBUG Command Summary

Mnemonic Syntax Description

ASM asm <<addr> stmt> Assemble

BC bc addr1 addr2 length Block Compare

BF bf <width> begin end data <inc> Block Fill

BM bm begin end dest Block Move

BR br addr <-r> <-c count> <-t trigger> Breakpoint

BS bs <width> begin end data Block Search

DC dc value Data Convert

DI di<addr> Disassemble

DL dl <offset> Download Serial

DLDBUG dldbug Download dBUG




DN dn <-c> <-e> <-i> <-s <-o offset>> <filename> Download Network

FL fl erase addr bytesfl write dest src bytes

Flash Utilities

GO go <addr> Execute

GT gt addr Execute To

HELP help <command> Help

IRD ird <module.register> Internal Register Display

IRM irm module.register data Internal Register Modify

LR lr<width> addr Loop Read

LW lw<width> addr data Loop Write

MD md<width> <begin> <end> Memory Display

MM mm<width> addr <data> Memory Modify

MMAP mmap Memory Map Display

RD rd <reg> Register Display

RM rm reg data Register Modify

RESET reset Reset

SD sd Stack Dump

SET set <option value> Set Configurations

SHOW show <option> Show Configurations

STEP step Step (Over)

SYMBOL symbol <symb> <-a symb value> <-r symb> -C|l|s> Symbol Management

TRACE trace <num> Trace (Into)

UP up begin end filename Upload Memory to File

VERSION version Show Version

Table 3-1. dBUG Command Summary (continued)

Mnemonic Syntax Description

ASM asm <<addr> stmt> Assemble

BC bc addr1 addr2 length Block Compare

BF bf <width> begin end data <inc> Block Fill




ASM Assembler ASM

Usage: ASM <<addr> stmt>

The ASM command is a primitive assembler. The <stmt> is assembled and the resulting code placed at <addr>. This command has an interactive and non-interactive mode of operation.

The value for address <addr> may be an absolute address specified as a hexadecimal value, or a symbol name. The value for stmt must be valid assembler mnemonics for the CPU.

For the interactive mode, the user enters the command and the optional <addr>. If the address is not specified, then the last address is used. The memory contents at the address are disassembled, and the user prompted for the new assembly. If valid, the new assembly is placed into memory, and the address incremented accordingly. If the assembly is not valid, then memory is not modified, and an error message produced. In either case, memory is disassembled and the process repeats.

The user may press the <Enter> or <Return> key to accept the current memory contents and skip to the next instruction, or a enter period to quit the interactive mode.

In the non-interactive mode, the user specifies the address and the assembly statement on the command line. The statement is then assembled, and if valid, placed into memory, otherwise an error message is produced.

Examples:To place a NOP instruction at address 0x00010000, the command is:

asm 10000 nop

To interactively assemble memory at address 0x00400000, the command is:asm 400000




BC Block Compare BC

Usage: BC addr1 addr2 length

The BC command compares two contiguous blocks of memory on a byte by byte basis. The first block starts at address addr1 and the second starts at address addr2, both of length bytes.

If the blocks are not identical, the address of the first mismatch is displayed. The value for addresses addr1 and addr2 may be an absolute address specified as a hexadecimal value or a symbol name. The value for length may be a symbol name or a number converted according to the user defined radix (hexadecimal by default).

Example:To verify that the data starting at 0x20000 and ending at 0x30000 is identical to the data starting at 0x80000, the command is:

bc 20000 80000 10000




BF Block Fill BF

Usage: BF<width> begin end data <inc>

The BF command fills a contiguous block of memory starting at address begin, stopping at address end, with the value data. <Width> modifies the size of the data that is written. If no <width> is specified, the default of word sized data is used.

The value for addresses begin and end may be an absolute address specified as a hexadecimal value, or a symbol name. The value for data may be a symbol name, or a number converted according to the user-defined radix, normally hexadecimal.

The optional value <inc> can be used to increment (or decrement) the data value during the fill.

This command first aligns the starting address for the data access size, and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly-aligned memory accesses.

Examples:To fill a memory block starting at 0x00020000 and ending at 0x00040000 with the value 0x1234, the command is:

bf 20000 40000 1234

To fill a block of memory starting at 0x00020000 and ending at 0x0004000 with a byte value of 0xAB, the command is:

bf.b 20000 40000 AB

To zero out the BSS section of the target code (defined by the symbols bss_start and bss_end), the command is:

bf bss_start bss_end 0

To fill a block of memory starting at 0x00020000 and ending at 0x00040000 with data that increments by 2 for each <width>, the command is:

bf 20000 40000 0 2




BM Block Move BM

Usage: BM begin end dest

The BM command moves a contiguous block of memory starting at address begin and stopping at address end to the new address dest. The BM command copies memory as a series of bytes, and does not alter the original block.

The values for addresses begin, end, and dest may be absolute addresses specified as hexadecimal values, or symbol names. If the destination address overlaps the block defined by begin and end, an error message is produced and the command exits.

Examples:To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to the location 0x00200000, the command is:

bm 40000 80000 200000

To copy the target code’s data section (defined by the symbols data_start and data_end) to 0x00200000, the command is:

bm data_start data_end 200000

NOTERefer to “upuser” command for copying code/data into Flash memory.




BR Breakpoints BR

Usage: BR addr <-r> <-c count> <-t trigger>

The BR command inserts or removes breakpoints at address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name. Count and trigger are numbers converted according to the user-defined radix, normally hexadecimal.

If no argument is provided to the BR command, a listing of all defined breakpoints is displayed.

The -r option to the BR command removes a breakpoint defined at address addr. If no address is specified in conjunction with the -r option, then all breakpoints are removed.

Each time a breakpoint is encountered during the execution of target code, its count value is incremented by one. By default, the initial count value for a breakpoint is zero, but the -c option allows setting the initial count for the breakpoint.

Each time a breakpoint is encountered during the execution of target code, the count value is compared against the trigger value. If the count value is equal to or greater than the trigger value, a breakpoint is encountered and control returned to dBUG. By default, the initial trigger value for a breakpoint is one, but the -t option allows setting the initial trigger for the breakpoint.

If no address is specified in conjunction with the -c or -t options, then all breakpoints are initialized to the values specified by the -c or -t option.

Examples:To set a breakpoint at the C function main() (symbol _main; see “symbol” command), the command is:

br _main

When the target code is executed and the processor reaches main(), control will be returned to dBUG.To set a breakpoint at the C function bench() and set its trigger value to 3, the command is:

br _bench -t 3

When the target code is executed, the processor must attempt to execute the function bench() a third time before returning control back to dBUG.To remove all breakpoints, the command is:

br -r




BS Block Search BS

Usage: BS<width> begin end data

The BS command searches a contiguous block of memory starting at address begin, stopping at address end, for the value data. <Width> modifies the size of the data that is compared during the search. If no <width> is specified, the default of word sized data is used.

The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or symbol names. The value for data may be a symbol name or a number converted according to the user-defined radix, normally hexadecimal.


Examples:To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 and ending at 0x00080000:

bs 40000 80000 1234

This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value 0x1234. If no match is found, then the address is incremented to 0x00040002 and the next 16-bit value is read and compared.To search for the 32-bit value 0xABCD in the memory block starting at 0x00040000 and ending at 0x00080000:

bs.l 40000 80000 ABCD

This reads the 32-bit word located at 0x00040000 and compares it against the 32-bit value 0x0000ABCD. If no match is found, then the address is incremented to 0x00040004 and the next 32-bit value is read and compared.




DC Data Conversion DC

Usage: DC data

The DC command displays the hexadecimal or decimal value data in hexadecimal, binary, and decimal notation.

The value for data may be a symbol name or an absolute value. If an absolute value passed into the DC command is prefixed by ‘0x’, then data is interpreted as a hexadecimal value. Otherwise data is interpreted as a decimal value.

All values are treated as 32-bit quantities.

Examples:To display the decimal and binary equivalent of 0x1234, the command is:

dc 0x1234

To display the hexadecimal and binary equivalent of 1234, the command is:dc 1234




DI Disassemble DI

Usage: DI <addr>

The DI command disassembles target code pointed to by addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name.

Wherever possible, the disassembler will use information from the symbol table to produce a more meaningful disassembly. This is especially useful for branch target addresses and subroutine calls.

The DI command attempts to track the address of the last disassembled opcode. If no address is provided to the DI command, then the DI command uses the address of the last opcode that was disassembled.

The DI command is repeatable.

Examples:To disassemble code that starts at 0x00040000, the command is:

di 40000

To disassemble code of the C function main(), the command is:di _main




DL Download Console DL

Usage: DL <offset>

The DL command performs an S-record download of data obtained from the console, typically a serial port. The value for offset is converted according to the user-defined radix, normally hexadecimal. Please reference the ColdFire Microprocessor Family Programmer’s Reference Manual for details on the S-Record format.

If offset is provided, then the destination address of each S-record is adjusted by offset.

The DL command checks the destination download address for validity. If the destination is an address outside the defined user space, then an error message is displayed and downloading aborted.

If the S-record file contains the entry point address, then the program counter is set to reflect this address.

Examples:To download an S-record file through the serial port, the command is:

dl

To download an S-record file through the serial port, and add an offset to the destination address of 0x40, the command is:

dl 0x40




DLDBUG Download dBUG DLDBUG

Usage: DL <offset>

The DLDBUG command is used to update the dBUG image in Flash. It erases the Flash sectors containing the dBUG image, downloads a new dBUG image in S-record format obtained from the console, and programs the new dBUG image into Flash.

When the DLDBUG command is issued, dBUG will prompt the user for verification before any actions are taken. If the the command is affirmed, the Flash is erased and the user is prompted to begin sending the new dBUG S-record file. The file should be sent as a text file with no special transfer protocol.

Use this command with extreme caution, as any error can render dBUG useless!




DN Download Network DN

Usage: DN <-c> <-e> <-i> <-s> <-o offset> <filename>

The DN command downloads code from the network. The DN command handle files which are either S-record, COFF, ELF or Image formats. The DN command uses Trivial File Transfer Protocol (TFTP) to transfer files from a network host.

In general, the type of file to be downloaded and the name of the file must be specified to the DN command. The -c option indicates a COFF download, the -e option indicates an ELF download, the -i option indicates an Image download, and the -s indicates an S-record download. The -o option works only in conjunction with the -s option to indicate an optional offset for S-record download. The filename is passed directly to the TFTP server and therefore must be a valid filename on the server.

If neither of the -c, -e, -i, -s or filename options are specified, then a default filename and filetype will be used. Default filename and filetype parameters are manipulated using the SET and SHOW commands.

The DN command checks the destination download address for validity. If the destination is an address outside the defined user space, then an error message is displayed and downloading aborted.

For ELF and COFF files which contain symbolic debug information, the symbol tables are extracted from the file during download and used by dBUG. Only global symbols are kept in dBUG. The dBUG symbol table is not cleared prior to downloading, so it is the user’s responsibility to clear the symbol table as necessary prior to downloading.

If an entry point address is specified in the S-record, COFF or ELF file, the program counter is set accordingly.

Examples:To download an S-record file with the name “srec.out”, the command is:

dn -s srec.out

To download a COFF file with the name “coff.out”, the command is:dn -c coff.out

To download a file using the default filetype with the name “bench.out”, the command is:dn bench.out

To download a file using the default filename and filetype, the command is:dn




FL Flash Utilities FL

Info Usage: FL

Erase Usage: FL erase addr bytes

Write Usage: FL write dest src bytes

The FL command provides a set of flash utilities that will display information about the Flash devices on the EVB, erase a specified range of Flash, or erase and program a specified range of Flash.

When issued with no parameters, the FL command will display usage information as well as device specific information for the Flash devices available. This information includes size, address range, protected range, access size, and sector boundaries.

When the erase command is given, the FL command will attempt to erase the number of bytes specified on the command line beginning at addr. If this range doesn’t start and end on Flash sector boundaries, the range will be adjusted automatically and the user will be prompted for verification before proceeding.

When the write command is given, the FL command will program the number of bytes specified from src to dest. An erase of this region will first be attempted. As with the erase command, if the Flash range to be programmed doesn’t start and end on Flash sector boundaries, the range will be adjusted and the user will be prompted for verification before the erase is performed. The specified range is also checked to insure that the entire destination range is valid within the same Flash device and that the src and dest are not within the same device.




GO Execute GO

Usage: GO <addr>

The GO command executes target code starting at address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name.

If no argument is provided, the GO command begins executing instructions at the current program counter.

When the GO command is executed, all user-defined breakpoints are inserted into the target code, and the context is switched to the target program. Control is only regained when the target code encounters a breakpoint, illegal instruction, trap #15 exception, or other exception which causes control to be handed back to dBUG.

The GO command is repeatable.

Examples:To execute code at the current program counter, the command is:

go

To execute code at the C function main(), the command is:go _main

To execute code at the address 0x00040000, the command is:go 40000




GT Execute To GT

Usage: GT addr

The GT command inserts a temporary breakpoint at addr and then executes target code starting at the current program counter. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name.

When the GT command is executed, all breakpoints are inserted into the target code, and the context is switched to the target program. Control is only regained when the target code encounters a breakpoint, illegal instruction, or other exception which causes control to be handed back to dBUG.

Examples:To execute code up to the C function bench(), the command is:

gt _bench




IRD Internal Register Display IRD

Usage: IRD <module.register>

This command displays the internal registers of different modules inside the MCF5271. In the command line, module refers to the module name where the register is located and register refers to the specific register to display.

The registers are organized according to the module to which they belong. Use the IRD command without any parameters to get a list of all the valid modules. Refer to the MCF5271 user’s manual for more information on these modules and the registers they contain.

Example:ird sim.rsr




IRM Internal Register Modify IRM

Usage: IRM module.register data

This command modifies the contents of the internal registers of different modules inside the MCF5271. In the command line, module refers to the module name where the register is located and register refers to the specific register to modify. The data parameter specifies the new value to be written into the register.

Example:To modify the TMR register of the first Timer module to the value 0x0021, the command is:

irm timer1.tmr 0021




HELP Help HELP

Usage: HELP <command>

The HELP command displays a brief syntax of the commands available within dBUG. In addition, the address of where user code may start is given. If command is provided, then a brief listing of the syntax of the specified command is displayed.

Examples:To obtain a listing of all the commands available within dBUG, the command is:

help

To obtain help on the breakpoint command, the command is:help br




LR Loop Read LR

Usage: LR<width> addr

The LR command continually reads the data at addr until a key is pressed. The optional <width> specifies the size of the data to be read. If no <width> is specified, the command defaults to reading word sized data.

Example:To continually read the longword data from address 0x20000, the command is:

lr.l 20000




LW Loop Write LW

Usage: LW<width> addr data

The LW command continually writes data to addr. The optional width specifies the size of the access to memory. The default access size is a word.

Examples:To continually write the longword data 0x12345678 to address 0x20000, the command is:

lw.l 20000 12345678

Note that the following command writes 0x78 into memory:lw.b 20000 12345678




MD Memory Display MD

Usage: MD<width> <begin> <end>

The MD command displays a contiguous block of memory starting at address begin and stopping at address end. The values for addresses begin and end may be absolute addresses specified as hexadecimal values, or symbol names. Width modifies the size of the data that is displayed. If no <width> is specified, the default of word sized data is used.

Memory display starts at the address begin. If no beginning address is provided, the MD command uses the last address that was displayed. If no ending address is provided, then MD will display memory up to an address that is 128 beyond the starting address.


Examples:To display memory at address 0x00400000, the command is:

md 400000

To display memory in the data section (defined by the symbols data_start and data_end), the command is:

md data_start

To display a range of bytes from 0x00040000 to 0x00050000, the command is:md.b 40000 50000

To display a range of 32-bit values starting at 0x00040000 and ending at 0x00050000:md.l 40000 50000




MM Memory Modify MM

Usage: MM<width> addr <data>

The MM command modifies memory at the address addr. The value for addr may be an absolute address specified as a hexadecimal value, or a symbol name. Width specifies the size of the data that is modified. If no <width> is specified, the default of word sized data is used. The value for data may be a symbol name, or a number converted according to the user-defined radix, normally hexadecimal.

If a value for data is provided, then the MM command immediately sets the contents of addr to data. If no value for data is provided, then the MM command enters into a loop. The loop obtains a value for data, sets the contents of the current address to data, increments the address according to the data size, and repeats. The loop terminates when an invalid entry for the data value is entered, i.e., a period.


Examples:To set the byte at location 0x00010000 to be 0xFF, the command is:

mm.b 10000 FF

To interactively modify memory beginning at 0x00010000, the command is:mm 10000




MMAP Memory Map Display MMAP

Usage: mmap

This command displays the memory map information for the M5271EVB evaluation board. The information displayed includes the type of memory, the start and end address of the memory, and the port size of the memory. The display also includes information on how the Chip-selects are used on the board and which regions of memory are reserved for dBUG use (protected).

Here is an example of the output from this command: Type Start End Port Size --------------------------------------------------- SDRAM 0x00000000 0x00FFFFFF 32-bit SRAM (Int) 0x20000000 0x2000FFFF 32-bit ASRAM (Ext) 0x30000000 0x3007FFFF 32-bit IPSBAR 0x40000000 0x7FFFFFFF 32-bit Flash (Ext) 0xFFE00000 0xFFFFFFFF 16-bit

Protected Start End ---------------------------------------- dBUG Code 0xFFE00000 0xFFE3FFFF dBUG Data 0x00000000 0x0000FFFF

Chip Selects ---------------- CS0 Ext Flash CS1 Ext ASRAM




RD Register Display RD

Usage: RD <reg>

The RD command displays the register set of the target. If no argument for reg is provided, then all registers are displayed. Otherwise, the value for reg is displayed.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RD command displays register values from the register buffer.

Examples:To display all the registers and their values, the command is:

rd

To display only the program counter:rd pc

Here is an example of the output from this command:PC: 00000000 SR: 2000 [t.Sm.000...xnzvc]

An: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000

Dn: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000




RM Register Modify RM

Usage: RM reg data

The RM command modifies the contents of the register reg to data. The value for reg is the name of the register, and the value for data may be a symbol name, or it is converted according to the user-defined radix, normally hexadecimal.

dBUG preserves the registers by storing a copy of the register set in a buffer. The RM command updates the copy of the register in the buffer. The actual value will not be written to the register until target code is executed.

Examples:To change register D0 on MC68000 and ColdFire to contain the value 0x1234, the command is:

rm D0 1234




RESET Reset the Board and dBUG RESET

Usage: RESET

The RESET command resets the board and dBUG to their initial power-on states.

The RESET command executes the same sequence of code that occurs at power-on. If the RESET command fails to reset the board adequately, cycle the power or press the reset button.

Examples:To reset the board and clear the dBUG data structures, the command is:

reset




SD Stack Dump SD

Usage: SD

The SD command displays a back trace of stack frames. This command is useful after some user code has executed that creates stack frames (i.e. nested function calls). After control is returned to dBUG, the SD command will decode the stack frames and display a trace of the function calls.




SET Set Configurations SET

Usage: SET <option value>

The SET command allows the setting of user-configurable options within dBUG. With no arguments, SET displays the options and values available. The SHOW command displays the settings in the appropriate format. The standard set of options is listed below.

baud — This is the baud rate for the first serial port on the board. All communications between dBUG and the user occur using either 9600 or 19200 bps, eight data bits, no parity, and one stop bit, 8-N-1, with no flow control.

base — This is the default radix for use in converting a number from its ASCII text representation to the internal quantity used by dBUG. The default is hexadecimal (base 16), and other choices are binary (base 2), octal (base 8), and decimal (base 10).

client — This is the network Internet Protocol (IP) address of the board. For network communications, the client IP is required to be set to a unique value, usually assigned by your local network administrator.

server — This is the network IP address of the machine which contains files accessible via TFTP. Your local network administrator will have this information and can assist in properly configuring a TFTP server if one does not exist.

gateway — This is the network IP address of the gateway for your local subnetwork. If the client IP address and server IP address are not on the same subnetwork, then this option must be properly set. Your local network administrator will have this information.

netmask — This is the network address mask to determine if use of a gateway is required. This field must be properly set. Your local network administrator will have this information.

filename — This is the default filename to be used for network download if no name is provided to the DN command.

filetype — This is the default file type to be used for network download if no type is provided to the DN command. Valid values are: “srecord”, “coff”, and “elf”.

mac — This is the ethernet Media Access Control (MAC) address (a.k.a hardware address) for the evaluation board. This should be set to a unique value, and the most significant nibble should always be even.

Examples:To set the baud rate of the board to be 19200, the command is:

set baud 19200

NOTESee the SHOW command for a display containing the correct formatting of these options.




SHOW Show Configurations SHOW

Usage: SHOW <option>

The SHOW command displays the settings of the user-configurable options within dBUG. When no option is provided, SHOW displays all options and values.

Examples:To display all options and settings, the command is:

show

To display the current baud rate of the board, the command is:show baud

Here is an example of the output from a show command:dBUG> show

base: 16

baud: 19200

server: 0.0.0.0

client: 0.0.0.0

gateway: 0.0.0.0

netmask: 255.255.255.0

filename: test.s19

filetype: S-Record

ethaddr: 00:CF:52:82:CF:01




STEP Step Over STEP

Usage: STEP

The STEP command can be used to “step over” a subroutine call, rather than tracing every instruction in the subroutine. The ST command sets a temporary breakpoint one instruction beyond the current program counter and then executes the target code.

The STEP command can be used to “step over” BSR and JSR instructions.

The STEP command will work for other instructions as well, but note that if the STEP command is used with an instruction that will not return, i.e. BRA, then the temporary breakpoint may never be encountered and dBUG may never regain control.

Examples:To pass over a subroutine call, the command is:

step




SYMBOL Symbol Name Management SYMBOL

Usage: SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s>

The SYMBOL command adds or removes symbol names from the symbol table. If only a symbol name is provided to the SYMBOL command, then the symbol table is searched for a match on the symbol name and its information displayed.

The -a option adds a symbol name and its value into the symbol table. The -r option removes a symbol name from the table.

The -c option clears the entire symbol table, the -l option lists the contents of the symbol table, and the -s option displays usage information for the symbol table.

Symbol names contained in the symbol table are truncated to 31 characters. Any symbol table lookups, either by the SYMBOL command or by the disassembler, will only use the first 31 characters. Symbol names are case-sensitive.

Symbols can also be added to the symbol table via in-line assembly labels and ethernet downloads of ELF formatted files.

Examples:To define the symbol “main” to have the value 0x00040000, the command is:

symbol -a main 40000

To remove the symbol “junk” from the table, the command is:symbol -r junk

To see how full the symbol table is, the command is:symbol -s

To display the symbol table, the command is:symbol -l




TRACE Trace Into TRACE

Usage: TRACE <num>

The TRACE command allows single-instruction execution. If num is provided, then num instructions are executed before control is handed back to dBUG. The value for num is a decimal number.

The TRACE command sets bits in the processors’ supervisor registers to achieve single-instruction execution, and the target code executed. Control returns to dBUG after a single-instruction execution of the target code.

This command is repeatable.

Examples:To trace one instruction at the program counter, the command is:

tr

To trace 20 instructions from the program counter, the command is:tr 20




UP Upload Data UP

Usage: UP begin end filename

The UP command uploads the data from a memory region (specified by begin and end) to a file (specified by filename) over the network. The file created contains the raw binary data from the specified memory region. The UP command uses the Trivial File Transfer Protocol (TFTP) to transfer files to a network host.




VERSION Display dBUG Version VERSION

Usage: VERSION

The VERSION command displays the version information for dBUG. The dBUG version, build number and build date are all given.

The version number is separated by a decimal, for example, “v 2b.1c.1a”.

The version date is the day and time at which the entire dBUG monitor was compiled and built.

Examples:To display the version of the dBUG monitor, the command is:

version

In this example, v 2b . 1c . 1a{ { {

dBUG commonmajor and minor revision

CPU major and minor revision

board majorand minor revision




3.5 TRAP #15 FunctionsAn additional utility within the dBUG firmware is a function called the TRAP 15 handler. This function can be called by the user program to utilize various routines within the dBUG, to perform a special task, and to return control to the dBUG. This section describes the TRAP 15 handler and how it is used.

There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR, CHAR_PRESENT, and EXIT_TO_dBUG.

3.5.1 OUT_CHAR

This function ( function code 0x0013) sends a character, which is in the lower 8 bits of D1, to the terminal.

Assembly example:/* assume d1 contains the character */

move.l #$0013,d0 Selects the function

TRAP #15 The character in d1 is sent to terminal

C example:void board_out_char (int ch)

{

/* If your C compiler produces a LINK/UNLK pair for this routine,

* then use the following code which takes this into account

*/

#if l

/* LINK a6,#0 -- produced by C compiler */

asm (“ move.l 8(a6),d1”); /* put ‘ch’into d1 */

asm (“ move.l #0x0013,d0”); /* select the function */

asm (“ trap #15”); /* make the call */

/* UNLK a6 -- produced by C compiler */

#else

/* If C compiler does not produce a LINK/UNLK pair, the use

* the following code.

*/

asm (“ move.l 4(sp),d1”); /* put ‘ch’into d1 */



#endif

}




3.5.2 IN_CHAR

This function (function code 0x0010) returns an input character (from terminal) to the caller. The returned character is in D1.

Assembly example:move.l #$0010,d0 Select the function

trap #15 Make the call, the input character is in d1.

C example:int board_in_char (void)

{



asm (“ move.l d1,d0”); /* put the character in d0 */

}

3.5.3 CHAR_PRESENT

This function (function code 0x0014) checks if an input character is present to receive. A value of zero is returned in D0 when no character is present. A non-zero value in D0 means a character is present.


trap #15 Make the call, d0 contains the response (yes/no).

C example:int board_char_present (void)

{



}




3.5.4 EXIT_TO_dBUG

This function (function code 0x0000) transfers the control back to the dBUG, by terminating the user code. The register context are preserved.


trap #15 Make the call, exit to dBUG.

C example:void board_exit_to_dbug (void)

{


asm (“ trap #15”); /* exit and transfer to dBUG */

}


Freescale Semiconductor A-1

Appendix A Configuring dBUG for Network DownloadsThe dBUG module has the ability to perform downloads over an Ethernet network using the Trivial File Transfer Protocol, TFTP (NOTE: this requires a TFTP server to be running on the host attached to the board). Prior to using this feature, several parameters are required for network downloads to occur. The information that is required and the steps for configuring dBUG are described below.

A.1 Required Network ParametersFor performing network downloads, dBUG needs 6 parameters; 4 are network-related, and 2 are download-related. The parameters are listed below, with the dBUG designation following in parenthesis.

All computers connected to an Ethernet network running the IP protocol need 3 network-specific parameters. These parameters are:

Internet Protocol, IP, address for the computer (client IP),IP address of the Gateway for non-local traffic (gateway IP), andNetwork netmask for flagging traffic as local or non-local (netmask).

In addition, the dBUG network download command requires the following three parameters:IP address of the TFTP server (server IP),Name of the file to download (filename),Type of the file to download (filetype of S-record, COFF, ELF, or Image).

Your local system administrator can assign a unique IP address for the board, and also provide you the IP addresses of the gateway, netmask, and TFTP server. Fill out the lines below with this information.

Client IP: ___.___.___.___(IP address of the board)Server IP: ___.___.___.___(IP address of the TFTP server)Gateway: ___.___.___.___(IP address of the gateway)Netmask: ___.___.___.___(Network netmask)

Configuring dBUG for Network Downloads


A-2 Freescale Semiconductor

A.2 Configuring dBUG Network ParametersOnce the network parameters have been obtained, the dBUG Rom Monitor must be configured. The following commands are used to configure the network parameters.

set client <client IP> set server <server IP> set gateway <gateway IP> set netmask <netmask> set mac <addr>

For example, the TFTP server is named ‘santafe’ and has IP address 123.45.67.1. The board is assigned the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250, and the netmask is 255.255.255.0. The MAC address is chosen arbitrarily and is unique. The commands to dBUG are:

set client 123.45.68.15 set server 123.45.67.1 set gateway 123.45.68.250 set netmask 255.255.255.0 set mac 00:CF:52:82:EB:01

The last step is to inform dBUG of the name and type of the file to download. Prior to giving the name of the file, keep in mind the following.

Most, if not all, TFTP servers will only permit access to files starting at a particular sub-directory. (This is a security feature which prevents reading of arbitrary files by unknown persons.) For example, SunOS uses the directory /tftp_boot as the default TFTP directory. When specifying a filename to a SunOS TFTP server, all filenames are relative to /tftp_boot. As a result, you normally will be required to copy the file to download into the directory used by the TFTP server.

A default filename for network downloads is maintained by dBUG. To change the default filename, use the command:

set filename <filename>

When using the Ethernet network for download, either S-record, COFF, ELF, or Image files may be downloaded. A default filetype for network downloads is maintained by dBUG as well. To change the default filetype, use the command:

set filetype <srecord|coff|elf|image>

Continuing with the above example, the compiler produces an executable COFF file, ‘a.out’. This file is copied to the /tftp_boot directory on the server with the command:

rcp a.out santafe:/tftp_boot/a.out

Change the default filename and filetype with the commands:set filename a.out set filetype coff

Finally, perform the network download with the ‘dn’ command. The network download process uses the configured IP addresses and the default filename and filetype for initiating a TFTP download from the TFTP server.



Freescale Semiconductor A-3

A.3 Troubleshooting Network ProblemsMost problems related to network downloads are a direct result of improper configuration. Verify that all IP addresses configured into dBUG are correct. This is accomplished via the ‘show ’command.

Using an IP address already assigned to another machine will cause dBUG network download to fail, and probably other severe network problems. Make certain the client IP address is unique for the board.

Check for proper insertion or connection of the network cable. Is the status LED lit indicating that network traffic is present?

Check for proper configuration and operation of the TFTP server. Most Unix workstations can execute a command named ‘tftp’ which can be used to connect to the TFTP server as well. Is the default TFTP root directory present and readable?

If ‘ICMP_DESTINATION_UNREACHABLE’ or similar ICMP message appears, then a serious error has occurred. Reset the board, and wait one minute for the TFTP server to time out and terminate any open connections. Verify that the IP addresses for the server and gateway are correct. Also verify that a TFTP server is running on the server.



A-4 Freescale Semiconductor


Freescale Semiconductor B-1

Appendix B Schematics

B.1 MCF5271EVM Schematics

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QSPI_DIN

QSPI_PCS1

QSPI_DOUTQSPI_PCS0

QSPI_SCK

I2C_SCLI2C_SDA

/U2RTS/U2CTS

/RSTOUT/IRQ[7:1]

She

et 3

AS

RA

M

B_A[23:0]

/BS[3:0]

/OE

B_D[31:0]

R/W

/CS[7:0]

She

et 1

1R

eset

Con

fig &

Clo

cks

/RESET/BDM_RSTIN

/EXT_RSTIN

XTALEXTAL

ETH_CLK/IRQ[7:1]

D[31:0]

JTAG_EN/RCON

CLKMOD[1:0]/RSTOUT

CLKOUT

/CS[7:0]

/BS[3:0]

/OER/W/TS

/TIP/TA

/TEA

TSIZ0

TSIZ1

DTIN0DTOUT0

DTIN1

DTIN2

DTIN3

DTOUT1

DTOUT2

DTOUT3

TMS/BKPTTDI/DSI

TDO/DSOTRST/DSCLK

She

et 4

Buf

fers

A[23:0]

B_A[23:0]

D[31:0]

B_D[31:0]

R/W

/CS[7:0]

She

et 6

Deb

ug

DDATA[3:0]

PST[3:0]

TCLK/PSTCLK

TDO/DSO

TMS/BKPT

TDI/DSI

TRST/DSCLK

/TA

BDM_/RSTIN

She

et 9

Fla

sh M

emor

y

B_A[23:0]B_D[31:0]/CS[7:0]

/OE

R/W

She

et 1

2S

DR

AM

/BS[3:0]

/SD_CS0

/SD_WESD_SCKE

D[31:0]

/SD_RAS

A[23:0]

CLKOUT

/SD_CAS

She

et 8

Exp

ansi

on C

onne

ctor

s

/U0C

TS

U0R

XD

DT

OU

T0

DT

IN0

U0T

XD

/U0R

TS

CLK

MO

D[1

:0]

D[3

1:0]

/EX

T_R

ST

IN

/OE

DT

OU

T1

DT

IN1

/IR

Q[7

:1]

TS

IZ0

TC

LK/P

ST

CLK

DT

OU

T2

DT

IN2

TD

I/DS

IT

DO

/DS

O

TM

S/B

KP

T

TR

ST

/DS

CLK

PS

T[3

:0]

DD

AT

A[3

:0]

JTA

G_E

N/R

CO

N

/RS

TO

UT

/RE

SE

T

EX

TA

LX

TA

L

/SD

_CS

1

CLK

OU

T

/SD

_CA

S

/SD

_CS

0/S

D_R

AS

R/W

/SD

_W

E

/TS

/TIP

/TA

/TE

A

DT

OU

T3

DT

IN3

A[2

3:0]

/CS

[7:0

]

TS

IZ1

U1T

XD

U1R

XD

/U1R

TS

U2T

XD

/U1C

TS

U2R

XD

SD

_SC

KE

QS

PI_

PC

S1

/BS

[3:0

]

QS

PI_

CS

0Q

SP

I_D

OU

TQ

SP

I_D

IN

I2C

_SD

A

QS

PI_

SC

K

I2C

_SC

L

EM

DC

EM

DIO

/U2C

TS

/U2R

TS

EC

OL

EC

RS

ER

XD

VE

RX

ER

ER

XC

LKE

RX

D0

ER

XD

1E

RX

D2

ER

XD

3E

TX

EN

ET

XE

RE

TX

CLK

ET

XD

0E

TX

D1

ET

XD

2E

TX

D3

She

et 5

CP

U A[2

3:0]

D[3

1:0]

/CS

[7:0

]

U1T

XD

/BS

[3:0

]

/OE

/IR

Q[7

:1]

TS

IZ0

TS

IZ1

CLK

MO

D[1

:0]

DT

OU

T1

DT

IN1

DT

OU

T2

DT

IN2

TC

LK/P

ST

CLK

PS

T[3

:0]

DD

AT

A[3

:0]

XT

AL

EX

TA

L

/SD

_CS

1/S

D_C

S0

JTA

G_E

N

CLK

OU

T

/SD

_RA

S/S

D_C

AS

R/W

/SD

_W

E

/TS

/TIP

/TA

/TE

A

DT

OU

T3

DT

IN3

U0R

XD

QS

PI_

PC

S1

/U1C

TS

/RS

TO

UT

/RC

ON

DT

OU

T0

TD

O/D

SO

/U0C

TS

SD

_SC

KE

/U1R

TS

TR

ST

/DS

CLK

QS

PI_

DO

UT

/U0R

TS

QS

PI_

PC

S0

U1R

XD

TM

S/B

KP

T

U0T

XD

QS

PI_

DIN

U2R

XD

TD

I/DS

I

QS

PI_

SC

K

U2T

XD

DT

IN0

EM

DIO

EM

DC

/RE

SE

T

I2C

_SD

AI2

C_S

CL

ER

XE

R

ET

XD

2E

TX

D1

ET

XE

N

ET

XD

3

ET

XE

R

ER

XD

0E

RX

D1

ER

XD

2E

RX

D3

ER

XC

LK

ER

XD

V

ET

XC

LKE

TX

D0

EC

OL

EC

RS

/U2R

TS

/U2C

TS

She

et 7

Eth

erne

t

/RSTOUT

ETH_CLK

EMDIOEMDC

/IRQ[7:1]

ECOLECRSERXDVERXERERXCLKERXD0ERXD1ERXD2ERXD3ETXENETXERETXCLKETXD0ETXD1ETXD2ETXD3

She

et 1

0P

SU

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_A

[23:

0]

/BS

2

B_D

20

B_A

[23:

0]

/BS

0/C

S1

B_A

[23:

0]

/BS

1

/BS

3

/BS[3:0]

/CS

1

B_D

10

B_D

18

B_D

11

B_D

24

B_D

16

B_D

13

B_D

5

B_D

0

B_D

8

B_D

19

B_D

25

B_D

17

B_D

7

B_D

12

B_D

1

B_D

28

B_D

31

B_D

23

B_D

26

B_D

[31:

0]

B_D

[31:

0]

B_D

15

B_D

22

B_D

29

B_D

21B

_D27

B_D

9

B_D

2B

_D3

B_D

6

B_D

4

B_D

14

B_D

30

B_A

5

B_A

3

B_A

18

B_A

18

B_A

9

B_A

7

B_A

4

B_A

10B

_A11

B_A

17

B_A

2

B_A

5

B_A

19

B_A

14

B_A

19

B_A

9B

_A15

B_A

15

B_A

12

B_A

4

B_A

2

B_A

10

B_A

7

B_A

16

B_A

3

B_A

6

B_A

13

B_A

12B

_A11

B_A

16B

_A8

B_A

13

B_A

17

B_A

6

B_A

8B

_A14

/CS

[7:0

]

B_A

[23:

0]

/BS

[3:0

]

/OE

B_D

[31:

0]

/CS

[7:0

]

R/W

+3.

3V+

3.3V

+3.

3V+

3.3V

+3.

3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Asy

nchr

onou

s S

RA

M1.

3

M52

71E

VB

B

313

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Asy

nchr

onou

s S

RA

M1.

3

M52

71E

VB

B

313

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Asy

nchr

onou

s S

RA

M1.

3

M52

71E

VB

B

313

Wed

nesd

ay, A

pril

21, 2

004

AS

RA

M U

pper

16-

bit w

ord

NO

TE

: /B

S3

sele

cts

the

mos

tsi

gnifi

cant

byt

e la

ne a

cces

s an

d/B

S0

the

leas

t sig

nific

ant.

AS

RA

M L

ower

16-

bit w

ord

TS

OP

II

TS

OP

II

Eac

h A

SR

AM

is 2

56K

x 1

6bit

(512

KB

)T

otal

AS

RA

M a

vaila

ble

= 1

MB

NO

TE

: Alte

rnat

ive

AS

RA

M's

with

the

sam

e P

CB

foot

prin

t an

d fu

nctio

nalit

y ar

e :-

Ren

esas

HM

62W

1625

5HC

JP-1

2

NO

TE

: Pla

ce th

e S

MT

foot

prin

ts fo

r bo

thth

ese

AS

RA

M's

on

the

unde

rsid

e of

the

PC

B c

lose

to th

e C

PU

.

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

A0

1

A1

2

A2

3

A3

4

A4

5

/CE

6

I/00

7

I/01

8

I/02

9

I/03

10

VC

C1

1

VS

S1

2

I/04

13

I/05

14

I/06

15

I/07

16

/WE

17

A5

18

A6

19

A7

20

A8

21

A9

22

A1

02

3A

11

24

A1

22

5A

13

26

A1

42

7N

C2

8I/O

82

9I/O

93

0I/

O1

03

1I/

O1

13

2V

CC

33

VS

S3

4I/

O1

23

5I/

O1

33

6I/

O1

43

7I/

O1

53

8/B

LE

39

/BH

E4

0/O

E4

1A

15

42

A1

64

3A

17

44

U2

CY

7C10

41C

V33

10Z

C (

No

popu

late

)

U2

CY

7C10

41C

V33

10Z

C (

No

popu

late

)

C1

1nF

C1

1nF

C2

1nF

C2

1nF

C3

1nF

C3

1nF

C4

1nF

C4

1nF

A0

1

A1

2

A2

3

A3

4

A4

5

/CE

6

I/00

7

I/01

8

I/02

9

I/03

10

VC

C1

1

VS

S1

2

I/04

13

I/05

14

I/06

15

I/07

16

/WE

17

A5

18

A6

19

A7

20

A8

21

A9

22

A1

02

3A

11

24

A1

22

5A

13

26

A1

42

7N

C2

8I/O

82

9I/O

93

0I/

O1

03

1I/

O1

13

2V

CC

33

VS

S3

4I/

O1

23

5I/

O1

33

6I/

O1

43

7I/

O1

53

8/B

LE

39

/BH

E4

0/O

E4

1A

15

42

A1

64

3A

17

44

U1

CY

7C10

41C

V33

10Z

C (

No

popu

late

)

U1

CY

7C10

41C

V33

10Z

C (

No

popu

late

)

C7

0.1u

FC

70.

1uF

C6

0.1u

FC

60.

1uF

C5

0.1u

FC

50.

1uF

C8

0.1u

FC

80.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_A

18

B_A

15

B_D

17

D7

A0

B_D

8

D18

D28

D[3

1:0]

B_A

17

A18

B_D

16

A11

A7

B_D

30

D10

D23

B_D

21

B_D

10

D30

B_D

1D

2

B_A

19

B_A

4

B_D

18

D20

B_D

[31:

0]

A1

D8

B_D

9

D16

A19

B_D

13

B_D

2

D6

B_D

26

A12

A8

D17

B_D

31

B_D

11

B_D

22

B_A

20

B_A

5

B_D

19

A2

B_D

27

B_D

3

A13

A9

D11

B_D

12

D0

B_A

21

B_A

6

A20

A3

B_A

10

A15

D9

B_D

28

A14

B_A

22

B_A

7

B_D

0

B_D

23

D19

D22

D21

D24

A4

D25

B_A

0

B_A

11

B_D

4

B_A

16

B_A

8

D5

A[2

3:0]

B_D

24

D3

A21

D26

B_A

12

B_A

1

B_D

5

D14

B_A

[23:

0]

B_A

9

D12

B_D

25

B_A

2

B_A

13

B_D

6

D13

D15

A22

A16

B_D

14

A5

B_A

14

B_A

3

D4

B_D

7

D1

D27

A17

B_D

15

A10

A6

B_D

29

B_D

20

D31

D29

B_A

23A

23

/CS

2

/CS

0

/CS

1

D[3

1:0]

B_D

[31:

0]

R/W

A[2

3:0]

B_A

[23:

0]

/CS

[7:0

]

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Buf

fers

1.3

M52

71E

VB

B

413

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Buf

fers

1.3

M52

71E

VB

B

413

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Buf

fers

1.3

M52

71E

VB

B

413

Wed

nesd

ay, A

pril

21, 2

004

AD

DR

ES

S B

US

BU

FF

ER

S

Add

ress

and

Dat

a B

us b

uffe

rs/tr

ansc

eive

rs u

sed

to b

uffe

rth

e si

gnal

s fo

r th

e A

SR

AM

and

Fla

sh m

emor

ies

and

the

US

B c

ontr

olle

r.

DA

TA

BU

S T

RA

NS

CE

IVE

RS

AN

D G

ate

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1O

E4

8

2O

E2

5

2DIR

24

GN

D4

GN

D1

0

GN

D1

5

GN

D2

1

GN

D2

8

GN

D3

4

GN

D3

9

GN

D4

5

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C1

8

VC

C3

1

VC

C4

2

U3

MC

74LC

X16

245D

T

U3

MC

74LC

X16

245D

T

C9

0.1u

FC

90.

1uF

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1O

E4

8

2O

E2

5

2DIR

24

GN

D4

GN

D1

0

GN

D1

5

GN

D2

1

GN

D2

8

GN

D3

4

GN

D3

9

GN

D4

5

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C1

8

VC

C3

1

VC

C4

2

U6

MC

74LC

X16

245D

T

U6

MC

74LC

X16

245D

T

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1DIR

1

1O

E4

8

2O

E2

5

2DIR

24

GN

D4

GN

D1

0

GN

D1

5

GN

D2

1

GN

D2

8

GN

D3

4

GN

D3

9

GN

D4

5

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

VC

C7

VC

C1

8

VC

C3

1

VC

C4

2

U4

MC

74LC

X16

245D

T

U4

MC

74LC

X16

245D

T

T/R

1

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

A7

9

GN

D1

0

VC

C2

0

OE

19

B0

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

U7 MC

74LC

X24

5DT

U7 MC

74LC

X24

5DT

C14

1nF

C14

1nF

C10

0.1u

FC

100.

1uF

C11

0.1u

FC

110.

1uF

11

22

33

44

55

66

77

88

RP

2

4x 4

.7K

RP

2

4x 4

.7K

A GN

DB

CV

CC Y

U5

SN

74LV

C1G

11

U5

SN

74LV

C1G

11

11

22

33

44

55

66

77

88

RP

1

4x 4

.7K

RP

1

4x 4

.7K

C12

0.1u

FC

120.

1uF

C13

1nF

C13

1nF

C16

1nF

C16

1nF

C15

1nF

C15

1nF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CLK

MO

D[1

:0]

CLK

MO

D1

CLK

MO

D0

D[31:0]

D[3

1:0]

D[3

1:0]

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D10

D15

D13

D9

D3D2D1D0D6D5D4D8D7D11

D12D14

/BS

[3:0

]

/BS2/BS3

/BS1/BS0

/CS

[7:0

]

/CS4

/CS6/CS1/CS5/CS0

/CS3/CS7/CS2

A[2

3:0]

A[2

3:0]

A22A23

A19A20A17

A16A15

A[23:0]

A18

A14

A13

A21

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

DD

AT

A[3

:0]

DDATA3

DDATA2DDATA1DDATA0

PS

T[3

:0]

PST3PST2PST1

PST0

/IRQ

[7:1

]

/IRQ1/IRQ2/IRQ3/IRQ4

/IRQ5/IRQ6/IRQ7

A[2

3:0]

D[3

1:0]

/CS

[7:0

]

/BS

[3:0

]

/OE

/IRQ

[7:1

]

TSIZ0

TSIZ1

CLK

MO

D[1

:0]

DTOUT1DTIN1

DTOUT2DTIN2

TCLK/PSTCLK

PS

T[3

:0]

DD

AT

A[3

:0]

XT

AL

EX

TA

L

/SD

_CS

1

/SD

_CS

0

JTA

G_E

N

CLK

OU

T

/SD

_RA

S/S

D_C

AS

R/W

/SD

_W

E

/TS

/TIP

/TA

/TE

A

DT

OU

T3

DT

IN3

U0R

XD

QSPI_PCS1

/RS

TO

UT

/RC

ON

DT

OU

T0

TDO/DSO

/U0C

TS

SD_SCKE

TRST/DSCLK

/U0R

TS

QSPI_PCS0

TMS/BKPT

U0T

XD

TDI/DSI

DT

IN0

/RE

SE

T

U2RXD

U2TXD

I2C

_SD

AI2

C_S

CL

/U2C

TS

/U2R

TS

ETXD3

ETXD0

ER

XD

0

ER

XD

1E

RX

D2

ER

XD

3

ER

XC

LKE

RX

DV

EC

OL

EC

RS

ER

XE

R

ETXCLK

ETXD2

ETXD1

ET

XE

N

ETXER

EM

DC

EMDIOQSPI_SCKQSPI_DINQSPI_DOUT

/U1RTSU1RXD

/U1CTS

U1TXD

+1.5

VP

+3.3

VP

+3.3

VP

VS

SP

LLV

SS

PLL

VS

SP

LL

+1.5

VP

+3.3

VP

+3.3

VP

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

CP

U1.

3

M52

71E

VB

C

513

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

CP

U1.

3

M52

71E

VB

C

513

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

CP

U1.

3

M52

71E

VB

C

513

Wed

nesd

ay, A

pril

21, 2

004

NO

TE

: Pla

ce C

42, C

43 &

L1

as c

lose

to p

ins

L14

& M

13 a

s po

ssib

le u

sing

ase

para

te g

roun

d pl

ane.

Place R1 as close to pin E8 on U8 as possible.

Pla

ce R

2 as

clo

se to

pin

L13

as

poss

ible

.

Pla

ce R

P3

as c

lose

to p

ins,

K11

,K

12, K

13 &

L12

as

poss

ible

.

PLL

Filt

er C

ircui

t

Def

ault

setti

ng fo

r JP

1 &

JP2

is b

etw

een

pins

1&

2

Ple

ase

plac

e th

e ca

paci

tors

bel

ow, w

hich

are

by-

pass

/dec

oupl

ing

capa

cito

rs,

as p

airs

as

clos

e as

pos

sibl

e to

the

VD

D &

VS

S p

ins

of U

8.

Mo

toro

la C

old

Fir

eM

icro

pro

cess

or

MC

F52

71

TM

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

R1

22R1

22

C20

100p

F

C20

100p

F

C19

100p

F

C19

100p

F

C31

0.1u

F

C31

0.1u

F

VSSA1

ER

XD

0B

1

ER

XE

RB

2

ER

XD

2C

1

ER

XD

1C

2

ET

XE

NC

3

ER

XC

LKD

1

ER

XD

VD

2

ER

XD

3D

3

EM

DC

D4

EC

RS

E1

EC

OL

E2

NC

E3

DT

IN0

E4

VD

DE

5

U0T

XD

F1

U0R

XD

F2

U0C

TS

F3

DT

OU

T0

F4

TE

ST

F5

VS

SF

6

D31

G1

D30

G2

U0R

TS

G3

Cor

e V

DD

G4

CLK

MO

D1

G5

VD

DG

6

D29

H1

D28

H2

D27

H3

D26

H4

CLK

MO

D0

H5

VS

SH

6

D25

J1

D24

J2

D23

J3

D22

J4

VS

SJ5

VD

DJ6

D21

K1

D20

K2

D19

K3

D18

K4

D17

L1

D16

L2

D10

L3

Cor

e V

DD

L4

D15

M1

D13

M2

D9

M3

D14 N1

D12 N2

VSS P1

D11 P2

D7 P3

D8 N3

D4 P4

D5 N4

D6 M4

D0 P5

D1 N5

D2 M5

D3 L5

VDD K5

TSIZ1 P6

OE N6

DTOUT1 M6

DTIN1 L6

VDD K6

TSIZ0 P7

IRQ7 N7

IRQ6 M7

IRQ5 L7

VSS K7

VSS J7

VDD H7

IRQ4 P8

IRQ3 N8

IRQ2 M8

IRQ1 L8

VDD K8

VDD J8

VDD H8

TCLK/PSTCLK P9

TRST/DSCLK N9

DTIN2 M9

DTOUT2 L9

JTAG_EN K9

TMS/BKPT P10

TDO/DSO N10

TDI/DSI M10

PST0 L10

RCON K10

PST1 P11

PST2 N11

PST3 M11

DDATA0 L11

DDATA1 P12

DDATA2 N12

DD

AT

A3

M12

RS

TO

UT

P13

RE

SE

TN

13V

SS

P14

XT

AL

N14

EX

TA

LM

14V

DD

PLL

M13

VS

SP

LLL1

4S

D_C

S0

L13

SD

_CS

1L1

2C

LKO

UT

K14

SD

_WE

K13

SD

_CA

SK

12S

D_R

AS

K11

TE

AJ1

4R

/WJ1

3S

DA

J12

SC

LJ1

1V

DD

J10

VS

SJ9

DT

IN3

H14

TSH

13T

IPH

12TA

H11

NC

H10

VD

DH

9D

TO

UT

3G

14A

0G

13A

1G

12A

2G

11N

CG

10V

SS

G9

A3

F14

A4

F13

A5

F12

Cor

e V

DD

F11

VS

SF

10V

DD

F9

A6

E14

A7

E13

A8

E12

A9

E11

A10

D14

A11

D13

A12

D12

A21

D11

A13

C14

A14

C13

A18

C12

A15B14A16B13 VSSA14A17A13A20A12 A19B12CS4A11 A23B11A22C11CS6A10 CS1B10CS5C10 CS0D10VDDE10CS3A9 CS7B9CS2C9 U1TXD/CAN0TXD9VSSE9

U2TXDA8 U1CTSB8U1RTSC8 U1RXD/CAN0RXD8

SD_SCKEE8VSSF8 VDDG8

U2RXDA7 QSPI_PCS1B7BS0C7BS1D7 VDDE7VDDF7 VSSG7

QSPI_PCS0A6BS3B6 BS2C6

Core VDDD6 VSSE6QSPI_DOUTA5

QSPI_DINB5 QSPI_SCKC5EMDIOD5 ETXD2A4ETXD0B4ETXD1C4 ETXD3A3ETXERB3 ETXCLKA2

U8

MC

F52

71C

VM

150

U8

MC

F52

71C

VM

150

C23

0.1u

F

C23

0.1u

F

R2

22R

222

C26

1nF

C26

1nF

C25

10uF

TA

NT

.C

2510

uF T

AN

T.

12

3

JP2

JP2

C27

1nF

C27

1nF

C41

1nF

C41

1nF

C39

1nF

C39

1nF

C21

0.1u

F

C21

0.1u

F

C43

1000

pFC

4310

00pF

C29

100p

F

C29

100p

F

C32

0.1u

F

C32

0.1u

F

C18

1nF

C18

1nF

C35

100p

F

C35

100p

F

1V

IA3

VIA

3

C24

0.1u

F

C24

0.1u

F

C36

100p

F

C36

100p

F

C37

100p

F

C37

100p

F

12

3

JP1

JP1

C40

1nF

C40

1nF

C33

0.1u

F

C33

0.1u

F

C28

100p

F

C28

100p

F

C22

0.1u

F

C22

0.1u

F

C38

100p

F

C38

100p

F

C30

0.1u

F

C30

0.1u

F

1V

IA1

VIA

1

C34

1nF

C34

1nF

C17

1nF

C17

1nF

11

22

33

44

55

66

77

88

RP

34x

22

RP

34x

22

L1 10uH

L1 10uH

1V

IA2

VIA

2

C42

0.1u

FC

420.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

AT

A2

DD

AT

A1

DD

AT

A0

DD

AT

A[3

:0]

PS

T0

DD

AT

A[3

:0]

PS

T3

PS

T2

DD

AT

A3

PS

T1

PS

T[3

:0]

PS

T[3

:0]

DD

AT

A[3

:0]

PS

T[3

:0]

TD

O/D

SO

TM

S/B

KP

T

TD

I/DS

I

TR

ST

/DS

CLK

BD

M_/

RS

TIN

/TA

TC

LK/P

ST

CLK

+1.5

V+3

.3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

BD

M/J

TA

G D

ebug

Por

t1.

3

M52

71E

VB

A

613

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

BD

M/J

TA

G D

ebug

Por

t1.

3

M52

71E

VB

A

613

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

BD

M/J

TA

G D

ebug

Por

t1.

3

M52

71E

VB

A

613

Wed

nesd

ay, A

pril

21, 2

004

Def

ault

setti

ng fo

rJP

3 is

fitte

d.

NO

TE

: JP

3 is

req

uire

d fo

r so

me

of th

e le

gacy

BD

Mca

bles

that

con

nect

pin

s 9

& 2

5 of

the

BD

M in

terf

ace

inte

rnal

ly. M

ore

rece

nt c

able

s su

ppor

t bot

h co

re &

I/O

volta

ges.

Ple

ase

chec

k w

ith y

our

BD

M c

able

sup

plie

r.

Cor

e V

olta

ge

IMP

OR

TA

NT

NO

TE

: ON

LY 3

.3V

BD

M d

ebug

ging

cab

les

can

be u

sed

with

the

MC

F52

71 p

roce

ssor

.

I/O V

olta

ge

NO

TE

: 4.7

K p

ull u

p re

sist

ors

are

used

on

sign

als

/BK

PT

, DS

CLK

, DS

I, D

SO

& /R

ES

ET

. A 1

K p

ull u

p is

use

d fo

r /T

A. S

ee s

heet

11

of th

e sc

hem

atic

s.

Def

ault

setti

ng -

FIT

TE

D

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

R3

10K

R3

10K

12

JP4

JP4

1 3 5 7 9 11 13 15 17 19 21 23 25

2 4 6 8 10 12 14 16 18 20 22 24 26

J1J1

12

JP3

JP3

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

/IRQ

[7:1

]/IR

Q2

/RS

TO

UT

ET

H_C

LK

EM

DIO

EM

DC

/IRQ

[7:1

]

ER

XD

3E

RX

D2

ER

XD

1E

RX

D0

ER

XD

VE

RX

CLK

ER

XE

RE

TX

CLK

ET

XE

RE

TX

EN

ET

XD

0E

TX

D1

ET

XD

2E

TX

D3

EC

OL

EC

RS

+3.

3V

+3.

3V

+2.

5VP

LL+

2.5V

A

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+2.

5VA

+2.

5VA

+2.

5VA

+2.

5VA

+2.

5VA

+2.

5VA

+2.

5VP

LL

+2.

5V

+2.

5V

+2.

5V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

10/1

00B

aseT

Eth

erne

t Tra

nsce

iver

1.3

M52

71E

VB

B

713

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

10/1

00B

aseT

Eth

erne

t Tra

nsce

iver

1.3

M52

71E

VB

B

713

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

10/1

00B

aseT

Eth

erne

t Tra

nsce

iver

1.3

M52

71E

VB

B

713

Wed

nesd

ay, A

pril

21, 2

004

Pla

ce s

ilk s

cree

n LE

D la

bels

next

to D

1 th

ru' D

4.

Sep

arat

e R

J45

conn

ecto

rch

assi

s gr

ound

.

NO

TE

: Eth

erne

t Ch.

phy

sica

l add

r. d

efau

lt se

tting

is a

ddr.

=1

sele

cted

via

inte

rnal

res

isto

r bi

asin

g du

ring

rese

t.

Pla

ce R

P4

& R

P5

as c

lose

to U

11 a

s po

ssib

le.

Pla

ce R

P6

& R

P7

as c

lose

to th

eM

CF

5271

(C

PU

U8)

as

poss

ible

.Li

nk

Col

lisio

n

100B

aseT

Ful

l Dup

lex

Ana

log

Eth

erne

t Pla

ne

GR

EE

N

GR

EE

N

GR

EE

N

GR

EE

N

Pla

ce th

e ca

paci

tors

abo

vecl

ose

to p

ins

7 an

d 24

on

U9.

Pla

ce R

4, R

5, R

6 &

R7

clo

se to

U9.

NO

TE

: U9

KS

8721

BL

has

an o

n-ch

ip L

DO

that

deriv

es th

e +

2.5V

sup

ply

from

the

+3.

3V s

uppl

y.

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

R4

49.9

1%

R4

49.9

1%

D3

D3

C53

0.1u

FC

530.

1uF

R8

4.7K

R8

4.7K

C54

47uF

C54

47uF

C55

0.1u

FC

550.

1uF

C57

0.1u

FC

570.

1uF

C51

0.1u

FC

510.

1uF

1 122

3 344

5 566

7 788

RP

6

4x 5

1

RP

6

4x 5

1

MD

IO1

MD

C2

RX

D3/

PH

YA

D1

3

RX

D2/

PH

YA

D2

4

RX

D1/

PH

YA

D3

5

RX

D0/

PH

YA

D4

6

VD

DIO

7

GN

D8

RX

DV

/PC

S_L

PB

K9

RX

C1

0

RX

ER

/ISO

11

GN

D1

2

VDDC 13

TXER 14

TXC/REFCLK 15

TXEN 16

TXD0 17

TXD1 18

TXD2 19

TXD3 20

COL/RMII 21

CRS/RMII_LPBK 22

GND 23

VDDIO 24INT

#/P

HY

AD

02

5LE

D0/

TE

ST

26

LE

D1/S

PD

100

27

LED

2/D

UP

LEX

28

LED

3/N

WA

YE

N2

9P

D#

30

VD

DR

X3

1R

X-

32

RX

+3

3F

XS

D/F

XE

N3

4G

ND

35

GN

D3

6

REXT37VDDRCV38

GND39TX-40TX+41

VDDTX42GND43GND44

XO45XI46

VDDPLL47RST#48

U9

KS

8721

BL

U9

KS

8721

BL

C47

0.1u

FC

470.

1uF

C49

0.1u

FC

490.

1uF

R11

220

R11

220

R13

220

R13

220

C59

10nF

C59

10nF

C44

0.1u

FC

440.

1uF

C45

0.1u

FC

450.

1uF

D2

D2

12

FB

2

ST

EW

AR

D H

I120

6T50

0R-0

0

FB

2

ST

EW

AR

D H

I120

6T50

0R-0

0

C48

1nF

C48

1nF

C52

0.1u

FC

520.

1uF

R14

220

R14

220

C60

10uF

C60

10uF

R6

49.9

1%

R6

49.9

1%

R9

6.49

K 1

%

R9

6.49

K 1

%

C56

0.1u

FC

560.

1uF

11

22

33

44

55

66

77

88

RP

54x

51

RP

54x

51

1 122

3 344

5 566

7 788

RP

7

4x 5

1

RP

7

4x 5

1

11

22

33

44

55

66

77

88

RP

44x

51

RP

44x

51

R7

49.9

1%

R7

49.9

1%

D4

D4

R12

220

R12

220

D1

D1

TX

+1

TX

-2

RX

+3

CT

_T

X4

CT

_RX

5

RX

-6

NC

7

GN

D8

J2 Hal

o H

FJ1

1-24

50E

J2 Hal

o H

FJ1

1-24

50E

C58

0.1u

F

C58

0.1u

F

12

FB

1

ST

EW

AR

D H

I120

6T50

0R-0

0

FB

1

ST

EW

AR

D H

I120

6T50

0R-0

0

C50

47uF

C50

47uF

R5

49.9

1%

R5

49.9

1%

R10

10K

R10

10K

C46

1nF

C46

1nF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

D28

D24

D25

D19

D16

CLK

MO

D1

D31

D26

D27

D13

A9

A7

A20

A19

A3

DD

AT

A3

A0

A5

A16

A22

A17

A14

A4

A8

D7D11

PST1 PST2

/IRQ2

D3

DDATA1

D1

/IRQ1

/IRQ6

DDATA2

D8

DDATA0

D4

D0

D5

CLK

MO

D0

D[3

1:0]

D[3

1:0]

D[3

1:0]

D29

D30

D23

D21

D22

D20

D17

D18

D9

D12

D15

D[3

1:0]

D14 D10D6

D2

/IRQ

[7:1

]

/IRQ

[7:1

]

/IRQ7

/IRQ3 /IRQ4/IRQ5

/IRQ

[7:1

]

PS

T[3

:0]

PS

T[3

:0]

PS

T[3

:0]

PST0

PST3

DD

AT

A[3

:0]

DD

AT

A[3

:0]

DD

AT

A[3

:0]

A[2

3:0]

A[2

3:0]

A[2

3:0]

A2

A1

A12

A6

A10

A11

A13

A15

A18

A21

A23

/CS

[7:0

]

/BS

[3:0

]

/CS

[7:0

]/C

S[7

:0]

/CS4/CS1/CS6/CS3

/CS0/CS5/CS7/CS2

/BS0/BS1/BS2/BS3

/U0C

TS

U0R

XD

DT

OU

T0

DT

IN0

U0T

XD

/U0R

TS

CLK

MO

D[1

:0]

D[3

1:0]

/OEDTOUT1

DTIN1

/IRQ

[7:1

]

TSIZ0

TCLK/PSTCLKDTOUT2 DTIN2

TDI/DSITDO/DSO

TMS/BKPTTRST/DSCLK

PS

T[3

:0]

DD

AT

A[3

:0]

JTAG_EN /RCON/RSTOUT

/RESET

EX

TA

LX

TA

L/S

D_C

S1

CLK

OU

T/S

D_C

AS

/SD

_CS

0/S

D_R

AS

R/W

/SD

_W

E/T

S/T

IP/T

A/T

EA

DT

OU

T3

DT

IN3

A[2

3:0]

/CS

[7:0

]

TSIZ1

U1TXDU1RXD/U1RTS

U2TXD

/U1CTSU2RXD

SD_SCKE

QSPI_PCS1/U2RTS

/BS

[3:0

]

QSPI_CS0QSPI_DOUT

QSPI_DINI2C_SDA

QSPI_SCKI2C_SCL

EMDCEMDIO

/EX

T_R

ST

IN

/U2CTSETXD0

ETXD1ETXD2

ETXERETXEN

ETXCLKERXER

ER

XD

3E

RX

D1

ETXD3

ERXD0

ER

XD

2E

RX

CLK

ER

XD

VE

CO

LE

CR

S

+3.

3V+

1.5V

+3.

3V+

5V+

3.3V

+1.

5V+

3.3V

+5V

+3.

3V

+1.

5V

+3.

3V +5V

+3.

3V+5V

+1.

5V

+3.

3V

+5V

+3.

3V

+1.

5V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Exp

ansi

on C

onne

ctor

s1.

3

M52

71E

VB

C

813

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Exp

ansi

on C

onne

ctor

s1.

3

M52

71E

VB

C

813

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Exp

ansi

on C

onne

ctor

s1.

3

M52

71E

VB

C

813

Wed

nesd

ay, A

pril

21, 2

004

NO

TE

: if d

esig

ning

a d

augh

ter

card

to fi

t the

se e

xpan

sion

con

nect

ors

plea

se e

nsur

e al

l sig

nals

are

buf

fere

d on

the

daug

hter

car

d.

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

C62

10nF

C62

10nF

C63

470p

FC

6347

0pF

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

J4 AM

P 1

7798

3-2

J4 AM

P 1

7798

3-2

2468

1012141618202224262830323436384042444648505254565860

1357911131517192123252729313335373941434547495153555759

J6 AM

P 1

7798

3-2

J6 AM

P 1

7798

3-2

C76

470p

F

C76

470p

F

C75

470p

F

C75

470p

F

C74

470p

F

C74

470p

F

C73

470p

F

C73

470p

F

C64

470p

FC

6447

0pF

C72

10nF

C72

10nF

C71

10nF

C71

10nF

C68

0.1u

F

C68

0.1u

F

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

J5 AM

P 1

7798

3-2

J5 AM

P 1

7798

3-2

C69

10nF

C69

10nF

2468

1012141618202224262830323436384042444648505254565860

1357911131517192123252729313335373941434547495153555759

J3 AM

P 1

7798

3-2

J3 AM

P 1

7798

3-2

C70

10nF

C70

10nF

C65

1nF

C65

1nF

C61

10nF

C61

10nF

C66

1nF

C66

1nF

C67

0.1u

F

C67

0.1u

F

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B_D15

B_D16

B_A

15

B_A

3

B_A

13

B_A

[23:

0]

B_A

14

B_D17

B_D9

B_D12

B_D21

B_A

2

B_A

21

B_D2

B_D26

B_D13B_D0

B_A

8

B_D28

B_D

[31:

0]

B_A

19

B_A

9

B_A

20

B_D18

B_D25

B_D6

B_D29

B_D1

B_D23

B_A

17

B_D27

B_A

6

B_A

4

B_D19

B_A

7

B_D5

B_D8

B_A

5

B_D11

B_A

11

B_D14

B_D22

B_A

10

B_D4

B_D30

B_D3

B_D10

B_A

18

B_D24

B_D31

B_D7

B_A

16

B_A

12

B_D20

B_D

[31:

0]

B_D

[31:

0]

B_A

[23:

0]

B_D

[31:

0]B

_D[3

1:0]

B_A

[23:

0]B

_A[2

3:0]

/CS

[7:0

]/C

S0

B_A

20

B_A

19B

_A18

B_A

8B

_A7

B_A

6B

_A5

B_A

4B

_A3

B_A

2B

_A1

B_A

9B

_A10

B_A

11B

_A12

B_A

13B

_A14

B_A

15B

_A16

B_A

17

B_D

16B

_D24

B_D

17B

_D25

B_D

18B

_D26

B_D

19B

_D27

B_D

31B

_D23

B_D

30B

_D22

B_D

29B

_D21

B_D

28B

_D20

/OE

R/W

B_A

[23:

0]

B_D

[31:

0]

/CS

[7:0

]

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Fla

sh M

emor

y1.

3

M52

71E

VB

C

913

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Fla

sh M

emor

y1.

3

M52

71E

VB

C

913

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Fla

sh M

emor

y1.

3

M52

71E

VB

C

913

Wed

nesd

ay, A

pril

21, 2

004

NO

TE

: onl

y on

e of

the

foot

prin

ts c

an/w

ill b

epo

pula

ted

- B

GA

(U

11)

OR

SS

OP

(U

10)

32M

Bit

Fla

sh B

oot

Def

ault

setti

ng -

JP

6 fit

ted

acro

ss p

ins

1 &

2

Mem

ory

Siz

e: 1

M x

32-

bit =

4M

B

NO

TE

: The

writ

e pr

otec

t pin

(C

5) s

houl

d no

t be

left

float

ing

asin

cons

ista

nt b

ehav

iour

of t

he F

lash

dev

ice

coul

d re

sult.

To

use

hard

war

e pr

otec

t on

the

top/

botto

m b

oot s

ecto

r se

tJP

5 be

twee

n pi

ns 2

& 3

. To

disa

ble

hard

war

e pr

otec

t set

betw

een

pins

1 &

2 (

defa

ult)

.

16-M

bit F

lash

boo

t

Def

ault

setti

ng -

JP26

fitte

d ac

ross

pins

1&

2

Mem

ory

Siz

e: 1

M x

16

= 2M

B

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

R15

4.7K

R15

4.7K

C84

0.1u

FC

840.

1uF

CE

A8

VS

SB

8

NC

A7

WO

RD

B7

OE

C7

WE

A6

NC

B6

NC

C6

NC

A5

AC

CB

5

WP

C5

NC

D5

NC

E5

A1

A4

A2

B4

A3

C4

A0

D4

A4

A3

A5

B3

VC

CB

2

DQ30B9

VCCC9

DQ15C8

DQ13D9

DQ29D8

DQ14D7

DQ31/A-1D6

DQ12E9

DQ28E8

VSSE7

NCE6

DQ27F9

DQ11F8

DQ10F7

NCF6

DQ26G9

VSSG8

DQ25G7

DQ8G6

VCCH9

DQ24H8

DQ9J9

A19

K8

VC

CJ8

A16

K7

A17

J7

A18

H7

A13

K6

A14

J6

A15

H6

NC

K5

NC

J5

NC

H5

NC

G5

NC

F5

A10

K4

A9

J4

A11

H4

A12

G4

A7

K3

A6

J3

A8

H3

VS

SK

2

DQ17 C1

DQ1 C2

VCC D1

VSS D2

DQ16 D3

DQ0 C3

DQ3 E1

DQ19 E2

DQ18 E3

DQ2 E4

DQ20 F1

DQ4 F2

DQ5 F3

NC F4

VSS G1

DQ6 G2

DQ21 G3

VCC H1

DQ22 J1

DQ23 J2

DQ7 H2

U11

Am

29P

L320

D

U11

Am

29P

L320

D

C85

1nF

C85

1nF

R16

4.7KR16

4.7K

C77

1nF

C77

1nF

1

2

3

JP7

JP7

C78

1nF

C78

1nF

C83

0.1u

FC

830.

1uF

C79

1nF

C79

1nF

C87

0.1u

F

C87

0.1u

F

WE

#1

A18

2

A17

3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11

CE

#12

Vss

13

OE

#14

DQ

015

DQ

816

DQ

117

DQ

918

DQ

219

DQ

1020

DQ

321

DQ

1122

Vcc

23D

Q4

24D

Q12

25D

Q5

26D

Q13

27D

Q6

28D

Q14

29D

Q7

30D

Q15

/A-1

31V

ss32

BY

TE

#33

A16

34A

1535

A14

36A

1337

A12

38A

1139

A10

40A

941

A8

42A

1943

NC

44

U10

AM

D A

m29

PL1

60C

B-6

5RS

U10

AM

D A

m29

PL1

60C

B-6

5RS

C82

0.1u

FC

820.

1uF

C80

1nF

C80

1nF

1

2

3

JP6

JP6

1

2

3

JP5

JP5

R17

4.7K

R17

4.7K

C86

0.1u

F

C86

0.1u

F

R18

4.7K

R18

4.7K

C81

0.1u

FC

810.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+3.

3VP

+5V

+3.

3V

+3.

3V

+3.

3V+

1.5V

+1.

5V+

1.5V

P

+5V

+1.

5V

VS

SP

LL

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pow

er S

uppl

y1.

3

M52

71E

VB

B

1013

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pow

er S

uppl

y1.

3

M52

71E

VB

B

1013

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pow

er S

uppl

y1.

3

M52

71E

VB

B

1013

Wed

nesd

ay, A

pril

21, 2

004

Aug

at 2

5V-0

2

+

NO

TE

: the

pos

itive

term

inal

of e

ach

pow

er c

onne

ctor

mus

t be

show

n on

the

silk

scre

en o

f the

PC

B

-

2-w

ay B

are

Wire

Pow

er C

onne

ctor

JP8

SH

OU

LD B

E IN

ST

ALL

ED

DU

RIN

G A

SS

EM

BLY

DC

vol

tage

inpu

t ran

ge +

7 to

+14

V

5.0V

Reg

ulat

or

-

3.3V

Reg

ulat

or

+

Pow

er J

ack

Con

nect

or -

2.1m

m d

iam

eter

NO

TE

: Dio

des

prev

ent e

xces

sive

diffe

renc

e be

twee

n 3.

3V &

1.5

Vra

ils, a

t pow

er u

p

NO

TE

: Sch

ottk

y D

iode

pre

vent

s ex

cess

ive

diffe

renc

e be

twee

n 3.

3V &

1.5

Vra

ils, a

t pow

er d

own

JP9

SH

OU

LD B

E IN

ST

ALL

ED

DU

RIN

G A

SS

EM

BLY

1.5V

Reg

ulat

or

VS

SP

LL -

filte

red

grou

nd fo

r C

PU

PLL

mod

ule

Filt

ered

gro

und

for

plan

e fo

r et

hern

et R

J45

conn

ecto

r

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

1 2

P2

P2

21

D7

MB

RS

340T

3

D7

MB

RS

340T

3

12

FB

3F

B3

C97

0.1u

F

C97

0.1u

F

VIN

3

ADJ 1

VO

UT

2

U14

LT10

86C

MU

14LT

1086

CM

D9

+5V

GR

EE

N P

OW

ER

LE

D

D9

+5V

GR

EE

N P

OW

ER

LE

D

21

D12

MB

RS

340T

3

D12

MB

RS

340T

3

R22

120

R22

120

R20

560

R20

560

R23

22R

2322

C88

330u

FC

8833

0uF

L2 25uH

L2 25uH

C89

0.1u

FC

890.

1uF

C93

330u

FC

9333

0uF

123

P1

Sw

itchc

raft

RA

PC

712

P1

Sw

itchc

raft

RA

PC

712

12

JP8

JP8

12

FB

4F

B4

54 6

21 3

SW

1

PO

WE

R S

W S

LID

E-S

PS

T(B

oard

Edg

e)

SW

1

PO

WE

R S

W S

LID

E-S

PS

T(B

oard

Edg

e)

21

D5

MB

RS

340T

3D

5M

BR

S34

0T3

VIN

1V

OU

T2

~O

N/O

FF

5

GND 3

FB

4

TAB 6

U12

LM25

96S

-3.3

U12

LM25

96S

-3.3

C90

0.1u

F

C90

0.1u

F

C95

10uF

TA

NT

.C

9510

uF T

AN

T.

21

D14

MB

RS

340T

3

D14

MB

RS

340T

3

C94

0.1u

FC

940.

1uF

21

D8

MB

RS

340T

3D

8M

BR

S34

0T3

12

JP9

JP9

C96

330u

FC

9633

0uF

D10

MR

A40

03T

3

D10

MR

A40

03T

3

D6 +3.

3V G

RE

EN

PO

WE

R L

ED

D6 +3.

3V G

RE

EN

PO

WE

R L

ED

C92

1000

uFC

9210

00uF

R19

270

R19

270

D11 M

RA

4003

T3

D11 M

RA

4003

T3

D13

+1.

5V G

RE

EN

PO

WE

R L

ED

D13

+1.

5V G

RE

EN

PO

WE

R L

ED

R21

0R21

0

L3

25uH

L3

25uH

F1

5A F

ast b

low

.

F1

5A F

ast b

low

.

C91

1nF

C91

1nF

VIN

1V

OU

T2

~O

N/O

FF

5

GND 3

FB

4

TAB 6

U13

LM25

96S

-5U

13LM

2596

S-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

/IRQ

7/IR

Q[7

:1]

D16

D20

D[3

1:0]

D19

D25

D24

D21

CLK

MO

D[1

:0]

CLK

MO

D1

CLK

MO

D0

/IRQ

2

/CS

6/C

S5

/IRQ

7/C

S7

/IRQ

6

/IRQ

[7:1

]

/CS

4/IR

Q5

/CS

3/IR

Q3

/IRQ

1

/CS

2

/IRQ

4

/CS

0

/CS

[7:0

]

/CS

0/C

S1

/BS

[3:0

]

/BS

0/B

S1

/BS

2/B

S3

/RE

SE

T/B

DM

_RS

TIN

/EX

T_R

ST

IN

ET

H_C

LK

XT

AL

/IRQ

[7:1

]

JTA

G_E

N

/RS

TO

UT

D[3

1:0]

/RC

ON

CLK

MO

D[1

:0]

/RS

TO

UT

/CS

[7:0

]

R/W

/BS

[3:0

]

TD

I/DS

I/O

ET

DO

/DS

O

/IRQ

[7:1

]

/TA

TR

ST

/DS

CLK

TS

IZ0

TM

S/B

KP

T

TS

IZ1

CLK

OU

T

/TS

/TA

/CS

[7:0

]

R/W

/OE

/TE

A

/TIP

/TS

EX

TA

L

DT

OU

T2

DT

OU

T3

DT

OU

T1

DT

OU

T0

DT

IN2

DT

IN1

DT

IN0

DT

IN3

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V

+3.

3V+

3.3V

VS

SP

LL

VS

SP

LL

VS

SP

LL

+3.

3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Res

et C

onfig

urat

ion

& C

lock

sel

ectio

n1.

3

M52

71E

VB

C

1113

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Res

et C

onfig

urat

ion

& C

lock

sel

ectio

n1.

3

M52

71E

VB

C

1113

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Res

et C

onfig

urat

ion

& C

lock

sel

ectio

n1.

3

M52

71E

VB

C

1113

Wed

nesd

ay, A

pril

21, 2

004

AB

OR

T/-

INT

7

DE

BO

UN

CE

D /I

RQ

7S

IGN

AL

HA

RD

RE

SE

T &

VO

LTA

GE

SE

NS

E C

ON

TR

OLL

ER

Buf

fere

d an

d "O

R'd

" /R

ST

I sig

nal t

o th

e C

PU

from

the

BD

M p

ort,

expa

nsio

n co

nnec

tors

or

rese

t sw

itch.

NO

TE

: sig

nal t

rack

leng

ths

betw

een

thes

e cl

ock

circ

uits

and

the

MC

F52

71 s

houl

d be

min

imis

ed.

OS

CIL

LAT

OR

- d

ual l

ayou

t foo

tprin

tfo

r 8

AN

D 1

4 pi

n so

cket

ed D

IL o

sc.'s

D24

D21

D20

D19

D16

CLK

MO

D0

CLK

MO

D1

JTA

G_E

NR

CO

N

IMP

OR

TA

NT

NO

TE

: TH

E /R

ST

OU

T S

IGN

AL

MU

ST

BE

US

ED

TO

DR

IVE

TH

E O

UT

PU

T E

NA

BLE

PIN

S O

F U

19 T

O A

LLO

W T

HE

D16

, D17

, D18

, D19

, D21

, D24

, D25

&D

26 S

IGN

ALS

TO

BE

LA

TC

HE

D C

OR

RE

CT

LY B

Y T

HE

MC

F52

70/1

FO

R C

ON

FIG

UR

AT

ION

AT

RE

SE

T.

Clo

sed/

On

Ope

n/O

ff

D25

Enc

oded

Add

ress

/Chi

p S

elec

t Mod

eS

W4-

9

SW

4-10

Mod

e--

----

----

-

--

----

----

-

--

----

----

----

----

----

----

O

FF

OF

F

P

F[7

:5] =

/CS

[6:4

]

OF

F

O

N

PF

7 =

/CS

6, P

F[6

:5] =

A[2

2:21

]

ON

O

FF

PF

[7:6

] = /C

S[6

:5],

PF

[5] =

A21

O

N

ON

P

F[7

:5] =

A[2

3:21

]

NO

TE

: Ple

ase

plac

e th

ese

tabl

es o

n th

e si

lksc

reen

on

the

tops

ide

of th

e P

CB

clo

se to

SW

4.

Enc

oded

Boo

t Dev

ice

(Por

t Siz

e)S

W4-

6

SW

4-7

Mod

e--

----

----

-

--

----

----

-

--

----

----

----

----

----

----

O

FF

O

FF

Ext

erna

l (32

-bit)

O

FF

O

N

E

xter

nal (

16-b

it)

ON

O

FF

Ext

erna

l (8-

bit)

O

N

O

N

E

xter

nal (

32-b

it)

Enc

oded

Ope

ratin

g M

ode

SW

4-5

M

ode

----

----

---

----

----

---

O

FF

Res

erve

d

ON

M

aste

r

Enc

oded

Clo

ck M

ode

SW

4-3

S

W4-

4

M

ode

----

----

---

-

----

----

--

-

----

----

----

----

----

----

----

----

----

----

----

----

-

OF

F

O

FF

Ext

erna

l Clo

ck -

(N

o P

LL)

O

FF

ON

1:

1 P

LL

ON

O

FF

Nor

mal

PLL

ope

ratio

n (E

xt. C

lock

)

ON

O

N

Nor

mal

PLL

ope

ratio

n (E

xt. C

ryst

al)

----

----

----

----

----

----

OF

F -

SW

4 -

ON

-

----

----

----

----

----

---

Chi

p C

onfig

. Off

1

C

hip

Con

fig. O

nJT

AG

Inte

rfac

e E

nabl

ed

2

BD

M In

terf

ace

Ena

bled

Enc

oded

Clo

ck M

ode

3

Enc

oded

Clo

ck M

ode

Enc

oded

Clo

ck M

ode

4

Enc

oded

Clo

ck M

ode

Enc

oded

Ope

r. M

ode

5

Enc

oded

Ope

r. M

ode

Enc

oded

Boo

t Dev

ice

6

E

ncod

ed B

oot D

evic

eE

ncod

ed B

oot D

evic

e

7

Enc

oded

Boo

t Dev

ice

Par

tial B

us D

rive

8

Ful

l Bus

Driv

eE

ncod

ed A

ddre

ss M

ode

9

Enc

oded

Add

ress

Mod

eE

ncod

ed A

ddre

ss M

ode

10

E

ncod

ed A

ddre

ss M

ode

Not

e: d

efau

lt se

tting

for

SW

4 is

all

switc

hes

clos

ed/o

n.

Impo

rtan

t Not

e -

all u

ncon

nect

ed p

ull-u

p an

d pu

ll-do

wn

resi

stor

pac

k co

nnec

tions

, on

all s

chem

atic

s pa

ges,

nee

dto

be

conn

ecte

d to

an

unm

aske

d vi

a.

NO

TE

: Pla

ce T

P8,

TP

9, T

P10

& T

P11

at t

he c

orne

rs o

f the

PC

Bto

allo

w e

asy

conn

ectio

n of

'sco

pe p

robe

gro

und

lead

s.

NO

TE

: Ple

ase

plac

e D

17 th

roug

h D

24 to

geth

er in

a li

ne.

DT

IN0

LED

DT

IN1

LED

DT

IN2

LED

DT

IN3

LED

DT

OU

T0

LED

DT

OU

T1

LED

DT

OU

T2

LED

DT

OU

T3

LED

Cry

stal

Ena

ble

Def

ault

setti

ng fo

r JP

13 th

roug

h JP

20 is

fitte

d.

Ext

erna

l Clo

ck In

put (

SM

A c

onne

ctor

)

Pla

ce T

P5

as c

lose

toE

XT

AL

as p

ossi

ble

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

Def

ault

setti

ng fo

rJP

10 is

bet

wee

npi

ns 1

& 2

.

Def

ault

setti

ng fo

rJP

11 is

bet

wee

npi

ns 1

& 2

.

Def

ault

setti

ng fo

rJP

12 is

fitte

d.

OE

11

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

GN

D10

O7

11O

612

O5

13O

414

O3

15O

216

O1

17O

018

OE

219

VC

C20

U19

MC

74LC

X54

1DT

U19

MC

74LC

X54

1DT

11

22

33

44

55

66

77

88

RP

10

4x 4

.7K

RP

10

4x 4

.7K

1TP

10

GR

OU

ND

TP

10

GR

OU

ND

SW

3

KS

11R

23C

QD

RE

SE

T

SW

3

KS

11R

23C

QD

RE

SE

T

11

22

33

44

55

66

77

88

RP

11

4x 4

.7K

RP

11

4x 4

.7K

OE

1

GN

D7

CLK

8

VD

D14

OE

4V

DD

11

U15

25M

Hz

U15

25M

Hz

1TP9

GR

OU

ND

TP9

GR

OU

ND

R27

270

R27

270

12

JP15

JP15

11

22

33

44

55

66

77

88

RP

12

4x 4

.7K

RP

12

4x 4

.7K

1 122

3 344

5 566

7 788

RP

13

4x 1

0K

RP

13

4x 1

0K1

2

3

JP10

JP10

11

22

33

44

55

66

77

88

RP

20

4x 4

.7K

RP

20

4x 4

.7K

D24

D24

SW

2

KS

11R

22C

QD

SW

2

KS

11R

22C

QD

MR

1

VC

C2

GN

D3

PF

I4

PF

O5

N.C

.6

RE

SE

T7

RE

SE

T8

U17

AD

M70

8SA

R

U17

AD

M70

8SA

R

11

22

33

44

55

66

77

88

RP

16

4x 4

.7K

RP

16

4x 4

.7K

MR

1

VC

C2

GN

D3

PF

I4

PF

O5

N.C

.6

RE

SE

T7

RE

SE

T8

U16

AD

M70

8SA

R

U16

AD

M70

8SA

R

1TP8

GR

OU

ND

TP8

GR

OU

ND

11

22

33

44

55

66

77

88

RP

15

4x 4

.7K

RP

15

4x 4

.7K

11

22

33

44

55

66

77

88

RP

9

4x 4

.7K

RP

9

4x 4

.7K

1

2345

J7J7

SW

4

Con

figur

atio

n D

IP s

witc

h -

Gra

yhill

78R

B12

SW

4

Con

figur

atio

n D

IP s

witc

h -

Gra

yhill

78R

B12

11

22

33

44

55

66

77

88

RP

14

4x 4

.7K

RP

14

4x 4

.7K

D20

D20

D21

D21

12

JP19

JP19

D15

RE

D -

INT

7 L

ED

D15

RE

D -

INT

7 L

ED

R24

270

R24

270

12

JP13

JP13

A GN

DB

CV

CC Y

U18

SN

74LV

C1G

11

U18

SN

74LV

C1G

11

D17

D17

R26

100

R26

100

R29

1KR29

1K

R25

10K

R25

10K

1 122

3 344

5 566

7 788

RP

19

4x 1

0

RP

19

4x 1

0

Y1 25

MH

z

Y1 25

MH

z

C99

10pF

C99

10pF

12

JP14

JP14

12

JP17

JP17

1TP4

CH

IP S

ELE

CT

0

TP4

CH

IP S

ELE

CT

0

12

JP16

JP16

12

JP18

JP18

1TP6

TR

AN

SF

ER

AC

KN

OW

LED

GE

TP6

TR

AN

SF

ER

AC

KN

OW

LED

GE

C98

10pF

C98

10pF

12

JP20

JP20

D22

D22

1TP2

OU

TP

UT

EN

AB

LE

TP2

OU

TP

UT

EN

AB

LE

1TP

11

GR

OU

ND

TP

11

GR

OU

ND

D23

D23

1TP1

TR

AN

SF

ER

ST

AR

T

TP1

TR

AN

SF

ER

ST

AR

T

1

2

3

JP11

JP11

11

22

33

44

55

66

77

88

RP

21

4x 4

.7K

RP

21

4x 4

.7K

1TP3

RE

AD

NO

T W

RIT

E

TP3

RE

AD

NO

T W

RIT

E

D16

RE

D R

ES

ET

LE

DD

16R

ED

RE

SE

T

LED

R28

100

R28

100

12

JP12

JP12

11

22

33

44

55

66

77

88

RP

8

4x 4

.7K

RP

8

4x 4

.7K

11

22

33

44

55

66

77

88

RP

22

4x 4

.7K

RP

22

4x 4

.7K

1TP5

CP

U C

LOC

K I/

P

TP5

CP

U C

LOC

K I/

P

D18

D18

D19

D19

11

22

33

44

55

66

77

88

RP

17

4x 4

.7K

RP

17

4x 4

.7K

1TP7

CP

U C

LOC

K O

/P

TP7

CP

U C

LOC

K O

/P

1 122

3 344

5 566

7 788

RP

18

4x 1

0

RP

18

4x 1

0

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

A13

D5 A

23

D27

D2

D13

D20

D[3

1:0]

D[3

1:0]

A20

D4

A11

/BS

[3:0

]

A17

D23

A[2

3:0]

D24

D3 A

12A

11

A12

D6

D25

A21

A17

A9

/BS

3 /BS

1

D17

D28

D9

D11

D8

D19

A13

D21

D26

/BS

2

A14

D16

A22

/BS

0

A[2

3:0]

D7

A10

D0A

20

D15

A19

D10

D31

A19

D14

A22

A10

D30

D12

A[2

3:0]

A15

A23

D29

D18 D

1

A[2

3:0]

A18

D[3

1:0]

A9

A21

A14

A15

A18

D22

/BS

[3:0

]

/SD

_CS

0

/SD

_WE

SD

_SC

KE

D[3

1:0]

/SD

_RA

SC

LKO

UT

/SD

_CA

S

A[2

3:0]

A[2

3:0]

+3.

3V

+3.

3V

+3.

3V+

3.3V

+3.

3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SD

RA

M1.

3

M52

71E

VB

B

1213

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SD

RA

M1.

3

M52

71E

VB

B

1213

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

SD

RA

M1.

3

M52

71E

VB

B

1213

Wed

nesd

ay, A

pril

21, 2

004

SD

RA

M U

pper

16-

bit W

ord.

SD

RA

M L

ower

16-

bit W

ord.

NO

TE

: Mem

ory

size

: Eac

h S

DR

AM

mem

ory

is c

onfig

ured

4M

x 1

6bit

(8M

B).

Tot

al a

vaila

ble

SD

RA

M is

16M

B.

NO

TE

: Alte

rnat

ive

SD

RA

M's

with

the

sam

e P

CB

foot

prin

t are

:S

amsu

ng K

4S64

1632

EH

yund

ai H

Y57

V64

1620

HG

Tos

hiba

TC

59S

6416

CF

TIn

fineo

n H

YB

39S

6416

0ET

Win

bond

W98

6416

DH

NO

TE

: Ple

ase

plac

e th

e S

DR

AM

(U

20 &

U21

) as

clo

se to

the

MC

F52

71(U

8) a

spo

ssib

le to

min

imis

e tr

ack

leng

ths.

Par

ticul

arly

in r

elat

ion

to th

e S

DR

AM

cont

rol s

igna

ls &

clo

cks

whe

re, i

fpo

ssib

le, t

hese

trac

ks s

houl

d be

a s

imila

rle

ngth

i.e.

with

in +

/-5m

m.

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

C10

01n

FC

100

1nF

C10

11n

FC

101

1nF

C10

21n

FC

102

1nF

C10

31n

FC

103

1nF

VD

D1

DQ

02

VD

DQ

3

DQ

14

DQ

25

VS

SQ

6

DQ

37

DQ

48

VD

DQ

9

DQ

51

0

DQ

61

1

VS

SQ

12

DQ

71

3

VD

D1

4

DQ

ML

15

WE

#1

6

CA

S#

17

RA

S#

18

CS

#1

9

BA

02

0

BA

12

1

A1

02

2

A0

23

A1

24

A2

25

A3

26

VD

D2

7V

SS

28

A4

29

A5

30

A6

31

A7

32

A8

33

A9

34

A1

13

5N

C3

6C

KE

37

CL

K3

8D

QM

H3

9N

C4

0V

SS

41

DQ

84

2V

DD

Q4

3D

Q9

44

DQ

10

45

VS

SQ

46

DQ

11

47

DQ

12

48

VD

DQ

49

DQ

13

50

DQ

14

51

VS

SQ

52

DQ

15

53

VS

S5

4

U20

MT

48LC

4M16

A2T

G (

TS

OP

II 4

00 m

il)

U20

MT

48LC

4M16

A2T

G (

TS

OP

II 4

00 m

il)

VD

D1

DQ

02

VD

DQ

3

DQ

14

DQ

25

VS

SQ

6

DQ

37

DQ

48

VD

DQ

9

DQ

51

0

DQ

61

1

VS

SQ

12

DQ

71

3

VD

D1

4

DQ

ML

15

WE

#1

6

CA

S#

17

RA

S#

18

CS

#1

9

BA

02

0

BA

12

1

A1

02

2

A0

23

A1

24

A2

25

A3

26

VD

D2

7V

SS

28

A4

29

A5

30

A6

31

A7

32

A8

33

A9

34

A1

13

5N

C3

6C

KE

37

CL

K3

8D

QM

H3

9N

C4

0V

SS

41

DQ

84

2V

DD

Q4

3D

Q9

44

DQ

10

45

VS

SQ

46

DQ

11

47

DQ

12

48

VD

DQ

49

DQ

13

50

DQ

14

51

VS

SQ

52

DQ

15

53

VS

S5

4

U21

MT

48LC

4M16

A2T

G (

TS

OP

II 4

00 m

il)

U21

MT

48LC

4M16

A2T

G (

TS

OP

II 4

00 m

il)

C10

60.

1uF

C10

60.

1uF

C10

50.

1uF

C10

50.

1uF

C10

40.

1uF

C10

40.

1uF

C10

70.

1uF

C10

70.

1uF

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

/IRQ

[7:1

]/IR

Q1

QS

PI_

PC

S1

QS

PI_

PC

S0

U0R

XD

/U1R

TS

/U0C

TS

/U1C

TS

/U0R

TS

U2R

XD

U1R

XD

QS

PI_

DIN

QS

PI_

DO

UT

QS

PI_

SC

K

QS

PI_

PC

S0

I2C

_SC

L

I2C

_SD

A

QS

PI_

PC

S1

U0T

XD

U1T

XD

U2T

XD

/U2C

TS

/U2R

TS

/IRQ

[7:1

]

/RS

TO

UT

+3.

3V

+3.

3V+3.

3V

+3.

3V

+3.

3V

+5V

+3.

3V

+3.

3V

+3.

3V +3.

3V

+3.

3V+

3.3V

+3.

3V

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Ser

ial I

/O1.

3

M52

71E

VB

C

1313

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Ser

ial I

/O1.

3

M52

71E

VB

C

1313

Wed

nesd

ay, A

pril

21, 2

004

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Ser

ial I

/O1.

3

M52

71E

VB

C

1313

Wed

nesd

ay, A

pril

21, 2

004

TE

RM

INA

L P

OR

T9-

WA

Y D

-TY

PE

(Fem

ale)

RS

232

Tra

nsce

iver

.

Def

ault

setti

ng fo

r JP

25 to

JP

26 is

fitte

d.

RS

232

Tra

nsce

iver

.

AU

XIL

IAR

Y P

OR

T 1

9-W

AY

D-T

YP

E(F

emal

e)

RS

232

Tra

nsce

iver

.

AU

XIL

IAR

Y P

OR

T 2

9-W

AY

D-T

YP

E(F

emal

e)

NO

TE

: the

I2C

bus

on

the

MC

F52

71pr

oces

sor

is 3

.3V

tole

rant

onl

y. If

con

nect

ion

to a

5V

sys

tem

is r

equi

red

high

freq

uenc

yvo

ltage

leve

l shi

fters

will

be

requ

ired

betw

een

the

perip

hera

l and

pro

cess

or.

NO

TE

: Lab

el a

s "U

AR

T0"

and

"Ter

min

al"

NO

TE

: Lab

el a

s "U

AR

T1"

and

"Aux

iliar

y"

NO

TE

: Lab

el P

5fo

otpr

int a

s "U

AR

T2"

and

"Aux

iliar

y"

I2C

0.1

" pi

tch

thru

' boa

rd c

onne

ctor

QS

PI 0

.1"

pitc

h th

ru' b

oard

con

nect

or

NO

TE

: J8,

the

QS

PI c

onne

ctor

, has

add

ition

alsi

gnal

s (/

RS

TO

UT

& /I

RQ

1) c

onne

cted

to it

toaf

ford

a w

ider

ran

ge o

f fun

ctio

nalit

y in

any

QS

PI p

erip

hera

ls c

onne

cted

.

Def

ault

setti

ng fo

r JP

23 to

JP

24 is

fitte

d.

Def

ault

setti

ng fo

r JP

21 to

JP

22 is

fitte

d.

Mot

orol

a S

PS

TS

PG

- T

EC

D C

oldF

ire G

roup

C11

5

0.1u

F

C11

5

0.1u

F

C11

1

0.1u

F

C11

1

0.1u

F

5 9 4 8 3 7 2 6 1

P5

P5

C11

90.

1uF

C11

90.

1uF

C10

80.

1uF

C10

80.

1uF

12

JP25

JP25

C11

20.

1uF

C11

20.

1uF

1 2 3 4 5 6 7 8 9 10

J8J8

C12

4

1nF

C12

4

1nF

11

22

33

44

55

66

77

88

RP

23

4x 4

.7K

RP

23

4x 4

.7K

11

22

33

44

55

66

77

88

RP

244x

4.7

KR

P24

4x 4

.7K

C11

70.

1uF

C11

70.

1uF

C11

30.

1uF

C11

30.

1uF

5 9 4 8 3 7 2 6 1

P4

P4

11

22

33

44

55

66

77

88

RP

254x

4.7

KR

P25

4x 4

.7K

12

JP21

JP21

C10

90.

1uF

C10

90.

1uF

12

JP22

JP22

12

JP23

JP23

12

JP26

JP26

12

JP24

JP24

C12

0

1nF

C12

0

1nF

RE

AD

Y1

C1+

2

V+

3

C1-

4

C2+

5

C2-

6

V-

7

T2O

UT

8

R2I

N9

R2O

UT

10IN

VA

LID

11T

2IN

12T

1IN

13F

OR

CE

ON

14

GN

D18

R1O

UT

15R

1IN

16T

1OU

T17

VC

C19

FO

RC

EO

FF

20

U22

MA

X32

25C

AP

or

ICL3

225C

A

U22

MA

X32

25C

AP

or

ICL3

225C

A

11

22

33

44

55

66

77

88

RP

26

4x 4

.7K

RP

26

4x 4

.7K

RE

AD

Y1

C1+

2

V+

3

C1-

4

C2+

5

C2-

6

V-

7

T2O

UT

8

R2I

N9

R2O

UT

10IN

VA

LID

11T

2IN

12T

1IN

13F

OR

CE

ON

14

GN

D18

R1O

UT

15R

1IN

16T

1OU

T17

VC

C19

FO

RC

EO

FF

20

U23

MA

X32

25C

AP

or

ICL3

225C

A

U23

MA

X32

25C

AP

or

ICL3

225C

A

C11

80.

1uF

C11

80.

1uF

C11

40.

1uF

C11

40.

1uF

C12

2

1nF

C12

2

1nF

C11

00.

1uF

C11

00.

1uF

5 9 4 8 3 7 2 6 1

P3

P3

C12

5

0.1u

F

C12

5

0.1u

F

C12

3

0.1u

F

C12

3

0.1u

F

C11

60.

1uF

C11

60.

1uF

C12

1

0.1u

F

C12

1

0.1u

F

RE

AD

Y1

C1+

2

V+

3

C1-

4

C2+

5

C2-

6

V-

7

T2O

UT

8

R2I

N9

R2O

UT

10IN

VA

LID

11T

2IN

12T

1IN

13F

OR

CE

ON

14

GN

D18

R1O

UT

15R

1IN

16T

1OU

T17

VC

C19

FO

RC

EO

FF

20

U24

MA

X32

25C

AP

or

ICL3

225C

A

U24

MA

X32

25C

AP

or

ICL3

225C

A

1 2 3 4J9J9


Freescale Semiconductor C-1

Appendix C M5271EVB BOM

C.1 M5271EVB BOMTable C-1. M5271EVB BOM (Sheet 1 of 3)

Item Qty Reference Part Function

1 33 C1,C2,C3,C4,C13,C14,C15,C16,C17,C18,C26,C27,C34, C39,C40,C41,C43,C46,C48,C65,C66,C77,C78,C79,C80,C85,C91,C100,C101,C102,C103,C120,C122,C124

1nF SMT Decoupling Capacitors

2 59 C12,C21,C22,C23,C24,C30,C31,C32,C33,C42,C44,C45,C47,C49,C51,C52,C53,C55,C56,C57,C58,C67,C68,C81,C82,C83,C84,C86,C87,C89,C90,C94,C97,C104,C105,C106,C107,C108,C109,C110,C111,C112,C113,C114,C115,C116,C117,C118,C119,C121,C123,C125

0.1uF SMT Decoupling Capacitors

3 8 C19,C20,C28,C29,C35,C36,C37,C38

100pF SMT Capacitors

4 2 C25,C95 10uF TANT SMT Capacitors

5 2 C50,C54 47uF TANT SMT Capacitors

6 7 C59,C61,C62,C69,C70,C71,,C72 10nF SMT Capacitors

7 1 C60 10uF AVX SMT Capacitors

8 6 C63,C64,C73,C74,C75,C76 470pF SMT Capacitors

9 3 C88,C93,C96 33uF SMT Capacitors

10 1 C92 1000uF 35V SMT Capacitors

11 2 C98,C99 10pF SMT Capacitors

12 8 C92,C93,C94,C95,C96,C97,C98,C99

0.22uF SMT Capacitors

13 7 D1,D2,D3,D4,D6,D9,D13 AA3528SGC Kingbright Green LED

SMT LEDs

14 5 D5,D7,D8,D12,D14 MBRS340T3 On Semi SMC Schottky Rectifier

15 2 D10,D11 MRA4003T3 On Semi SMA Power Rectifier

M5271EVB BOM


C-2 Freescale Semiconductor

16 2 D15,D16 AA3528SRC Kingbright Red LED

SMT LEDs

17 8 D17,D18,D19,D20,D21,D22,D23,D24

AA3528MBC Kingbright Blue LED

SMT LEDs

18 4 FB1,FB2,FB3,FB4 HI1206T500R-00 Ferrite

19 1 F1 Fuse Holder by Keystone 0216005.H ; Fuse by Littlefuse, 5a, 250V, 5x 20mm, glass

5A Fast blow fuse and holder

20 7 JP1,JP2,JP5,JP6,JP7,JP10,JP11 Harwin M22-2010305 3-way jumper

21 19 JP3,JP4,JP8,JP9,JP12,JP13,JP14,JP15,JP16,JP17,JP18,JP19,JP20,JP21,JP22,JP23,JP24,JP25,JP26

Harwin M22-2010205 2-way jumper

22 1 J1 Thomas&Betts 609-2627 BDM 26-way header

23 1 J2 Halo HFJ11-2450E RJ45 Connector w/mag

24 4 J3,J4,J5,J6 AMP 177983-2 60 SMT Recpetacle

25 1 J7 AMP 1053378-1 RF/SMB/V External Clock conn

26 1 J8 Molex 22-10-2101 Conn, 1x10 .1 male header

27 1 J9 Molex 22-10-2041 Conn, 1x4 .1 male header

28 1 L1 1210-103J API Delevan External 10uH inductor

29 2 L2,L3 SIEMENS B82111-B-C24 25uH Inductors

30 1 P1 Switchcraft RAPC722 power jack 2.1mm

31 4 P2 Augat 25V-02 2-way bare wire power connector

32 3 P3,P4,P5 AMP 747844-3 DB9 Female

33 1 P2 Switchcraft RAPC722 PSU barrel connector

34 18 RP1,RP2,RP8,RP9,RP10,RP11,RP12,RP14,RP15,RP16,RP17,RP20,RP21,RP22,RP23,RP24,RP25,RP26

Philips 4x4.7 SMT 0603

35 1 RP3 Philips 4x22 SMT 0603

36 1 RP4,RP5,RP6,RP7 Philips 4x51 SMT 0603

37 1 RP13 Philips 4x10K SMT 0603

38 2 RP18,RP19 Philips 4x10 SMT 0603

39 3 R1,R2,R23 Philips SM/R 0805 22 ohm resistor

40 3 R3,R10,R25 Philips SM/R 0805 10K ohm resistor

41 4 R4,R5,R6,R7 Philips SM/R 0805 49.9 1% ohm resistor

42 5 R8,R15,R16,R17,R18 Philips SM/R 0805 4.7K ohm resistor

Table C-1. M5271EVB BOM (Sheet 2 of 3)


M5271EVB BOM


Freescale Semiconductor C-3

43 1 R9 Philips SM/R 0805 6.49K 1% ohm resistor

44 4 R11,R12,R13,R14 Philips SM/R 0805 220 ohm resistor

45 3 R19,R24,R27 Philips SM/R 0805 270 ohm resistor

46 1 R20 Philips SM/R 0805 560 ohm resistor

47 1 R21 Philips SM/R 0805 0 ohm resistor

48 1 R22 Philips SM/R 0805 120ohm resistor

49 2 R26,R28 Philips SM/R 0805 100 ohm resistor

50 1 R29 Philips SM/R 0805 1K ohm resistor

51 1 SW1 EAO Switch POWER SW SLIDE-SPST(Board Edge)

52 1 SW2 C&K KS11R22CQD IRQ7 black push-button switch

53 1 SW3 C&K KS11R23CQD Hard reset push-button switch

54 1 SW4 Grayhill 78RB12 Configuration DIP switch

55 11 TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9,TP10,TP11

Keystone 5015 Test points

56 2 U1,U2 CY7C1041CV3310ZC ASRAM (Not populated)

57 3 U3,U4,U6 MC74LCX16245DT Bus transceiver

58 2 U5,U18 SN74LVC1G11 3-input positive AND gate

59 1 U7 MC74LCX245DT Bus transceiver

60 1 U8 MCF5271CVM100 Freescale MCF5271 microprocessor

61 1 U9 KS8721BL MCF5282 ColdFire

62 1 U10 Am29LV160CB AMD 2MB Flash

63 1 U11 Am29PL320DB AMD 4MB Flash (not populated)

64 1 U12 LM2596S-3.3 National Semi DCtoDC switcher

65 1 U13 LM2596S-5 National Semi DCtoDC switcher

66 1 U14 LT1086CM Regulator

67 2 U16,U17 ADM708SAR Voltage sensor

68 2 Y1 FOXS/250F-20 25MHz Crystal

69 1 U15 P1145-HCV 25MHz Oscillator

70 1 U19 MC74LCX541DT Octal Buffer

71 2 U20,U21 MT48LC4M16A2TG (TSOP II 400 mil)

SDRAM

72 3 U22,U23,U24 MAX3225CAP RS232 Transceivers

Table C-1. M5271EVB BOM (Sheet 3 of 3)


M5271EVB BOM


C-4 Freescale Semiconductor

Document Number: M5271EVBUMRev. 1.105/2006

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E-mail:[email protected]

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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

© Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative.

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