ltm2883 - spi/digital or i2c µmodule isolator with adjustable ±12.5

LTM2883

12883fc

For more information www.linear.com/LTM2883

Typical applicaTion

FeaTures DescripTion

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V

and 5V Regulated Power

The LTM®2883 is a complete galvanic 6-channel digital µModule® (micromodule) isolator. No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply.

Available options are compliant with SPI and I2C (master mode only) specifications.

The isolated side includes ±12.5V and 5V nominal power supplies, each capable of providing more than 20mA of load current. Each supply may be adjusted from its nominal value using a single external resistor.

Coupled inductors and an isolation power transformer provide 2500VRMS of isolation between the input and out-put logic interface. This device is ideal for systems where the ground loop is broken, allowing for a large common mode voltage range. Communication is uninterrupted for common mode transients greater than 30kV/μs.L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks and Easy Drive, Hot Swap, SoftSpan and TimerBlox are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Isolated 4MHz SPI Interface

applicaTions

n 2500VRMS for One Minute per UL1577 UL Recognized ® File #E151738

n Isolated Adjustable DC Power: 3V to 5V at Up to 30mA ±12.5V at Up to 20mA

n No External Components Requiredn SPI (LTM2883-S) or I2C (LTM2883-I) Optionsn High Common Mode Transient Immunity: 30kV/μsn High Speed Operation:

10MHz Digital Isolation 4MHz/8MHz SPI Isolation 400kHz I2C Isolation

n 3.3V (LTM2883-3) or 5V (LTM2883-5) Operationn 1.62V to 5.5V Logic Supplyn ±10kV ESD HBM Across the Isolation Barriern Maximum Continuous Working Voltage: 560VPEAKn Low Current Shutdown Mode (<10µA)n Low Profile (15mm × 11.25mm × 3.42mm)

BGA Package

n Isolated SPI or I2C Interfacesn Industrial Systemsn Test and Measurement Equipmentn Breaking Ground Loops

LTM2883 Operating Through 35kV/µs CM Transient

2883 TA01a

ON

CS CS2

LTM2883-5S

VL

VCC5V

GND GND2

SDI

SDOE

SDI2

DO2

SCK SCK2

CS

SDI

SCK

CS

SDI

SCK

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2SDO SDO

I2

DO1 I1

ISOL

ATIO

N BA

RRIE

R

5V AT 20mA

12.5V AT 20mA

–12.5V AT 15mA

20ns/DIV

2V/DIV2V/DIV

SCKSD0SCK2 = SD02

200V/DIV2883 TA01b

REPETITIVECOMMON MODETRANSIENTS

http://www.linear.com/LTM2883


LTM2883

22883fc


absoluTe MaxiMuM raTings

VCC to GND .................................................. –0.3V to 6VVL to GND .................................................... –0.3V to 6VVCC2, AVCC2, AV+ to GND2 ........................... –0.3V to 6VV+ to GND2 ................................................ –0.3V to 16VV–, AV– to GND2 .........................................0.3V to –16VLogic Inputs

DI1, SCK, SDI, CS, SCL, SDA, SDOE, ON to GND ..................................–0.3V to (VL + 0.3V) I1, I2, SDA2, SDO2 to GND2 ........................–0.3V to (VCC2 + 0.3V)

(Note 1)

Logic Outputs DO1, DO2, SDO to GND ..............–0.3V to (VL + 0.3V) O1, SCK2, SDI2, CS2, SCL2 to GND2 ........................–0.3V to (VCC2 + 0.3V)

Operating Temperature Range (Note 4) LTM2883C .........................................0°C ≤ TA ≤ 70°C LTM2883I ..................................... –40°C ≤ TA ≤ 85°C

Maximum Internal Operating Temperature ............ 105°CStorage Temperature Range .................. –40°C to 105°CPeak Body Reflow Temperature ............................ 245°C

LTM2883-I LTM2883-S

VCCGNDDO1

AV+AV–GND2I1

BGA PACKAGE32-PIN (15mm × 11.25mm × 3.42mm)

TOP VIEW

AVCC2

F

G

H

L

J

K

E

A

B

C

D

21 43 5 6 7 8

DNCDO2 SDASCL DI1 GND ON VL

DNCI2 SDA2SCL2 O1 VCC2 V– V+

TJMAX = 105°C, θJA = 30°C/W, θJC(BOTTOM) = 15.7°C/W,

θJC(TOP) = 25°C/W, θJBOARD = 14.5°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

VCCGNDDO1

AV+AV–GND2I1

BGA PACKAGE32-PIN (15mm × 11.25mm × 3.42mm)

TOP VIEW

AVCC2

F

G

H

L

J

K

E

A

B

C

D

21 43 5 6 7 8

DO2SDO SDISCK CS SDOE ON VL

I2SDO2 SDI2SCK2 CS2 VCC2 V– V+

TJMAX = 105°C, θJA = 30°C/W, θJC(BOTTOM) = 15.7°C/W,

θJC(TOP) = 25°C/W, θJBOARD = 14.5°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

pin conFiguraTion


LTM2883

32883fc


orDer inForMaTion

elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Supplies

VCC Input Supply Range LTM2883-3 LTM2883-5

l

l

3 4.5

3.3 5

3.6 5.5

V V

VL Logic Supply Range LTM2883-S LTM2883-I

l

l

1.62 3

5

5.5 5.5

V V

ICC Input Supply Current ON = 0V LTM2883-3, ON = VL, No Load LTM2883-5, ON = VL, No Load

l

l

l

0 25 19

10 35 28

µA mA mA

IL Logic Supply Current ON = 0V LTM2883-S, ON = VL LTM2883-I, ON = VL

l 0 10

10

150

µA µA µA

PART NUMBER INPUT VOLTAGE

PAD OR BALL FINISH

PART MARKING PACKAGE TYPE

MSL RATING

TEMPERATURE RANGEDEVICE FINISH CODE

LTM2883CY-3S#PBF

3V TO 3.6V

SAC305(RoHS)

LTM2883Y-3S

e1 BGA 4

0°C TO 70°C

LTM2883IY-3S#PBF –40°C TO 85°C

LTM2883HY-3S#PBF (OBSOLETE) –40°C TO 105°C

LTM2883CY-5S#PBF

4.5V TO 5.5V LTM2883Y-5S

0°C TO 70°C

LTM2883IY-5S#PBF –40°C TO 85°C

LTM2883HY-5S#PBF (OBSOLETE) –40°C TO 105°C

LTM2883CY-3I#PBF

3V TO 3.6V LTM2883Y-3I

0°C TO 70°C

LTM2883IY-3I#PBF –40°C TO 85°C

LTM2883HY-3I#PBF (OBSOLETE) –40°C TO 105°C

LTM2883CY-5I#PBF

4.5V TO 5.5V LTM2883Y-5I

0°C TO 70°C

LTM2883IY-5I#PBF –40°C TO 85°C

LTM2883HY-5I#PBF (OBSOLETE) –40°C TO 105°C

•Device temperature grade is indicated by a label on the shipping container.

•Pad or ball finish code is per IPC/JEDEC J-STD-609.•Terminal Finish Part Marking: www.linear.com/leadfree•This product is not recommended for second side reflow. For more

information, go to: www.linear.com/BGA-assy

•Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy

•BGA Package and Tray Drawings: www.linear.com/packaging•This product is moisture sensitive. For more information, go to:

www.linear.com/BGA-assy


http://www.linear.com/leadfree

http://www.linear.com/BGA-assy


http://www.linear.com/packaging


LTM2883

42883fc


elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Supplies

VCC2 Regulated Output Voltage No Load l 4.75 5 5.25 V

Output Voltage Operating Range (Note 2) 3 5.5 V

Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 25 100 mV

Load Regulation ILOAD = 100µA to 20mA l 8 80 mV

ADJ Pin Voltage ILOAD = 100µA to 20mA l 585 600 615 mV

Voltage Ripple ILOAD = 20mA (Note 2) 1 mVRMS

Efficiency ILOAD = 20mA (Note 2) 45 %

ICC2 Output Short Circuit Current VCC2 = 0V 45 mA

Current Limit ΔVCC2 = –5% l 20 mA

V+ Regulated Output Voltage No Load l 12 12.5 13 V

Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 5 30 mV

Load Regulation ILOAD = 100µA to 20mA l 200 mV

ADJ Pin Voltage ILOAD = 100µA to 20mA l 1.170 1.220 1.260 mV

Voltage Ripple ILOAD = 20mA (Note 2) 3 mVRMS


I+ Output Short Circuit Current V+ = 0V 70 mA

Current Limit ΔV+ = –0.5V l 20 mA

V– Regulated Output Voltage No Load l –12 –12.5 –13 V

Line Regulation ILOAD = –1mA, MIN ≤ VCC ≤ MAX l 4 15 mV

Load Regulation ILOAD = 100µA to 15mA, V+LOAD = 1.5mA 35 mV

ADJ Pin Voltage ILOAD = 100µA to 15mA, V+LOAD = 1.5mA l –1.184 –1.220 –1.256 mV

Voltage Ripple ILOAD = 15mA, V+LOAD = 1.5mA (Note 2) 2 mVRMS


I– Output Short-Circuit Current V– = 0V 30 mA

Current Limit ΔV– = 0.5V, V+ = 1.5mA l 10 15 mA

Logic/SPI

VITH Input Threshold Voltage ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ VL < 2.35V ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ VL I1, I2, SDO2

l

l

l

0.25•VL 0.33•VL 0.33•VCC2

0.75•VL 0.67•VL 0.67•VCC2

V V V

IINL Input Current l ±1 µA

VHYS Input Hysteresis (Note 2) 150 mV

VOH Output High Voltage DO1, DO2, SDO ILOAD = –1mA, 1.62V ≤ VL < 3V ILOAD = –4mA, 3V ≤ VL ≤ 5.5V

l VL – 0.4 V

O1, SCK2, SDI2, CS2, ILOAD = –4mA l VCC2 – 0.4 V

VOL Output Low Voltage DO1, DO2, SDO ILOAD = 1mA, 1.62V ≤ VL < 3V ILOAD = 4mA, 3V ≤ VL ≤ 5.5V

l 0.4 V

O1, SCK2, SDI2, CS2, ILOAD = 4mA l 0.4 V

ISC Short-Circuit Current 0V ≤ (DO1, DO2, SDO) ≤ VL 0V ≤ (O1, SCK2, SDI2, CS2) ≤ VCC2

l ±60

±85 mA mA


LTM2883

52883fc


elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I2CVIL Low Level Input Voltage SCL, SDA

SDA2l

l

0.3•VL 0.3•VCC2

V V

VIH High Level Input Voltage SCL, SDA SDA2

l

l

0.7•VL 0.7•VCC2

V V

IINL Input Current SCL, SDA = VL or 0V l ±1 µA

VHYS Input Hysteresis SCL, SDA SDA2

0.05•VL 0.05•VCC2

mV mV

VOH Output High Voltage SCL2, ILOAD = –2mA DO2, ILOAD = –2mA

l

l

VCC2 – 0.4 VL – 0.4

V V

VOL Output Low Voltage SDA, VL = 3V, ILOAD = 3mA DO2, VL = 3V, ILOAD = 2mA SCL2, ILOAD = 2mA SDA2, No Load, SDA = 0V, 4.5V ≤ VCC2 < 5.5V SDA2, No Load, SDA = 0V, 3V < VCC2 < 4.5V

l

l

l

l

l

0.3

0.4 0.4 0.4

0.45 0.55

V V V V V

CIN Input Pin Capacitance SCL, SDA, SDA2 (Note 2) l 10 pF

CB Bus Capacitive Load SCL2, Standard Speed (Note 2) SCL2, Fast Speed SDA, SDA2, SR ≥ 1V/μs, Standard Speed (Note 2) SDA, SDA2, SR ≥ 1V/μs, Fast Speed

l

l

l

l

400 200 400 200

pF pF pF pF

Minimum Bus Slew Rate SDA, SDA2 l 1 V/µs

ISC Short-Circuit Current SDA2 = 0, SDA = VL 0V ≤ SCL2 ≤ VCC2 0V ≤ DO2 ≤ VL SDA = 0, SDA2 = VCC2 SDA = VL, SDA2 = 0

l ±30 ±30 6

–1.8

100 mA mA mA mA mA

ESD (HBM) (Note 2)

Isolation Boundary (VCC2, V+, V–, GND2) to (VCC, VL, GND) ±10 kV

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

swiTching characTerisTics


Logic

Maximum Data Rate Ix → DOx, CL = 15pF (Note 3) l 10 MHz

tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns

tR Rise Time CL = 15pF (Figure 1) LTM2883-I, DO2, CL = 15pF (Figure 1)

l

l

3 20

12.5 35

ns ns

tF Fall Time CL = 15pF (Figure 1) LTM2883-I, DO2, CL = 15pF (Figure 1)

l

l

3 20

12.5 35

ns ns

SPI

Maximum Data Rate Bidirectional Communication (Note 3) Unidirectional Communication (Note 3)

l

l

4 8

MHz MHz

tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns

tPWU Output Pulse Width Uncertainty SDI2, CS2 (Note 2) –20 50 ns



LTM2883

62883fc


SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVISO Rated Dielectric Insulation Voltage

(Notes 5, 6, 7)1 Minute, Derived from 1 Second Test 2500 VRMS

1 Second ±4400 V

Common Mode Transient Immunity LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = ON = 3.3V, VCM = 1kV, Δt = 33ns (Note 2)

30 kV/µs

VIORM Maximum Continuous Working Voltage (Notes 2, 5) 560 400

VPEAK VRMS

Partial Discharge VPD = 1050VPEAK (Notes 2, 5) 5 pC

CTI Comparative Tracking Index IEC 60112 (Note 2) 600 VRMS

Depth of Erosion IEC 60112 (Note 2) 0.017 mm

DTI Distance Through Insulation (Note 2) 0.06 mm

Input to Output Resistance (Notes 2, 5) 109 Ω

Input to Output Capacitance (Notes 2, 5) 6 pF

Creepage Distance (Note 2) 9.48 mm

isolaTion characTerisTics TA = 25°C.

swiTching characTerisTics


tR Rise Time CL = 15pF (Figure 1) l 3 12.5 ns

tF Fall Time CL = 15pF (Figure 1) l 3 12.5 ns

tPZH, tPZL Output Enable Time SDOE = ↓, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns

tPHZ, tPLZ Output Disable Time SDOE = ↑, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns

I2C

Maximum Data Rate (Note 3) l 400 kHz

tPHL, tPLH Propagation Delay SCL → SCL2, CL = 15pF (Figure 1) SDA → SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 → SDA, RL = 1.1kΩ, CL = 15pF (Figure 3)

l

l

l

150 150 200

225 250 350

ns ns ns

tPWU Output Pulse Width Uncertainty SDA, SDA2 (Note 2) –20 50 ns

tHD;DAT Data Hold Time (Note 2) 600 ns

tR Rise Time SDA2, CL = 200pF (Figure 3) SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1)

l

l

l

40 40 40

250 300 250 250

ns ns ns ns

tF Fall Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1)

l

l

l

40 40

250 250 250

ns ns ns

tSP Pulse Width of Spikes Suppressed by Input Filter

l 0 50 ns

Power Supply

Power-Up Time ON = ↑ to VCC2 (Min) ON = ↑ to V+ (Min) ON = ↑ to V– (Min)

l

l

l

0.6 0.6 0.6

2 2

2.5

ms ms ms



LTM2883

72883fc


Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: Guaranteed by design and not subject to production test.Note 3: Maximum data rate is guaranteed by other measured parameters and is not tested directly.Note 4: This module includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 105°C when overtemperature protection is active.

Continuous operation above specified maximum operating junction temperature may result in device degradation or failure.Note 5: Device considered a 2-terminal device. Pin group A1 through B8 shorted together and pin group K1 through L8 shorted together.Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating.Note 7: In accordance with UL1577, each device is proof tested for the 2500VRMS rating by applying the equivalent positive and negative peak voltage multiplied by an acceleration factor of 1.2 for one second.

isolaTion characTerisTics


LTM2883

82883fc


Typical perForMance characTerisTics

VCC2 Line Regulation vs Load Current

V+ Line Regulation vs Load Current

V– Line Regulation vs Load Current

VCC2 Line Regulation vs Load Current

V+ Line Regulation vs Load Current

V– Line Regulation vs Load Current

VCC Supply Current vs Temperature

Isolated Supplies vs Equal Load Current

Isolated Supplies vs Equal Load Current

TA = 25°C, LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

TEMPERATURE (°C)–50

SUPP

LY C

URRE

NT (m

A)

30

25

15

20

10500 100

2883 G01

12525–25 75

NO LOAD, REFRESH DATA ONLY

LTM2883-3VCC = 3.3V

LTM2883-5VCC = 5V

LOAD CURRENT (mA)0

V CC2

, V+ , |

V– | VOL

TAGE

(V)

14

4

2

6

8

10

12

02010 155

2883 G02

25

LTM2883-3VCC = 3.3V

VCC2V+

V–

LOAD CURRENT (mA)0

V CC2

, V+ , |

V– | VOL

TAGE

(V)

14

4

2

6

8

10

12

02010 155

2883 G03

3025

LTM2883-5VCC = 5V

VCC2V+

V–

LOAD CURRENT (mA)0

V CC2

VOL

TAGE

(V)

6.0

3.0

3.5

4.0

4.5

5.0

5.5

2.52010 30

2883 G04

40

LTM2883-3I+ = I– = 0A

VCC = 3VVCC = 3.3VVCC = 3.6V

LOAD CURRENT (mA)0

V+ VOL

TAGE

(V)

13.0

10.0

10.5

11.0

11.5

12.0

12.5

9.0

9.5

2010 30

2883 G05

605040

VCC = 3VVCC = 3.15VVCC = 3.3VVCC = 3.6V

LTM2883-3ICC2 = I– = 0A

–9.0

–10.0

–10.5

–11.0

–11.5

–12.0

–12.5

–13.0

–9.5

LOAD CURRENT (mA)0

V– VOL

TAGE

(V)

2010

2883 G06

30

VCC = 3VVCC = 3.15VVCC = 3.3VVCC = 3.6V

LTM2883-3ICC2 = I+ = 0A

LOAD CURRENT (mA)0

V CC2

VOL

TAGE

(V)

6.0

3.0

3.5

4.0

4.5

5.0

5.5

2.52010 30

2883 G07

40

VCC = 4.5VVCC = 5VVCC = 5.5V

LTM2883-5I+ = I– = 0A

LOAD CURRENT (mA)0

V+ VOL

TAGE

(V)

13.0

10.0

10.5

11.0

11.5

12.0

12.5

9.0

9.5

2010 30

2883 G08

605040

VCC = 4.5VVCC = 4.75VVCC = 5VVCC = 5.5V

LTM2883-5ICC2 = I– = 0A

–9.0

–10.0

–10.5

–11.0

–11.5

–12.0

–12.5

–13.0

–9.5

LOAD CURRENT (mA)0

V– VOL

TAGE

(V)

2010 30

2883 G09

40

VCC = 4.5VVCC = 4.75VVCC = 5VVCC = 5.5V

LTM2883-5ICC2 = I+ = 0A


LTM2883

92883fc



V+ Load Regulation vs Temperature

V– Load Regulation vs Temperature

V– Load Regulation vs Temperature

VCC2 EfficiencyVCC2 Voltage and ICC Current vs Load Current

VCC2 Load Regulation vs Temperature

VCC2 Load Regulation vs Temperature

V+ Load Regulation vs Temperature



V CC2

VOL

TAGE

(V)

5.20

5.05

5.15

5.10

5.00

4.90

4.95

500 100

2883 G10

12525–25 75

LTM2883-3VCC = 3.3VI+ = I– = 0A

ICC2 = 1mAICC2 = 20mA


V CC2

VOL

TAGE

(V)

5.20

5.05

5.15

5.10

5.00

4.90

4.95

500 100

2883 G11

12525–25 75

LTM2883-5VCC = 5VI+ = I– = 0A

ICC2 = 1mAICC2 = 20mA


V+ VOL

TAGE

(V)

12.8

12.5

12.7

12.6

12.4

12.2

12.3

500 100

2883 G12

12525–25 75

LTM2883-3VCC = 3.3VICC2 = I– = 0A

I+ = 1mAI+ = 5mAI+ = 10mAI+ = 15mAI+ = 20mA


V+ VOL

TAGE

(V)

12.7

12.5

12.6

12.4

12.1

12.2

12.3

500 100

2883 G13

12525–25 75

I+ = 1mAI+ = 5mAI+ = 10mAI+ = 15mAI+ = 20mA

LTM2883-5VCC = 5VICC2 = I– = 0A


V– VOL

TAGE

(V)

–12.2

–12.5

–12.3

–12.4

–12.6

–12.8

–12.7

500 100

2883 G14

12525–25 75

I– = 1mAI– = 15mA

LTM2883-3VCC = 3.3VICC2 = I+ = 0A


V– VOL

TAGE

(V)

–12.2

–12.5

–12.3

–12.4

–12.6500 100

2883 G15

12525–25 75

I– = 1mAI– = 20mA

LTM2883-5VCC = 5VICC2 = I+ = 0A

LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

60

10

20

30

40

50

0

0.6

0.4

0.2

0.3

0.1

0.5

02010 30

2883 G16

40

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

EFFICIENCY

POWER LOSS

I+ = I– = 0A

LOAD CURRENT (mA)0

V CC2

VOL

TAGE

(V) ICC CURRENT (m

A)

6

1

2

3

4

5

0

150

100

50

75

25

125

02010 30

2883 G17

40

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

VOLTAGE

ICC CURRENT

I+ = I– = 0A


LTM2883

102883fc



V– EfficiencyV– Voltage and ICC Current vs Load Current

VCC2 Transient Response 20mA Load Step

V+ Transient Response 20mA Load Step

V– Transient Response 20mA Load Step

V+ EfficiencyV+ Voltage and ICC Current vs Load Current


LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

60

10

20

30

40

50

0

1.2

0.8

0.4

0.6

0.2

1.0

02010 30

2883 G18

5040

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

EFFICIENCY

POWER LOSS

ICC2 = I– = 0A

0 2010 30 5040LOAD CURRENT (mA)

V+ VOL

TAGE

(V)

ICC CURRENT (mA)

14

12

6

8

10

2

4

0

350

250

150

50

200

100

300

0

2883 G19

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

ICC2 = I– = 0AVOLTAGE

ICC CURRENT

LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

60

10

20

30

40

50

0

0.6

0.4

0.2

0.3

0.1

0.5

02010

2883 G20

30

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

EFFICIENCY

POWER LOSS

LOAD CURRENT (mA)0

V– VOL

TAGE

(V)

ICC CURRENT (mA)

–9.0

–12.5

–12.0

–11.5

–11.0

–10.0

–9.5

–10.5

–13.0

320

200

120

80

160

40

240

280

02010

2883 G21

30

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

VOLTAGE

ICC CURRENT

100µs/DIV

VCC2100mV/DIV

ICC210mA/DIV

2883 G22 100µs/DIV

V+

200mV/DIV

I+

10mA/DIV

2883 G23 100µs/DIV

V–

200mV/DIV

I–

10mA/DIV

2883 G24

I+ = 1.5mA


LTM2883

112883fc



VCC Supply Current vs Single Channel Data Rate

Logic Input Threshold vs VL Supply Voltage

Logic Output Voltage vs Load Current

VCC2 Ripple V+ Ripple V– Ripple


VCC2 Noise V+ Noise V– Noise

1ms/DIV

2mV/DIV

2883 G30

500ns/DIV

2mV/DIV

2883 G25 500ns/DIV

5mV/DIV

I+ = 1mA

I+ = 20mA

2883 G26 500ns/DIV

5mV/DIV

I– = 1mA

I– = 20mA

2883 G27

1ms/DIV

2mV/DIV

2883 G28 1ms/DIV

2mV/DIV

2883 G29

DATA RATE (Hz)1k

V CC

CURR

ENT

(mA)

70

60

20

30

40

50

10100k10k 1M

2883 G31

100M10M

VCC = 5VICC2 = I+ = I– = 0

CL = 1nFCL = 330pFCL = 100pFCL = 20pF

VL SUPPLY VOLTAGE (V)1

THRE

SHOL

D VO

LTAG

E (V

)

3.5

2.5

0.5

1.0

2.0

3.0

1.5

04 52

2883 G32

63

INPUT RISING

INPUT FALLING

LOAD CURRENT (mA)0

OUTP

UT V

OLTA

GE (V

)

6.0

1.0

2.0

3.0

4.0

5.0

021 3

2883 G33

10987654

VL = 5.5VVL = 3.3VVL = 1.62V


LTM2883

122883fc



VCC2 Cross Regulation vs V+, V– Load

Isolated Supply Efficiency with Equal Load Current

Power On SequenceVCC2 Cross Regulation vs V+, V– Load


200µs/DIV

5V/DIV

V–

ON

V+

VCC2

2883 G34

LOAD CURRENT (mA)0

V CC2

VOL

TAGE

(V)

V+, |V

–| VOLTAGE (V)

5.2

4.9

5.0

5.1

4.8

14

7

8

9

10

12

11

13

62010 30

2883 G35

40

LTM2883-3VCC = 3.3VICC2 = 15mA

VCC2V+

V–

0 2010 30 40LOAD CURRENT (mA)

V CC2

VOL

TAGE

(V)

V+, |V

–| VOLTAGE (V)

5.2

4.9

5.0

5.1

4.8

14

7

8

9

10

12

11

13

6

2883 G36

LTM2883-5VCC = 5VICC2 = 15mA

VCC2V+

V–

V+ Cross Regulation vs V– Load V+ Cross Regulation vs V– Load

LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

60

10

20

30

40

50

0

1.0

0.8

0.4

0.6

0.2

0.7

0.3

0.5

0.1

0.9

02010

2883 G37

25155

LTM2883-3, VCC = 3.3VLTM2883-5, VCC = 5V

EFFICIENCY

POWER LOSS

LOAD CURRENT (mA)0

V+ , |V– | V

OLTA

GE (V

)

14

7

8

9

10

12

11

13

620105 15

2883 G38

25

LTM2883-3VCC = 3.3V

V+, I+ = 10mAV–, I+ = 10mAV+, I+ = 15mAV–, I+ = 15mA

LOAD CURRENT (mA)0

V+ , |V– | V

OLTA

GE (V

)

14

7

8

9

10

12

11

13

620105 2515 30

2883 G39

35

LTM2883-5VCC = 5V

V+, I+ = 10mAV–, I+ = 10mAV+, I+ = 15mAV–, I+ = 15mA


LTM2883

132883fc


pin FuncTionsLogic Side

DO2 (A1): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

DNC (A2): Do Not Connect Pin. Pin connected internally.

SCL (A3): Serial I2C Clock Input, Referenced to VL and GND. Logic input connected to isolated side SCL2 pin through isolation barrier. Clock is unidirectional from logic to isolated side. Do not float.

SDA (A4): Serial I2C Data Pin, Referenced to VL and GND. Bidirectional logic pin connected to isolated side SDA2 pin through isolation barrier. Under the condition of an isola-tion communication failure this pin is in a high impedance state. Do not float.

DI1 (A5): Digital Input, Referenced to VL and GND. Logic input connected to O1 through isolation barrier. The logic state on DI1 translates to the same logic state on O1. Do not float.

GND (A6, B2 to B6): Circuit Ground.

ON (A7): Enable. Enables power and data communica-tion through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float.

VL (A8): Logic Supply. Interface supply voltage for pins DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is 3V to 5.5V. Internally bypassed with 2.2µF.

DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5. Internally bypassed with 2.2µF.

Isolated Side

I2 (L1): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO2 through isolation barrier.

The logic state on I2 translates to the same logic state on DO2. Do not float.

DNC (L2): Do Not Connect Pin. Pin connected internally.

SCL2 (L3): Serial I2C Clock Output, Referenced to VCC2 and GND2. Logic output connected to logic side SCL pin through isolation barrier. Clock is unidirectional from logic to isolated side. SCL2 has a push-pull output stage, do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state.

SDA2 (L4): Serial I2C Data Pin, Referenced to VCC2 and GND2. Bidirectional logic pin connected to logic side SDA pin through isolation barrier. Output is biased high by a 1.8mA current source. Do not connect an external pull-up device to SDA2. Under the condition of an isolation communication failure this output defaults to a high state.

O1 (L5): Digital Output, Referenced to VCC2 and GND2. Logic output connected to DI1 through isolation barrier. Under the condition of an isolation communication failure O1 defaults to a high state.

VCC2 (L6): 5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V. Internally bypassed with 2.2µF.

V– (L7): –12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to –12.5V. Internally bypassed with 1µF.

V+ (L8): 12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 12.5V. Internally bypassed with 1µF.

I1 (K1): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float.

GND2 (K2 to K5): Isolated Ground.

AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV referenced to GND2.

AV– (K7): –12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is –1.22V referenced to GND2.

AV+ (K8): 12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 1.22V referenced to GND2.

(LTM2883-I)


LTM2883

142883fc


pin FuncTionsLogic Side

SDO (A1): Serial SPI Digital Output, Referenced to VL and GND. Logic output connected to isolated side SDO2 pin through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

DO2 (A2): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

SCK (A3): Serial SPI Clock Input, Referenced to VL and GND. Logic input connected to isolated side SCK2 pin through isolation barrier. Do not float.

SDI (A4): Serial SPI Data Input, Referenced to VL and GND. Logic input connected to isolated side SDI2 pin through isolation barrier. Do not float.

CS (A5): Serial SPI Chip Select, Referenced to VL and GND. Logic input connected to isolated side CS2 pin through isolation barrier. Do not float.

SDOE (A6): Serial SPI Data Output Enable, Referenced to VL and GND. A logic high on SDOE places the logic side SDO pin in a high impedance state, a logic low enables the output. Do not float.

ON (A7): Enable. Enables power and data communica-tion through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float.

VL (A8): Logic Supply. Interface supply voltage for pins SDI, SCK, SDO, DO1, DO2, CS, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 2.2µF.

DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

GND (B2 to B6): Circuit Ground.

VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5. Internally bypassed with 2.2µF.

Isolated Side

SDO2 (L1): Serial SPI Digital Input, Referenced to VCC2 and GND2. Logic input connected to logic side SDO pin through isolation barrier. Do not float.

I2 (L2): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO2 through isolation barrier. The logic state on I2 translates to the same logic state on DO2. Do not float.

SCK2 (L3): Serial SPI Clock Output, Referenced to VCC2 and GND2. Logic output connected to logic side SCK pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state.

SDI2 (L4): Serial SPI Data Output, Referenced to VCC2 and GND2. Logic output connected to logic side SDI pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state.

CS2 (L5): Serial SPI Chip Select, Referenced to VCC2 and GND2. Logic output connected to logic side CS pin through isolation barrier. Under the condition of an isolation com-munication failure this output defaults to a high state.

VCC2 (L6): 5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V. Internally bypassed with 2.2µF.

V– (L7): –12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to –12.5V. Internally bypassed with 1µF.

V+ (L8): 12.5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 12.5V. Internally bypassed with 1µF.

I1 (K1): Digital Input, Referenced to VCC2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float.

GND2 (K2 to K5): Isolated Ground.

AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV Referenced to GND2.

AV– (K7): –12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is –1.22V Referenced to GND2.

AV+ (K8): 12.5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 1.22V Referenced to GND2.

(LTM2883-S)


LTM2883

152883fc


block DiagraM

2883 BDb

2.2µF

2.2µFVCC VCC2

AVCC2

GND2

VL

110k

2.2µF

GND

ON

CS

SDOE

SDI

SDO

DO1

DO2

SCK

CS2

SDI2

SDO2

I1

I2

SCK2

DC/DCCONVERTER

ISOLATEDCOMMUNI-CATIONS

INTERFACE


INTERFACE

REG

15k

1µFV+

AV+

150k

REG

REG

16.2k

16.2k

1µFAV–

V–

150k

REG

LTM2883-I

LTM2883-S

2882 BDa

2.2µF

2.2µFVCC VCC2

AVCC2

GND2

VL

110k

2.2µF

GND

ON

DI1

DO2

DO1

SCL

SDA

O1

SDA2

I2

I1

SCL2

DC/DCCONVERTER


INTERFACE


INTERFACE

REG

15k

1µFV+

AV+

150k

REG

REG

16.2k

16.2k

1µFAV–

V–

150k

REG


LTM2883

162883fc


TesT circuiTs

INPUT

OUTPUT

CLtPLH tPHL

tR tF

90%

10%

10%

90%½VCC2

½VL

VL

VOL

VOH

0V

INPUT

OUTPUT

INPUT

OUTPUT

CL

2883 F01

tPLH tPHL

tR tF

90%

10%

10%

90%½VL

½VCC2

VCC2

VOL

VOH

0V

INPUT

OUTPUT

Figure 1. Logic Timing Measurements

Figure 2. Logic Enable/Disable Time

2883 F02

SDOE

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL

VL

VOH

VOL

0V

0VVL

SDO

SDO

SDOE

½VL

½VL

SDO

VL OR 0V

0V OR VCC2

SDO2

CL

RL

Figure 3. I2C Timing Measurements

tPHL tPLH

tF tR

30%½VL 70%

70%

30%VOL

VOH

SDA

SDA2

CL

VL

VOL

VOH

0V

SDA

SDA2

VL

RL

2883 F03

½VCC2

tPHL tPLH

tF tR

30%½VCC2 70%

70%

30%

½VL

VCC2

0V

SDA2

SDA

SDA

CL

VL

RL

SDA2


LTM2883

172883fc


applicaTions inForMaTionOverview

The LTM2883 digital µModule isolator provides a galvanically-isolated robust logic interface, powered by an integrated, regulated DC/DC converter, complete with decoupling capacitors. The LTM2883 is ideal for use in networks where grounds can take on different voltages. Isolation in the LTM2883 blocks high voltage differences, eliminates ground loops and is extremely tolerant of com-mon mode transients between ground planes. Error-free operation is maintained through common mode events greater than 30kV/μs providing excellent noise isolation.

Isolator µModule Technology

The LTM2883 utilizes isolator µModule technology to translate signals and power across an isolation barrier. Signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using core-less transformers formed in the µModule substrate. This system, complete with data refresh, error checking, safe shutdown on fail, and extremely high common mode im-munity, provides a robust solution for bidirectional signal isolation. The µModule technology provides the means to combine the isolated signaling with multiple regulators and a powerful isolated DC/DC converter in one small package.

DC/DC Converter

The LTM2883 contains a fully integrated DC/DC converter, including the transformer, so that no external components are necessary. The logic side contains a full-bridge driver, running at 2MHz, and is AC-coupled to a single trans-former primary. A series DC blocking capacitor prevents transformer saturation due to driver duty cycle imbalance. The transformer scales the primary voltage, and is recti-fied by a full-wave voltage doubler. This topology allows for a single diode drop, as in a center tapped full-wave bridge, and eliminates transformer saturation caused by secondary imbalances.

The DC/DC converter is connected to a low dropout regula-tor (LDO) to provide a regulated 5V output.

An integrated boost converter generates a regulated 14V supply and a charge pumped –14V supply. These rails are regulated to ±12.5V respectively by low dropout regulators. Performance of the –12.5V supply is enhanced by loading

the 12.5V supply. A load current of 1.5mA is sufficient to improve static and dynamic load regulation characteristics of the –12.5V output. The increased load allows the boost regulator to operate continuously and in turn improves the regulation of the inverting charge pump.

The internal power solution is sufficient to provide a mini-mum of 20mA of current from VCC2 and V+, and 15mA from V–. VCC and VCC2 are each bypassed with 2.2µF ceramic capacitors, and V+ and V– are bypassed with 1µF ceramic capacitors.

VL Logic Supply

A separate logic supply pin VL allows the LTM2883 to in-terface with any logic signal from 1.62V to 5.5V as shown in Figure 4. Simply connect the desired logic supply to VL.

There is no interdependency between VCC and VL; they may simultaneously operate at any voltage within their specified operating ranges and sequence in any order. VL is bypassed internally by a 2.2µF capacitor.

Hot-Plugging Safely

Caution must be exercised in applications where power is plugged into the LTM2883’s power supplies, VCC or VL, due to the integrated ceramic decoupling capacitors. The

2883 F04

ON

CS CS2

LTM2883-S

ANY VOLTAGE FROM1.62V TO 5.5V

3V TO 3.6V LTM2883-34.5V TO 5.5V LTM2883-5

EXTERNALDEVICE

VL

VCC

GND GND2

SDI SDI2

SCK SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO

DO2

SDO2

I2

DO1 I1

ISOL

ATIO

N BA

RRIE

R

SDOE

Figure 4. VCC and VL Are Independent


LTM2883

182883fc


applicaTions inForMaTion

Figure 5. Adjustable Voltage Rails

parasitic cable inductance along with the high Q char-acteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the LTM2883. Refer to Linear Technology Ap-plication Note 88, entitled Ceramic Input Capacitors Can Cause Overvoltage Transients for a detailed discussion and mitigation of this phenomenon.

Isolated Supply Adjustable Operation

The three isolated power rails may be adjusted by con-nection of a single resistor from the adjust pin of each output to its associated output voltage or to GND2. The pre-configured voltages represent the maximums for guaranteed performance. Figure 5 illustrates configura-tion of the output power rails for VCC2 = 3.3V, V+ = 10V, and V– = –10V.

Table 1. Voltage Adjustment FormulaOUTPUT VOLTAGE

RESISTOR (Ax TO Vx) TO REDUCE OUTPUT

RESISTOR (Ax TO GND2) TO INCREASE OUTPUT

VCC2 110k • VCC2 – 0.6( )5 – VCC2

66kVCC2 – 5

V+, V– 150k • V+ ,V– – 1.22( )12.5 – V+ ,V–

183k

V+ ,V– – 12.5

Channel Timing Uncertainty

Multiple channels are supported across the isolation bound-ary by encoding and decoding of the inputs and outputs. Up to three signals in each direction are assembled as a serial packet and transferred across the isolation barrier. The time required to transfer all 3 bits is 100ns maximum, and sets the limit for how often a signal can change on the opposite side of the barrier. Encoding transmission is independent for each data direction. The technique used assigns SCK or SCL on the logic side, and SDO2 or I2 on the isolated side, the highest priority such that there is no jitter on the associated output channels, only delay. This preemptive scheme will produce a certain amount of uncertainty on the other isolation channels. The resulting pulse width uncertainty on these low priority channels is typically ±6ns, but may vary up to ±44ns if the low priority channels are not encoded within the same high priority serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2883-S provides a SPI compatible isolated inter-face. The maximum data rate is a function of the inherent channel propagation delays, channel to channel pulse width uncertainty, and data direction requirements. Chan-nel timing is detailed in Figures 5 through 8 and Tables 3 and 4. The SPI protocol supports four unique timing configurations defined by the clock polarity (CPOL) and clock phase (CPHA) summarized in Table 2.

Table 2. SPI ModeCPOL CPHA DATA TO (CLOCK) RELATIONSHIP

0 0 Sample (Rising) Set-Up (Falling)0 1 Set-Up (Rising) Sample (Falling)1 0 Sample (Falling) Set-Up (Rising)1 1 Set-Up (Falling) Sample (Rising)

To decrease the output voltage a resistor must be connected from the output voltage pin to the associated adjust pin. To increase the output voltage connect a resistor to the adjust pin to GND2. Use the equations listed in Table 1 to calculate the resistances required to adjust each output. The output voltage adjustment range for VCC2 is 3V to 5.5V. Adjustment range for V+ and V– is ±1.22V to approximately ±13.5V. Operation at low output voltages for V+ or V– may result in thermal shutdown due to low dropout regulator power dissipation.

2883 F05

CS CS2

LTM2883-5S

VL

VCC5V

GND GND2

SDI SDI2

DO2

SCK SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2

I2

DO1 I1

ISOL

ATIO

N BA

RRIE

R

3.3V174k

10V

–10V

530k

530k

ON

SDOE


LTM2883

192883fc


The maximum data rate for bidirectional communication is 4MHz, based on a synchronous system, as detailed in the timing waveforms. Slightly higher data rates may be achieved by skewing the clock duty cycle and minimiz-ing the SDO to SCK set-up time, however the clock rate is still dominated by the system propagation delays. A discussion of the critical timing paths relative to Figure 6 and 7 follows.

applicaTions inForMaTion• CS to SCK (master sample SDO, 1st SDO valid)

t0 → t1 ≈50ns, CS to CS2 propagation delay

t1 → t1+ Isolated slave device propagation (response time), asserts SDO2

t1 → t3 ≈50ns, SDO2 to SDO propagation delay

t3 → t5 Set-up time for master SDO to SCK

Figure 6. SPI Timing, Bidirectional, CPHA = 0

Figure 7. SPI Timing, Bidirectional, CPHA = 1

2883 F06

SDO2

SDO

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 0

t0 t1 t2 t3 t4 t5 t6 t7t8

t9 t10 t11 t12 t13 t14 t15 t17 t18

INVALID

2883 F07

SDO2

SDO

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 1

t0 t1 t2 t3 t4 t5 t6 t7t8

t9 t10 t11 t12 t13 t14 t15 t16 t17 t18

INVALID


LTM2883

202883fc


applicaTions inForMaTion• SDI to SCK (master data write to slave)

t2 → t4 ≈50ns, SDI to SDI2 propagation delay

t5 → t6 ≈50ns, SCK to SCK2 propagation delay

t2 → t5 ≥50ns, SDI to SCK, separate packet non-zero set-up time

t4 → t6 ≥50ns, SDI2 to SCK2, separate packet non-zero set-up time

• SDO to SCK (master sample SDO, subsequent SDO valid)

t8 set-up data transition SDI and SCK

t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2 propagation delay

t10 SDO2 data transition in response to SCK2

t10 → t11 ≈50ns, SDO2 to SDO propagation delay

t11 → t12 Set-up time for master SDO to SCK

Table 3. Bidirectional SPI Timing Event DescriptionTIME CPHA EVENT DESCRIPTION

t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output enabled, initial data is not equivalent to slave device data output

t0 to t1, t17 to t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical

t1 0, 1 Slave device chip select output data enable

t2 0 Start of data transmission, data set-up

1 Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t1 to t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical

t3 0, 1 Slave data output valid, logic side

t2 to t4 0 Propagation delay of data, logic side to isolated side

1 Propagation delay of data and clock, logic side to isolated side

t5 0, 1 Logic side data sample time, half clock period delay from data set-up transition

t5 to t6 0, 1 Propagation delay of clock, logic to isolated side

t6 0, 1 Isolated side data sample time

t8 0, 1 Synchronous data and clock transition, logic side

t7 to t8 0, 1 Data to clock delay, must be ≤13ns

t8 to t9 0, 1 Clock to data delay, must be ≤3ns

t8 to t10 0, 1 Propagation delay clock and data, logic to isolated side

t10, t14 0, 1 Slave device data transition

t10 to t11, t14 to t15 0, 1 Propagation delay slave data, isolated to logic side

t11 to t12 0, 1 Slave data output to sample clock set-up time

t13 0 Last data and clock transition logic side

1 Last sample clock transition logic side

t13 to t14 0 Propagation delay data and clock, logic to isolated side

1 Propagation delay clock, logic to isolated side

t15 0 Last slave data output transition logic side

1 Last slave data output and data transition, logic side

t15 to t16 1 Propagation delay data, logic to isolated side

t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side

t18 0, 1 Chip select transition isolated side, slave data output disabled


LTM2883

212883fc



Figure 8. SPI Timing, Unidirectional, CPHA = 0

Figure 9. SPI Timing, Unidirectional, CPHA = 1

2883 F08

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 0

t0 t1 t2 t3 t4 t5 t7t6

t9t8 t11 t12

2883 F09

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 1

t0 t1 t2 t3 t4 t5 t7t6

t9t8 t11t10 t12

Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod-ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 4.

Additional requirements to insure maximum data rate are:

• CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI

• SDI and SCK set-up data transition occur within the same data packet. Referencing Figure 6, SDI can pre-cede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns (t8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 → t5) or lag SCK by 3ns (t5 → t6).

Inter-IC Communication (I2C) Bus

The LTM2883-I provides an I2C compatible isolated in-terface, Clock (SCL) is unidirectional, supporting master mode only, and data (SDA) is bidirectional. The maximum


LTM2883

222883fc



data rate is 400kHz which supports fast-mode I2C. Timing is detailed in Figure 10. The data rate is limited by the slave acknowledge setup time (tSU;ACK), consisting of the I2C standard minimum setup time (tSU;DAT) of 100ns, maximum clock propagation delay of 225ns, glitch filter and isolated data delay of 350ns maximum, and the combined isolated and logic data fall time of 500ns at maximum bus load-ing. The total setup time reduces the I2C data hold time (tHD;DAT) to a maximum of 125ns, guaranteeing sufficient data setup time (tSU;ACK).

The isolated side bidirectional serial data pin, SDA2, simplified schematic is shown in Figure 11. An internal

1.8mA current source provides a pull-up for SDA2. Do not connect any other pull-up device to SDA2. This current source is sufficient to satisfy the system requirements for bus capacitances greater than 200pF in FAST mode and greater than 400pF in STANDARD mode.

Additional proprietary circuitry monitors the slew rate on the SDA and SDA2 signals to manage directional control across the isolation barrier. Slew rates on both pins must be greater than 1V/μs for proper operation.

The logic side bidirectional serial data pin, SDA, requires a pull-up resistor or current source connected to VL. Follow

Table 4. Unidirectional SPI Timing Event DescriptionTIME CPHA EVENT DESCRIPTION

t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns

t0 to t1 0, 1 Propagation delay chip select, logic to isolated side

t2 0 Start of data transmission, data set-up

1 Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t2 to t3 0 Propagation delay of data, logic side to isolated side

1 Propagation delay of data and clock, logic side to isolated side

t3 0, 1 Logic side data sample time, half clock period delay from data set-up transition

t3 to t5 0, 1 Clock propagation delay, clock and data transition

t4 to t5 0, 1 Data to clock delay, must be ≤13ns

t5 to t6 0, 1 Clock to data delay, must be ≤3ns

t5 to t7 0, 1 Data and clock propagation delay

t8 0 Last clock and data transition

1 Last clock transition

t8 to t9 0 Clock and data propagation delay

1 Clock propagation delay

t9 to t10 1 Data propagation delay

t11 0, 1 Asynchronous chip select transition, end of transmission

t12 0, 1 Chip select transition isolated side

Figure 10. I2C Timing Diagram

2883 F10

SDA

1 8 9

SDA2

SCL

SCL2

START tPROP tSU;DAT tHD;DAT tSU;ACK

SLAVE ACK

STOP


LTM2883

232883fc


the requirements in Figures 12 and 13 for the appropri-ate pull-up resistor on SDA that satisfies the desired rise time specifications and VOL maximum limits for FAST and STANDARD modes. The resistance curves represent the maximum resistance boundary; any value may be used to the left of the appropriate curve.

The isolated side clock pin, SCL2, has a weak push-pull output driver; do not connect an external pull-up device. SCL2 is compatible with I2C devices without clock stretch-ing. On lightly loaded connections, a 100pF capacitor from SCL2 to GND2 or RC low-pass filter (R = 500Ω C = 100pF) can be used to increase the rise and fall times and minimize noise.

Some consideration must be given to signal coupling between SCL2 and SDA2. Separate these signals on a printed circuit board or route with ground between. If these signals are wired off board, twist SCL2 with VCC2 and/or GND2 and SDA2 with GND2 and/or VCC2, do not twist SCL2 and SDA2 together. If coupling between SCL2 and SDA2 is unavoidable, place the aforementioned RC filter at the SCL2 pin to reduce noise injection onto SDA2.

RF, Magnetic Field Immunity

The isolator µModule technology used within the LTM2883 has been independently evaluated, and successfully passed the RF and magnetic field immunity testing requirements per European Standard EN 55024, in accordance with the following test standards:

EN 61000-4-3 Radiated, Radio-Frequency, Electromagnetic Field Immunity

EN 61000-4-8 Power Frequency Magnetic Field Immunity

EN 61000-4-9 Pulsed Magnetic Field Immunity

Tests were performed using an unshielded test card de-signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 5.

Table 5.TEST FREQUENCY FIELD STRENGTH

EN 61000-4-3 Annex D 80MHz to 1GHz 10V/m

1.4MHz to 2GHz 3V/m

2GHz to 2.7GHz 1V/m

EN 61000-4-8 Level 4 50Hz and 60Hz 30A/m

EN 61000-4-8 Level 5 60Hz 100A/m*

EN 61000-4-9 Level 5 Pulse 1000A/m

*non IEC method

CBUS (pF)10

R PUL

L_UP

(kΩ

)

30

25

5

10

15

20

0100

2883 F12

1000

V = 3VV = 3.3VV = 3.6VV = 4.5V TO 5.5V

CBUS (pF)10

R PUL

L_UP

(kΩ

)

10

9

1

3

5

7

2

4

6

8

0100

2883 F13

1000

V = 3VV = 3.3VV = 3.6VV = 4.5V TO 5.5V

Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA

Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA

Figure 11. Isolated SDA2 Pin Schematic

2883 F11

SDA2

1.8mA

FROMLOGIC

SIDE

TOLOGIC

SIDE

GLITCH FILTER



LTM2883

242883fc


TECHNOLOGY

applicaTions inForMaTionPCB Layout

The high integration of the LTM2883 makes PCB layout very simple. However, to optimize its electrical isolation characteristics, EMI, and thermal performance, some layout considerations are necessary.

• Under heavily loaded conditions VCC and GND current can exceed 300mA. Sufficient copper must be used on the PCB to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. Similarly, the VCC2 and GND2 conductors must be sized to support any external load current. These heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity.

• Input and output decoupling is not required, since these components are integrated within the package. An ad-ditional bulk capacitor with a value of 6.8µF to 22µF is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance.

• Do not place copper on the PCB between the inner col-umns of pads. This area must remain open to withstand the rated isolation voltage.

• The use of solid ground planes for GND and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions.

• For large ground planes a small capacitance (≤330pF) from GND to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing

any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, volt-age rating, leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates component selection issues; however, the PCB must be 4 layers. Care must be exercised in applying either technique to insure the voltage rating of the barrier is not compromised.

The PCB layout in Figures 14a and 14b shows the low EMI demo board for the LTM2883. The demo board uses a combination of EMI mitigation techniques, including both embedded PCB bridge capacitance and discrete GND to GND2 capacitors. Two safety rated type Y2 capacitors are used in series, manufactured by MuRata, part number GA342QR7GF471KW01L. The embedded capacitor ef-fectively suppresses emissions above 400MHz, whereas the discrete capacitors are more effective below 400MHz.

EMI performance is shown in Figure 15, measured using a Gigahertz Transverse Electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, Testing and Measure-ment Techniques – Emission and Immunity Testing in Transverse Electromagnetic Waveguides.

Figure 14a. LTM2883 Low EMI Demo Board Layout


LTM2883

252883fc


Top Layer Inner Layer 2

Inner Layer 1 Bottom Layer

Figure 14b. LTM2883 Low EMI Demo Board Layout (DC1748A)



LTM2883

262883fc



Figure 15. LTM2883 Low EMI Demo Board Emissions

FREQUENCY (MHz)0

–30

dBµV

/m

–20

0

10

20

600 700 800 900

60

2883 F15

–10

100 200 300 400 500 1000

30

40

50

DETECTOR = QuasiPeakRBW = 120kHzVBW = 300kHzSWEEP TIME = 17s# OF POINTS = 501

DC1748A-A

DC1748A-B

CISPR 22 CLASS B LIMIT

2883 F16

LTM2883-5I

5V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCLµCSDA

VCC

GND

VREF

LTC2301, ADC

SDA

VDD GND

AD0

AD1

REFC

GND IN–

IN+

12

10

11

1

2

7

9

8

6

5

GNDSCL3 4

REF

LTC2631A-LM12, DAC

CA0 R_SEL

SCL

SDA

VOUT

GND VCC

3

1

3

2

4

8

1

2

4

6

8

7

5

0.1µF

0.1µF

0.1µF

1µF

1.7k

1.7k

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AV+

V–

AV–

AVCC2

V+

–12.5V

12.5V

1.25V

2.5V F.S.

4V F.S.

2.5V

5VVCC2

DO2 I2

DO1 I1

GND2

–

+

45

7

6±10V OUT

0.1µF12.5V

–12.5V

0.1µF

+

–

8

1

9

2

10

3

1/2 LTC2055

LT1991G = 8

5

6

7

–

+1/2 LTC2055

+

–

1µF

10µF 0.1µF

45

7

6

±10V IN

0.1µF12.5V

–12.5V

0.1µF

8

1

9

2

10

3

LT1991G = 0.2

Figure 16. Isolated I2C 12-Bit, ±10V Analog Input and Output

Typical applicaTions


LTM2883

272883fc



Figure 17. Isolated SPI Device Expansion

2883 F17

ON

CS

I2

CS2

LTM2883-3S

VL

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2

CSA

MOSI

SCK

CSB

MISO

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

74VC1G123

Rx/Cx Cx

CLR

A

B Q

3.3V

1µF

1nF

µC

CSA

CSB

MISO

VCC

GND

MOSI

SCK

CSA

CSB

MOSI

SCK

10k

Figure 18. Isolated I2C Buffer with Programmable Outputs

2883 F18

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

ENABLE

5V

SDA

SCLIN

DNC

SCL2

AV+

V–

AV–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L610k

L1

K1

K2

VCCLTC4302-1

GND

SDAIN SDAOUT

SCLIN

CONN

SCLOUT

ADDR GPIO2

GPIO1

SDA

SCLOUT

GPIO2

GPIO1

3

1

2

4

5

8

10

9

7

6

8.66k

137Ω

10k

10k 10k

LTM2883-5I


LTM2883

282883fc



Figure 19. 16-Channel Isolated Temperature to Frequency Converter

2883 F19

ON

CS

I2

CS2

LTM2883-5S

VL

VCC

GND

SDI SDI2

SDOE

SCK

5V

DO2

SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

OxµC

Oz

Oy

Iy

Ix

1M

1M

VCC

GNDX2

DG4051A

NTC THERMISTORS, MURATA NTSD1WD104, 100k

C

VCC X0

X

A

X1

B X3

X4

11

16

3

10

9

15

13

–t°

14

12

1

X5

GND

ENABLE

VEE X6

X7

6

7

8

5

2

4

SET

LTC1799

OUT V+

DIV

GND4

5

3

1

23.01k

SET

LTC1799

TEMPERATURE (°C) FREQUENCY (kHz)

–40–30–20–100102030405060708090100110120

1.231.461.872.583.775.678.6413.0919.5328.4740.6555.8774.4596.08119.83144.73169.36

OUT V+

DIV

GND4

5

3

1

23.01k

–t°

–t°

–t°

–t°

–t°

–t°

–t°

X2

DG4051A

C

VCC X0

X

A

X1

B X3

X4

11

16

3

10

9

15

13

–t°

14

12

1

X5

GND

ENABLE

VEE X6

X7

6

7

8

5

2

4

–t°

–t°

–t°

–t°

–t°

–t°

–t°


LTM2883

292883fc


2883 F20

ON

CS

I2

CS2

LTM2883-5S

VL

VCC

GND

SDI SDI2

SDOE

SCK

5V

DO2

SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

–12.5V UV

12.5V ENABLE

5V ENABLE

12.5V UV

–12.5V ENABLE

SWITCHED 12.5V

SWITCHED –12.5V

SWITCHED 5V

5V UV

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

V2

LTC2902

CRT

COMP3 COMP2

COMP1

V3

COMP4

V1 V4

VREF

3

1

2

4

5

14

16

15

13

12

VPG

RDIS

RST

T0 GND

T1

6

7

8

11

10

9

0.1µF

10k

226k

9.53k

93.1k

20k

196k

100k

100k

IRF7509

IRF7509

IRLML2402

IRF7509

100k

100k


Figure 20. Digitally Switched Triple Power Supply with Undervoltage Monitor


LTM2883

302883fc



Figure 21. Quad 16-Bit ±10V Output Range DAC

–12.5V

2883 F21

LTM2883-3S

3.3V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCKµC

MOSI

VCC

GND

VOUTC

LTC2654-L16

SDO

CS VOUTA

SDI

SCK

VOUTB

CLR VOUTD

REFLO

8

7

9

11

10

13

2

VCC REFOUT

LDAC REFC

4

14

1

15

6

5

3

GNDPORSEL12 16

3

4

2

5

1

0.1µF

0.1µF

ON

CS

I2

CS2

VL

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

AV+

V–

AV–

AVCC2

V+

–12.5V

12.5V

VCC2

SDO

CS

MISO SDO2

DO1 I1

GND2

–

+

45

7

6±10V OUTA

0.1µF

12.5V

–12.5V

0.1µF

8

1

9

2

10

3

LTC2054

45

7

6±10V OUTB

0.1µF

12.5V

0.1µF

+

–

+

–

8

1

9

2

10

3

LT1991G = 8

–12.5V

45

7

6±10V OUTC

0.1µF

12.5V

0.1µF

+

–

8

1

9

2

10

3

LT1991G = 8

–12.5V

45

7

6±10V OUTD

0.1µF

12.5V

0.1µF

+

–

8

1

9

2

10

3

LT1991G = 8

0.1µF

LT1991G = 8

1.25V

5V


LTM2883

312883fc



Figure 22. –48V, 200W Hot Swap Controller with Isolated I2C Interface

2883 F22

LTM2883-5I

5V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCL

Ix

Ox

µCSDA

VCC

GND

10k

10k

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AV+

V–

AV–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2 VEE

VEE

VOUT

SDAI

LTC4261CGNSS

UVL FLTIN

UVH

ADIN2

SCL

OV SDAO

ALERT

10

8

9

11

19

5

22

6

4

3

ONTMR20

ADR0

EN

PGI

ADR1

1

26

25

24ADIN

PGI0

PG

PWRGD2

–48V RTN

–48V INPUTIRF1310NS

PWRGD1

28

27

23

VEE

13

SENSE

14

GATE

15

INTVCC

7

VIN

21

DRAIN

16

RAMP

18

2

10nF100V0.1µF47nF

100nF 220nF1µF

0.1µF

330µF100V

1k

16.9k

11.8k

453k 1k, ×4 IN SERIES1/4W EACH

47nF10Ω

10k 402k0.008Ω

1%

1M

+

10k


LTM2883

322883fc


Figure 23. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown


ON

CS

I2

CS2

LTM2883-3S

VL

VCC

GND

SDI SDI2

SCK

DO2

SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

SCKO

LTC6803-1

VMODE

CSI CSO

SDO

SDI

SDOI

SCKI V+

C12

42

44

43

41

40

S12

WDT

GPIO2

GPIO1 C11

S11

39

38

37

3

1

2

4

5

6

7

8

1µF

µC

CS

MISO

VCC

GND

3.3V

MOSI

SCK

S10

VREF

MM

TOS

C10

VREG C9

S9

35

36

34

33

10

9

11

12

C8

NC

VTEMP2

VTEMP1 S8

C7

32

31

30

13

14

15

C6

S2

V–

S1

S7

C1 S6

C5

28

29

27

26

17

16

18

19

S5

C3

C2

S3 C4

S4

25

24

23

20

21

22

1µF1µF

100k

100k

100k

100k

3.3k3.3k 3.3k 3.3k

SDOE

2883 F23

74LVC3G07

LTM2883-3I

3.3V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCLµC

SDA

VCC

GND

10k

10k

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AV+

V–

AV–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2

LTC4151

SHDN

ADINSDA

SCL

GND

ADR0

ADR1

48V

SENSE–SENSE+ VIN

VOUT

1.37k1%

0.02Ω

100k AT 25°C, 1%VISHAY 2381 6154.104

NADIN IS THE DIGITAL CODE MEASUREDBY THE ADC AT THE ADIN PIN

T CLN

N

C T

ADIN

( ).

,° =+ −

− − ° <3950

8 9651000

1273 40 << °150 C

2883 F24

Figure 24. Isolated I2C Voltage, Current and Temperature Power Supply Monitor


LTM2883

332883fc



LTM2883-5I

5V

SHUTDOWN

ENABLE

SDA

SCLIN

INTERRUPT

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

10k

10k

100k

174kON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AV+

V–

AV–

AVCC2

V+

VCC2

DO2 I2

DO1 I1

GND2

1/4 LTC4266

PHY

(NETWORKPHYSICAL

LAYERCHIP)

RESET

INT

DETECT

BYP

SDAIN

SCL

AD0

AD1

AD2

AD3

SDAOUT

AUTO

SHDN1 VDD

DGND AGND VEE SENSE GATE OUTQ1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10TFB1, FB2: TDK MPZ2012S601AT1: PULSE H609NL OR COILCRAFT ETH1-230LD

2883 F25

1µFSMAJ58A

–48V

0.1µF

0.1µF

0.22µF

0.25Ω

S1B

Q1

S1B

CMPD3003

FB2

RJ45CONNECTOR

FB1

T1•

•

•

•

••

75Ω 75Ω10nF 10nF

1

2

3

•

•

•

•

••

75Ω 75Ω10nF 10nF

4

6

7

8

5

1nF

Figure 25. One Complete Isolated Powered Ethernet Port


LTM2883

342883fc


package DescripTionPlease refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

5. P

RIM

ARY

DATU

M -Z

- IS

SEAT

ING

PLAN

E

6. S

OLDE

R BA

LL C

OMPO

SITI

ON IS

96.

5% S

n/3.

0% A

g/0.

5% C

u

7PA

CKAG

E RO

W A

ND C

OLUM

N LA

BELI

NG M

AY V

ARY

AMON

G µM

odul

e PR

ODUC

TS. R

EVIE

W E

ACH

PACK

AGE

LAYO

UT C

AREF

ULLY

!

NOTE

S:1.

DIM

ENSI

ONIN

G AN

D TO

LERA

NCIN

G PE

R AS

ME

Y14.

5M-1

994

2. A

LL D

IMEN

SION

S AR

E IN

MIL

LIM

ETER

S

BAL

L DE

SIGN

ATIO

N PE

R JE

SD M

S-02

8 AN

D JE

P95

43

DETA

ILS

OF P

IN #

1 ID

ENTI

FIER

ARE

OPT

IONA

L,BU

T M

UST

BE L

OCAT

ED W

ITHI

N TH

E ZO

NE IN

DICA

TED.

THE

PIN

#1 ID

ENTI

FIER

MAY

BE

EITH

ER A

MOL

D OR

M

ARKE

D FE

ATUR

E

PACK

AGE

TOP

VIEW

4

PIN

“A1”

CORN

ER

X

Y

aaa

Zaaa Z

PACK

AGE

BOTT

OM V

IEW

3

SEE

NOTE

S

SUGG

ESTE

D PC

B LA

YOUT

TOP

VIEW

BGA

32 1

112

REV

D

LTM

XXXX

XXµM

odul

e

TRAY

PIN

1BE

VEL

PACK

AGE

IN T

RAY

LOAD

ING

ORIE

NTAT

ION

COM

PONE

NTPI

N “A

1”

DETA

IL A

PIN

1

0.0000.635

0.635

1.905

1.905

3.175

3.175

4.445

4.445

6.35

0

6.35

0

5.08

0

5.08

0

0.00

0

DETA

IL A

Øb (3

2 PL

ACES

)

F G H LJ KEA B C D

21

43

56

78

DETA

IL B

SUBS

TRAT

E

0.27

– 0

.37

2.45

– 2

.55

// bbb Z

D

A

A1

b1

ccc

Z

DETA

IL B

PACK

AGE

SIDE

VIE

W

MOL

DCA

P

Z

MX

YZ

ddd

MZ

eee

0.63

0 ±0

.025

Ø 3

2x

SYM

BOL

A A1 A2 b b1 D E e F G aaa

bbb

ccc

ddd

eee

MIN

3.22

0.50

2.72

0.60

0.60

NOM

3.42

0.60

2.82

0.75

0.63

15.0

11.2

51.

2712

.70

8.89

MAX

3.62

0.70

2.92

0.90

0.66

0.15

0.10

0.20

0.30

0.15

NOTE

S

DIM

ENSI

ONS

TOTA

L NU

MBE

R OF

BAL

LS: 3

2

E

b

e

e

b

A2

F

G

BGA

Pack

age

32-L

ead

(15m

m ×

11.

25m

m ×

3.4

2mm

)(R

efer

ence

LTC

DW

G #

05-0

8-18

51 R

ev D

)

7

SEE

NOTE

S


LTM2883

352883fc


Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisToryREV DATE DESCRIPTION PAGE NUMBER

A 11/12 Storage temperature range updated. 2

B 8/13 Added CTI/DTI parameters and Notes 6, 7 to Isolation Characteristics table 6, 7

C 5/14 Removed H-grade throughout data sheetChanged Depth of Erosion parameterChanged overtemperature protection threshold

1-3667


LTM2883

362883fc


Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417

LINEAR TECHNOLOGY CORPORATION 2012

LT 0514 REV C • PRINTED IN USA

relaTeD parTs

Typical applicaTionPrecision 4mA to 20mA Sink/Source with Current Monitor

1µF

0.01µF

ON

CS

I2

CS2

LTM2883-3S

VL

VCC

GND

SDI SDI2

SDOE

SCK

3.3V

DO2

SCK2

AV+

V–

AV–

AVCC2

V+

VCC2

SDO SDO2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

3 1

2

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

1µF

µC

CS

MISO

VCC

GND

MOSI

SCK

2883 TA02

0.1µF

OUTIN

LT6660-3

GNDIN–

LTC2452, ADC

REF VCC

CS

SCK

IN+

SDO GND

1

3

7

8

5

4

6

2

VOUT

LTC2641, DAC

REF GND

CS

SCK

VDD

DIN CLR

3

1

2

4

6

8

7

5

3

2

4

7

6

–

+LTC1050

0.1µFSOURCE

RETURN

12.5V

–5V

SINK

Si1555DL_N

0.1µF

100k

75k

11

6

7

10

14

23

15–

+LTC1100G = 10

1k

15Ω0.1%3V

5V

PART NUMBER DESCRIPTION COMMENTSLTM2881 Isolated RS485/RS422 µModule Transceiver Plus Power 20Mbps 2500VRMS Isolation with Power in LGA/BGA PackageLTM2882 Dual Isolated RS232 µModule Transceiver Plus Power 20Mbps 2500VRMS Isolation with Power in LGA/BGA PackageLTC4310 Hot-Swappable I2C Isolators Bidirectional I2C Communication, Low Voltage Level ShiftingLTC6803 Multistack Battery Monitor Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple

Devices Interconnected via SPILTC2309/LTC2305/LTC2301

12-Bit, 8-/2-/1-Channel, 14ksps SAR ADCs with I2C 5V, Internal Reference, Software Compatible Family

LTC2631/LTC2630 Single 12-/10-/8-Bit I2C or SPI VOUT DACs with 10ppm/°C Reference

180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output

LTC2641/LTC2642 16-/14-/12-Bit VOUT DACs ±1LSB INL/DNL, 0.5nV•s Glitch, 1μs Settling, 3mm × 3mm DFNLTC2452/LTC2453 Ultra-Tiny 16-Bit Differential ±5.5V Δ∑ ADCs, SPI/I2C 2LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT PackagesLTC1859/LTC1858/LTC1857

8-Channel 16-/14-/12-Bit, 100ksps, ±10V SoftSpan™ SAR ADCs with SPI

5V Supply, Up to ±10V Configurable Unipolar/Bipolar Input Range, Pin Compatible Family in SSOP-28 package

LTC2487/LTC2486 16-Bit 2- or 4-Channel Δ∑ ADCs with Easy Drive™ Inputs and I2C/SPI Interface

16-Bit and 24-Bit Δ∑ ADC Family, Up to 16 Input Channels and Integrated Temperature Sensor

LTC4303/LTC4304 Hot Swappable I2C Bus Buffers 2.7V to 5.5V Supply, Rise Time Acceleration, Stuck Bus Protection, ±15kV ESD

LTC1100 Zero-Drift Instrumentation Amplifier Fixed Gain of 10 or 100LT1991 Precision, Pin Configurable Gain Difference Amplifier Gain Range –13 to +14LTC2054/LTC2055 Micropower Zero-Drift Op Amps 3V/5V/±5V SupplyLTC4151 High Voltage I2C Current and Voltage Monitor Wide Operating Range: 7V to 80VLTC4261 Negative Voltage Hot Swap™ Controller with ADC and

I2C MonitoringFloating Topology Allows Very High Voltage Operation

LTC1799 Wide Frequency Range Silicon Oscillator 1kHz to 30MHzLTC6990 TimerBlox™ Voltage Controlled Oscillator 488Hz to 2MHzLTM2892 SPI/Digital or I2C Isolated µModule 3500VRMS Isolation, 6 Channels

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM2883




http://www.linear.com/LTC4310





http://www.linear.com/product/LTC2631














http://www.linear.com/LT1991









ltm2883 - spi/digital or i2c µmodule isolator with adjustable ±12.5

Documents