ltc6561 four-channel multiplexed transimpedance amplifier ... · gnd in3 order information tube...

LTC6561

1Rev. B

For more information www.analog.com

TYPICAL APPLICATION

FEATURES DESCRIPTION

Four-Channel Multiplexed Transimpedance Amplifier

with Output Multiplexing

The LTC®6561 is a low-noise four-channel, transimped-ance amplifier (TIA)with 220MHz bandwidth. The LTC6561 multi-channel transimpedance amplifier’s low noise, high transimpedance, and low power dissipation are ideal for LIDAR receivers using Avalanche Photodiodes (APDs). The amplifier features 74kΩ transimpedance gain and 30µA linear input current range. Using an APD input cir-cuit with a total capacitance of 2pF, the input current noise density is 4.5pA/√Hz at 200MHz. With lower capacitance, noise and bandwidth improve further. Only a 5V single supply is needed and the device consumes only 200mW. Utilizing the internal 4-to-1 MUX along with the LTC6561’s output MUX; multiple 4-channel LTC6561 devices can be combined to directly interface with 8, 12, 16 and 32-chan-nel APD arrays. The LTC6561’s fast overload recovery and fast channel switchover make it well suited for LIDAR receivers with multiple APDs. Its single-ended output can swing 2VP-P on a 100Ω load. While its low impedance op amp-style output can drive back-terminated 50Ω cables.

The LTC6561 is packaged in a compact 4mm × 4mm 24-pin leadless QFN package with an exposed pad for thermal management and low inductance.

Typical Application with DC-Coupled Inputs Driving a Time-to-Digital Converter with Back-Terminated Cable

APPLICATIONS

n 220MHz –3dB Bandwidth with 2pF Input Capacitance n Single-Ended Output n 74kΩ Transimpedance Gain n 4.8pA/√Hz Input Current Noise Density at

200MHz (2pF) n 64nARMS Integrated Input Current Noise Over

200MHz (2pF) n Linear Input Range 0µA to 30µA n Overload Current > ±400mA Peak n Fast Overload Recovery 12ns, 1mA n Fast Channel Switchover < 50ns n Single 5V Supply n 200mW Power Dissipation for 4 Channels n 2VP-P Output Swing on 100Ω Load n 4mm × 4mm, 24-Lead QFN Package n Output MUX Combines Multiple 4-Channel Devices

to Create 4, 8,12,16, 24, 32 Channel Solutions

n LIDAR Receiver n Industrial Imaging

All registered trademarks and trademarks are the property of their respective owners.

Pulse Response at the Edge of the Overload Region (40µA)

WITH SERIES 50Ω, INTO 50Ω LOAD,RTEFF = 37kΩ

OUTPUT RESPONSE(0.5V/DIV)

INPUT PULSE(20µA/DIV)

5ns/DIV6561 F01b

47.5Ω WIRE-ORMUXOUT(2)

MULTIPLE LTC6561’s

6561 TA01a

VCCO

47.5Ω

50Ω

CHSEL1,0 O_MUX

O_MUX(2)

OUT

LTC6561VCC1,2

GND

IN1

VREF1

IN2

VREF2

IN3

VREF3

IN4

TIA

TIA

TIA

TIA

VREF4

4:1MUX

GAIN

OUTTERM

OUTPUTSTAGE

TIME-OF-FLIGHTDETECTOR

APD ARRAY–150V

+

–

Document Feedback

https://www.analog.com/LTC6561?doc=LTC6561.pdf

https://www.analog.com?doc=LTC6561.pdf


https://form.analog.com/Form_Pages/feedback/documentfeedback.aspx?doc=LTC6561.pdf&product=LTC6561&Rev=B

LTC6561

2Rev. B


PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (VCC1, VCC2, VCCO to GND) ......5.5VVoltage (CHSEL0, CHSEL1, O_MUX) ............. –0.3V to 5.5VAmplifier Reference Current (VREF1, VREF2, VREF3, VREF4) ....................................................... ±10mAAmplifier Reference Voltage (VREF1, VREF2, VREF3, VREF4) ............................................ –0.3V to 3.5VAmplifier Input Current (IN1, IN2, IN3, IN4) .................±400mA RMS ±2A Transient (10ns)Amplifier Output Current (OUT, OUTTERM) ........ +80mAOperating Temperature Range

LTC6561I (Note 2)................................–40°C to 85°C LTC6561H (Note 3) ............................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°CJunction Temperature ........................................... 150°C

(Note 1)

24 23 22 21 20 19

7 8 9

TOP VIEW

UF PACKAGE24-LEAD (4mm × 4mm) PLASTIC QFN

TJMAX = 150°C, θJA = 47°C/W, θJC = 4.5°C/WEXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

10 11 12

6

5

4

3

2

1

13

14

15

16

17

18VCCO

CHSEL0

VCC1

VREF1

GND

IN1

VCCO

O_MUX

VCC2

VREF4

GND

IN4

25GND

CHSE

L1

OUT

GND

GND

OUTT

ERM

DNC

IN2

GND

V REF

2

V REF

3

GND

IN3

ORDER INFORMATIONTUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6561IUF#PBF LTC6561IUF#TRPBF 6561 24-LEAD (4mm × 4mm) PLASTIC QFN –40°C to 85°C

LTC6561HUF#PBF LTC6561HUF#TRPBF 6561 24-LEAD (4mm × 4mm) PLASTIC QFN –40°C to 125°C

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

BW –3dB Bandwidth 200mVP-P,OUT and CIN,TOT = 2pF 220 MHz

RT Small Signal Transimpedance IIN < 2µAP-P l

63 47.7

74 85 101

kΩ

RIN Input Impedance f = 100kHz 236 Ω

ROUT Output Impedance f = 100kHz 3 Ω

In Input Current Noise Density f = 100MHz, CIN,TOT = 2pF 4.3 pA/√Hz

f = 200MHz, CIN,TOT = 2pF 4.8 pA/√Hz

Integrated Input Current Noise f = 0.1MHz to 100MHz, CIN,TOT = 2pF 43 nARMS

f = 0.1MHz to 200MHz, CIN,TOT = 2pF 64 nARMS

Adjacent Channel to Channel Isolation f = 100MHz –45 dB

Non Adjacent Channel Isolation f = 100MHz –65 dB

tRECOVER Overload Recovery Time Input Pulse = 1mA 12 ns

tSWITCH Channel Switchover Time DC Coupled Input 50 ns

tOMUX_SWITCH Output MUX Switchover Time DC Coupled Input 50 ns

AC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100Ω. Output is AC-coupled. Output taken from OUT pin.



https://www.analog.com/media/en/package-pcb-resources/package/tape-reel-rev-n.pdf?doc=LTC6561.pdf

LTC6561

3Rev. B


The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VCC1,2 = VCC0 = 5V, O_MUX = 0V, GND = 0V, ZLOAD = 100Ω. Output is AC-coupled. Output taken from OUT pin.

DC ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LTC6561I is guaranteed to meet specified performance from –40°C to 85°C.Note 3: The LTC6561H is guaranteed to meet specified performance from –40°C to 125°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN1,2,3,4 Pins and VREF1,2,3,4 Pins

VIN Input Bias Voltage Active Channel Inactive Channel

l

l

1.43 1.25 0.78 0.70

1.55

0.93

1.64 1.76 1.38 1.53

V V V V

VREF Input Reference Voltage Active Channel Inactive Channel

1.43 1.34

1.55 1.50

1.63 1.67

V V

Offset VIN – VREF Active Channel Inactive Channel

–12 –741

12 –116

mV mV

OUT Pin

VOUT Output Default Voltage O_MUX = 0V O_MUX = 3.3V, Standalone Device

l

l

0.83 0.79 0.32 0.28

1.10

0.60

1.47 1.67 0.88 0.92

V V V V

OVR Output Voltage Range IIN Current Range = 0 to –50µA l

1.22 0.98

1.90 2.58 2.80

VP-P VP-P

OUTTERM Internal Series Resistor for Optional Output 44 56 70.8 Ω

CHSEL0, CHSEL1, O_MUX Pins with Internal Pull-Down Resistors

VIL l 0.7 V

VIH l 1.5 V

IIL Pin Voltage = 0.7V l

16.9 15.4

20.7 26.0 28.0

µA µA

IIH Pin Voltage = 1.5V l

37 34

47 57 62

µA µA

CIN Input Capacitance 1.5 pF

RIN Input Resistance l

22 21

29 35 37

kΩ kΩ

Power Supply

VS Operating Supply Range 4.75 5 5.25 V

ICC1,2 Input Supply Current VCC1 and VCC2 Are Internally Tied Together

l

29.0 26.8

36.3 44.0 45.8

mA mA

ICC0 Output Supply Current Both VCCO Pins Are Internally Tied Together

l

1.8 1.7

2.3 2.8 2.9

mA mA

IS Total Supply Current (IS(VCC1,2) + IS(VCC0)) l

30.8 28.5

38.6 46.8 48.7

mA mA

PSRR(VCC1,2) Input Power Supply Rejection Ratio VCC1,2 = 4.75V to 5.25V, VCC0 = 5V l

21 15

25 dB dB

PSRR(VCC0) Output Power Supply Rejection Ratio VCC0 = 4.75V to 5.25V, VCC1,2 = 5V l

34 33

40 dB dB



LTC6561

4Rev. B


TYPICAL PERFORMANCE CHARACTERISTICS

ISUPPLY vs VSUPPLY Over Temperature ICCI vs VCCI Over Temperature ICCO vs VCCO Over Temperature

VIN vs Temperature VREF vs Temperature

VIN–VREF Offset vs Temperature RIN vs Temperature

VSUPPLY (V)2 2.5 3 3.5 4 4.5 5 5.5 6

0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.0

I SUP

PLY

(mA)

6561 G01

VSUP = VCCI = VCCO

125°C85°C25°C–40°C

TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120 140

1.0

1.2

1.4

1.6

1.8

2.0

V IN

(V)

6561 G04

TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120 140

–10.0

–6.0

–2.0

2.0

6.0

10.0

V IN–

V REF

OFF

SET

(mV)

6561 G06TEMPERATURE (°C)

–40 –20 0 20 40 60 80 100 120 1400

50

100

150

200

250

300

350

R IN

(Ω)

6561 G07

TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120 140

1.0

1.2

1.4

1.6

1.8

2.0

V REF

(V)

6561 G05

VCCI (V)2 2.5 3 3.5 4 4.5 5 5.5 6

0

5

10

15

20

25

30

35

40

45

50

I CCI

(mA)

6561 G02

125°C85°C25°C–40°C

VCCO (V)2 2.5 3 3.5 4 4.5 5 5.5 6

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

I CCO

(mA)

6561 G03

125°C85°C25°C–40°C



LTC6561

5Rev. B


RT Transimpedance vs Temperature


VIN vs IIN Over TemperatureVOUT vs IIN Over Temperature

RT Transimpedance vs IIN Over Temperature

3dB Bandwidth vs Temperature Over CIN,TOT

Input-Referred Noise Density with CIN,TOT = 0.5pF

Integrated Input-Referred Noise vs Bandwidth Over Temperature CIN,TOT = 0.5pF

TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120 140

0

20

40

60

80

100

R T (k

Ω)

6561 G08IIN (µA)

–40 –35 –30 –25 –20 –15 –10 –5 01.00

1.20

1.40

1.60

1.80

2.00

V IN

(V)

6561 G09

125°C85°C25°C–40°C

125°C85°C25°C–40°C

IIN (uA)–40 –35 –30 –25 –20 –15 –10 –5 0

0

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

V OUT

(V)

6561 G10

IIN (µA)–40 –35 –30 –25 –20 –15 –10 –5 0

0

20

40

60

80

100

R T T

RANS

IMPE

DANC

E (k

Ω)

6561 G11

125°C85°C25°C–40°C

TEMPERATURE (°C)–40 –20 0 20 40 60 80 100

0

50

100

150

200

250

300

3DB

BAND

WID

TH (M

Hz)

6561 G12

CIN,TOT = 0.5pFCIN,TOT = 2.2pFCIN,TOT = 4.0pF

INTEGRATED STARTING FROM 100kHzCIN,TOT = 0.5pF

FREQUENCY (MHz)0 50 100 150 200 250 300

0102030405060708090

100110120130140

INTE

GRAT

ED IN

PUT

REFE

RRED

NOI

SE (n

A RM

S)

6561 G14

125°C85°C25°C–40°C

FREQUENCY (MHz)0.1 1 10 100 500

0

2

4

6

8

10

12

14

16

INPU

T–RE

FERR

ED N

OISE

DEN

SITY

(pA/

√Hz)

6561 G13

125°C85°C25°C–40°C



LTC6561

6Rev. B





PSRR Out to VCCI, VCCOCh to Ch Isolation vs Frequency Over Temperature

O_MUX Isolation vs Frequency Over Temperature

FREQUENCY (MHz)0.1 1 10 100 500

0

2

4

6

8

10

12

14

16

6561 G15

INPU

T–RE

FERR

ED N

OISE

DEN

SITY

(pA/

√Hz) 125°C

85°C25°C–40°C

125°C85°C25°C–40°C


FREQUENCY (MHz)0 50 100 150 200 250 300

0102030405060708090

100110120130140

INTE

GRAT

ED IN

PUT

REFE

RRED

NOI

SE (n

A RM

S)

6561 G16

FREQUENCY (MHz)0.1 1 10 100 500

0

2

4

6

8

10

12

14

16

6561 G17

INPU

T–RE

FERR

ED N

OISE

DEN

SITY

(pA/

√Hz) 125°C

85°C25°C–40°C

125°C85°C25°C–40°C


FREQUENCY (MHz)0 50 100 150 200 250 300

0102030405060708090

100110120130140

INTE

GRAT

ED IN

PUT

REFE

RRED

NOI

SE (n

A RM

S)

6561 G18

PSRR VCCIPSRR VCCO

FREQUENCY (MHz)1 400 800 1200 1600 2000

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

POW

ER S

UPPL

Y RE

JECT

ION

RATI

O (d

B)

6561 G19

ANY SELECTED CHANNEL TO ANY UNSELECTED CHANNEL

FREQUENCY (MHz)0 200 400 600 800 1000

0

10

20

30

40

50

60

70

MAG

NITU

DE IS

OLAT

ION

(dB)

6561 G20

125°C85°C25°C–40°C

FREQUENCY (MHz)0 200 400 600 800 1000

0

20

40

60

80

100

MAG

NITU

DE IS

OLAT

ION

(dB)

6561 G21

ANY INPUT TO OUTPUT WHEN O_MUX = HI

125°C85°C25°C–40°C





LTC6561

7Rev. B


S21(Gain) vs Frequency Over Temperature

Stability Factor K vs Frequency Over Temperature

S22 vs Frequency Over Temperature








FREQUENCY (MHz)0 200 400 600 800 1000

–40

–30

–20

–10

0

10

20

30

MAG

NITU

DE S

21 (d

B)

6561 G22

CIN,TOT = 0.5pF

125°C85°C25°C–40°C

125°C85°C25°C–40°C

CIN,TOT = 0.5pF

FREQUENCY (MHz)0 200 400 600 800 1000

–40

–30

–20

–10

0

MAG

NITU

DE S

21 (d

B)

6561 G23

UnconditionallyStable

Potentiallyunstable

FREQUENCY (MHz)0 200 400 600 800 1000

0

1

2

3

4

5

6

7

6561 G24

UNCONDITIONALLYSTABLE

POTENTIALLYUNSTABLE

CIN,TOT = 0.5pF

MAG

NITU

DE K

(UNI

TLES

S)

125°C85°C25°C–40°C

FREQUENCY (MHz)0 200 400 600 800 1000

–40

–30

–20

–10

0

10

20

30

MAG

NITU

DE S

21 (d

B)

6561 G25

CIN,TOT = 2pF

125°C85°C25°C–40°C

125°C85°C25°C–40°C

CIN,TOT = 2pF

FREQUENCY (MHz)0 200 400 600 800 1000

–40

–30

–20

–10

0

MAG

NITU

DE S

21 (d

B)

6561 G26

125°C85°C25°C–40°C

CIN,TOT = 4pF

FREQUENCY (MHz)0 200 400 600 800 1000

–40

–30

–20

–10

0

MAG

NITU

DE S

21 (d

B)

6561 G29


POTENTIALLYUNSTABLE

FREQUENCY (MHz)0 200 400 600 800 1000

0

1

2

3

4

5

6

7

MAG

NITU

DE K

(UNI

TLES

S)

6561 G27

CIN,TOT = 2pF125°C85°C25°C–40°C

CIN,TOT = 4pF

FREQUENCY (MHz)0 200 400 600 800 1000

0

1

2

3

4

5

6

7

6561 G30


POTENTIALLYUNSTABLE

MAG

NITU

DE K

(UNI

TLES

S)

125°C85°C25°C–40°C

FREQUENCY (MHz)0 200 400 600 800 1000

–40

–30

–20

–10

0

10

20

30

MAG

NITU

DE S

21 (d

B)

6561 G28

CIN,TOT = 4pF

125°C85°C25°C–40°C



LTC6561

8Rev. B


O_MUX Switching Time DC Coupled Input

Pulse Response Overload Region (1mA)

Pulse Response Linear Range (20µA)

Channel Select Switching Time DC Coupled Input

Pulse Response Overload Region (40µA)

Pulse Response Linear Range (2.5µA)

READY IN LESS THAN 30ns

OPTICAL PULSE–INJECTED30ns AFTER CHSEL

SWITCHINGGLITCH

50ns/DIV

OUTPUT 0.5V/DIV

CHSELUNSELECT–>SELECT

6561 G35

5ns/DIV6561 G33

OUTPUT RESPONSE0.5V/DIV

INPUT PULSE20µA/DIV


5ns/DIV6561 G31


INPUT PULSE1µA/DIV


O_MUX OUTPUTGLITCH

5ns/DIV6561 G36

SETTLED IN LESS THAN 25ns

OUTPUT1V/DIV

O_MUXDISABLED–>ENABLED

5ns/DIV


INPUT PULSE0.5mA/DIV

6561 G34


5ns/DIV6561 G32


INPUT PULSE10µA/DIV




LTC6561

9Rev. B


Pulse Width vs ADP Current Optical Measurement

Pulse Stretching CIN = 2.0pF, Using FWHM



y = 10.5x + 2.0CIN = 4.0pF

USING FULL WIDTH = HALF MAX.TO DETERMINE OUTPUT PULSE WIDTH

125°C85°C25°C–40°CCURVE FIT

INPUT CURRENT (mA)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0123456789

10111213141516

PULS

E ST

RETC

HING

(nS)

6561 G42

USING FULL WIDTH = HALF MAX.TO DETERMINE OUTPUT PULSE WIDTHy = 5.1x + 2.0CIN = 0.5pF

INPUT CURRENT (mA)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0123456789

10111213141516

PULS

E ST

RETC

HING

(nS)

6561 G40


APD CAP APPROXIMATELY 4pF

APD CURRENT (mA)0 2 4 6 8 10

0102030405060708090

100110120130140150

PULS

E W

IDTH

(nS)

6561 G43



INPUT CURRENT (mA)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0123456789

10111213141516

PULS

E ST

RETC

HING

(nS)

6561 G41

O_MUX and Channel Switching Time for AC Coupled Input

Channel Switching Glitch AC Coupled Input, 10pF

Channel Switching Glitch AC Coupled Input, 100pF

RC = 12kΩ • INPUT CAP

INPUT CAPACITOR VALUE (pF)1 10 100 1000 1E4 1E5

1

10

100

1000

1E4

1E5

1E6

SWIT

CHIN

G TI

ME

(ns)

6561 G37

MIN. MEASURED SWITCHING TIMERC MODELED

CHANNEL SELECT GLITCH

INPUT COUPLINGCAP = 10pF

TIME (ns)0 100 200 300 400 500

0

0.25

0.50

0.75

1.00

1.25

AMPL

ITUD

E (V

)

6561 G39

CHSELOUT



0 400 800 1200 1600 20000

0.25

0.50

0.75

1.00

1.25

AMPL

ITUD

E (V

)

6561 G39TIME (ns)

CHSELOUT



LTC6561

10Rev. B


PIN FUNCTIONSVCCO (Pins 1, 18): Positive Power Supply for the output stage. Typically 5V. VCCO can be tied to VCC1 or VCC2 for single supply operation. Bypass capacitors of 1000pF and 0.1µF should be placed as close as possible between VCCO and ground. Both VCCO pins are internally tied together.

CHSEL0 (Pin 2): LSB for Channel Selection. CMOS input. The CHSEL0 pin has a 29kΩ internal pull-down resistor. Default value is 0V.

VCC1, VCC2 (Pins 3, 16): Positive Power Supply. Typically 5V. Bypass capacitors of 1000pF and 0.1µF should be placed as close as possible between VCC1,2 and ground. VCC1 (Pin 3) and VCC2 (Pin 16) are internally tied together.

VREF1, VREF2, VREF3, VREF4 (Pins 4, 9, 10, 15): Reference Voltage Pins for Transimpedance Amplifier for Channels 1, 2, 3, and 4 Respectively. This pin sets the input volt-age for each transimpedance amplifier. The VREF pin has a Thevenin equivalent resistance of approximately 1.4k and can be overdriven by an external voltage. If no volt-age is applied to VREF, it will float to a default voltage of approximately 1.55V on a 5V supply. Each VREF pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.1µF. The bypass cap should be located close to its VREF pin.

GND(Pins 5,8,11,14,21,22,Exposed Pad Pin 25): Negative Power Supply. Normally tied to ground. All GND pins and the exposed pad must be tied to the same

voltage. The exposed pad (pin 25) should have multiple via holes to underlying ground plane for low inductance and good heat transfer.

IN1, IN2, IN3, IN4 (Pin 6, 7, 12, 13): Input Pin for Transimpedance Amplifier for Channels 1, 2, 3, and 4 respectively. This pin is internally biased to 1.55V. See the Applications section for specific recommendations.

O_MUX(Pin 17): Output MUX is a digital input control-ling the output multiplexing function. The pin is functional when multiple LTC6561s are combined at the output. When O_MUX is low, the output is enabled. When O_MUX is high, all 4 inputs are decoupled from the output. Its default value is 0V. This MUX pin is ineffective effect unless a 2nd LTC6561 is DC-coupled at the output. See Applications section on how to use O_MUX to expand the channel count with multiple LTC6561s. The O_MUX pin has a 29kΩ internal pull-down resistor.

DNC(Pin 19): No Connection. Do not connect.

OUTTERM (Pin 20): TIA Output with an Internal Series 50Ω Resistor.

OUT (Pin 23): TIA Output without an internal series 50Ω

CHSEL1 (Pins 24): MSB for Channel Selection. CMOS input. The CHSEL1 pin has a 29kΩ internal pull-down resistor. Default value is 0V.



LTC6561

11Rev. B


BLOCK DIAGRAM

6561 BD

VCCO

CHSEL0,1 O_MUX

OUT

47.5Ω

VCC1,2

GND

IN1

VREF1

TIA

4:1MUX

GAIN

OUTTERM

OUTPUTSTAGE

IN2

VREF2

TIA

IN3

VREF3

TIA

IN4

VREF4

TIA



LTC6561

12Rev. B


OPERATIONThe LTC6561 is a four channel transimpedance amplifier (TIA) with an integrated 4-to-1 multiplexer. Each of the transimpedance amplifiers converts an input current to an output voltage. The integrated multiplexer simplifies the system design while saving space and power. In addi-tion, the Output Multiplexer capability (O_MUX) allows multiple 4-channel LTC6561 devices to be combined. 8, 12, 16 or 32 input channels are easily multiplexed into a single output.

In typical LIDAR applications, the LTC6561 amplifies the output current of an APD. APD are biased near breakdown to achieve high current gain Under intense optical illumi-nation they can conduct large currents, often in excess of 1A. The LTC6561 survives and quickly recovers from large overload currents of this magnitude. During recover, any TIA is blinded from subsequent pulses. The LTC6561 recovers from 1mA saturation events in less than 12ns without phase reversal, minimizing this form of data loss. As the level of input current exceeds the linear range, the output pulse width will widen. However, the recovery time remains in the 10’s of ns. See Figure 7b and Figure 8a plots of pulse stretching versus input current.

Internally the LTC6561 consists of multiple stages. The first stage is a transimpedance amplifier. A second voltage gain stage leads to a final output buffer that can drive a 2VP-P swing on a 100Ω load.

To increase the LIDAR’s spatial resolution many APDs are deployed, often in an array. To achieve maximum bandwidth each APD pixel must have a dedicated TIA as increasing CIN will reduce bandwidth. The LTC6561 multiplexing capability allows compact multichannel designs without external multiplexers. The use of multiple LTC6561’s works well with an APD array to minimize trace capacitance and solution size.

Channel SelectionCHSEL1 CHSEL0 O_MUX ACTIVE CHANNEL

0 0 0 1

0 1 0 2

1 0 0 3

1 1 0 4

X X 1 High Z

6561 F01

VCCO

CHSEL0,1 O_MUX

47.5Ω

OUT

LTC6561VCC1,2

GND

IN1

VREF1

IN2

VREF2

IN3

VREF3

IN4

TIA

APD ARRAY TIA

TIA

TIA

VREF4

4:1MUX GAIN

OUTTERM

OUTPUTSTAGE

–150V

+

–

47.5Ω

50Ω


Figure 1. Typical Application with DC-Coupled Inputs Driving a TDC with Back-Terminated Cable



LTC6561

13Rev. B


APPLICATIONS INFORMATION

PCB Layout

The LTC6561 has separate supply pins for input (VCC1,2) and output (VCCO). VCC1 (Pin 3) and VCC2 (Pin 16) are internally tied together. VCC0 pins (Pins 1 and 18) are internally tied together as well. Duplicate supply pins are provided to ease layout. One set of supply pins should be bypassed with 1000pF and 0.1µF capacitors to ground. For best operation, the output and input supplies should be set to the same voltage.

At each VREF pin the LTC6561 has small internal bypass capacitors connected between pin and ground to ensure low input noise. For the lowest possible input noise, the VREF pin at each TIA should be bypassed with a high qual-ity 1000pF ceramic capacitor to ground. This bypass cap should be located physically close to each VREF pin and far from input pins to avoid unintentional coupling to the output.

Output Considerations

The LTC6561’s output stage is a low impedance driver. When using the OUT pin, a series 47.5Ω resistor must be added to match to 50Ω transmission lines and equipment. If the OUTTERM pin is utilized, the 47.5Ω resistor is inter-nal and no external component is needed. Only one of the outputs should be utilized at a time. At the single ended output, the resting voltage is approximately 1.0V. Loaded

with 100Ω or higher load, the output can swing to 3V. This is equivalent to a 2VP-P swing. If loaded with 50Ω, only a 1VP-P swing is possible since half of the voltage is dropped across the series output resistor. The output must be terminated with a low impedance load <400Ω. If the output is measured directly into a high impedance oscilloscope, the output falling edge will be distorted as the LTC6561 has limited ability to sink current. When monitoring the output, be sure to set the oscilloscope’s input termination to 50Ω.

Input Considerations AC- or DC-Coupling

Input coupling the APD to the TIA is a critical design aspect with many trade-offs to consider. The DC coupled input is the simplest, requiring minimal components to directly couple the APD to the TIA. In the DC case switch-ing times are fast <50nS and saturation recovery times are minimized. However, DC coupling allows APD dark current, and ambient light components to leak through. These DC components can diminish the TIA’s dynamic range. DC current cancellation can be used to restore the TIA’s dynamic range by injecting current at the TIA input to offset the APD’s DC current component. Care must be taken at the TIA’s input as current injection can also inject noise.

The AC coupled input case will block all DC inputs, preserving the TIA’s full dynamic range. See Figure 3.



6561 F02

VCCO

47.5Ω

50Ω

CHSEL1,0 O_MUX

O_MUX(2)

OUT

LTC6561VCC1,2

GND

IN1

VREF1

IN2

VREF2

IN3

VREF3

IN4

TIA

TIA

TIA

TIA

VREF4

4:1MUX

GAIN

OUTTERM

OUTPUTSTAGE


APD ARRAY–150V

+

–

Figure 2. Typical Application with Multiplexed Output



LTC6561

14Rev. B



However, switching times will be affected depending on the choice of AC coupling capacitor. When a channel is switched from inactive to active using either the CHSEL or O_MUX control, a glitch will appear at the output. (See Figure 5 and Figure 6) The TIA will not be ready for a desired input pulse until the glitch has settled. The glitch settling time is dependent upon the AC coupling capacitor value. The value of the AC coupling cap must be carefully considered. A plot of switching times vs. coupling capaci-tor is shown in Figure 4.

Figure 4.

RC = 12kΩ • INPUT CAP

INPUT CAPACITOR VALUE (pF)1 10 100 1000 1E4 1E5

1

10

100

1000

1E4

1E5

1E6

SWIT

CHIN

G TI

ME

(ns)

6561 F04

MIN. MEASURED SWITCHING TIMERC MODELED

AC Switching Times

To maximize dynamic range, the LTC6561’s input is lim-ited to negative current pulses (current flowing out of the LTC6561). When using a negatively biased APD, the TIA input can be AC or DC coupled to the APD cathode.

When using a positively biased APD, the input must be AC coupled off of the APD’s anode.

Figure 5.



TIME (ns)0 100 200 300 400 500

0

0.25

0.50

0.75

1.00

1.25AM

PLIT

UDE

(V)

6561 F05

CHSELOUT

Switching Glitch 10pF

Figure 6.



0 400 800 1200 1600 20000

0.25

0.50

0.75

1.00

1.25

AMPL

ITUD

E (V

)

6561 F06TIME (ns)

CHSELOUT

Switching Glitch 100pF

50Ω WIRE-ORMUXOUT(2)

MULTIPLE LTC6561s

6561 F03

VCCO

50Ω

50Ω

CHSEL1,0 O_MUX

O_MUX(2)

OUT

LTC6561VCC1,2

GND

IN1

VREF1

IN2

VREF2

IN3

VREF3

IN4

TIA

TIA

TIA

TIA

VREF4

4:1MUX

GAIN

OUTTERM

OUTPUTSTAGE


APD ARRAY150V

+

–

1nF

1nF

1nF

1nF

10k10k10k10k

Figure 3. Typical Application with Multiplexed Output



LTC6561

15Rev. B


APPLICATIONS INFORMATIONCoupling the APD to the TIA is critical, direct DC coupling or AC coupling, using a small AC coupling capacitor from 10pF to 100pF is recommended.

Channel Selection

There are four TIA inputs to the LTC6561. The active channel is selected using the two channel selection bits CHSEL0 and CHSEL1. When a channel is selected, its DC input voltage is approximately 1.5V; when deselected its input voltage drops to 0.9V. A reselected channel will not be active until its AC-coupling cap is recharged to 1.5V, leading to slow switching times. With a large AC-coupling cap, switching time can stretch into the µS range. When DC- coupled, the LTC6561 will switch channels in less than 50nS. Inactive channels have more than 45dB of isolation to the active channel to prevent cross-talk. It is critical to route adjacent channel input lines with ground isolation between them to minimize channel to channel coupling.

Output MUXing

The Output MUX (O_MUX) requires at least one additional LTC6561 devices to operate in a master/slave relationship. To MUX multiple LTC6561’s they need to share a DC connection at their outputs. One LTC6561 output must be selected at all times by asserting its O_MUX pin low. To disable the rest of the outputs, drive the other O_MUX pins high. The chosen LTC6561 effectively commands the others. It is recommended to DC couple the outputs after the series 40-50Ω resistor as this will limit reflection from unselected outputs. At least one LTC6561 output must be selected at all times.

In its default mode O_MUX is low, so the LTC6561 out-put is enabled. Obviously, if there is only one LTC6561, then setting the O_MUX pin high will not MUX anything, however the output will be isolated from all the inputs.

Input Capacitance

As with most TIAs, bandwidth and rise time of the output pulse are a strong function of the input capacitance. To receive narrow pulses, a low capacitance APD sensor is recommended. As well, trace capacitance and parasitic pad capacitance should be minimized at the input. All

LTC6561 plots reference CIN,TOT which is the total input capacitance including APD sensor, trace routing and para-sitics. The LTC6561’s MUX capability allows short input coupling to individual APDs and a more compact solution size for APD arrays.

Internal protection circuitry at each TIA input can protect the LTC6561 even under strong overdrive conditions. Most application circuits will not need external protec-tion diodes which add to the total input capacitance and slow the rise time. Output rise time can be estimated from the amplifier bandwidth using the following relationship:

RISETIME =

0.35BW

ADP Biasing

Proper APD biasing is key to producing a high fidelity output and protecting both the APD and TIA. As suggested earlier a negatively biased APD provides the lowest input capacitance and allows the APD to be DC coupled to the TIA. To keep the optical gain stable the APD bias should be temperature compensated. Quenching resistors in series are required to limit the maximum current, thereby pro-tecting the APD and TIA from damage. An example of a typical APD bias network is shown in Figure 9. Starting at the Negative bias input, two physically large 10kW resis-tors can dissipate the maximum pulse power. They are decoupled with a 1nF capacitor. Moving towards the APD, a second smaller quenching resistor 50Ω is decoupled by two 0.047µF capacitors. This smaller quenching resistor acts to dampen ringing especially under high slew rates due to large optical inputs pulses. All capacitors must be rated for high voltage as APD bias voltages can run above 200V.

Dramatically Improving the LTC6561’s Dynamic Range

While the LTC6561’s 30µA of linear input range is quite respectable, it is possible to dramatically improve the range over which input current can be accurately mea-sured. The measurement range can be increased from 30µA to at least 3mA, a 100x improvement in current measurement range! As the input current exceeds the linear range, the output pulse amplitude saturates. Once



LTC6561

16Rev. B


APPLICATIONS INFORMATIONin saturation, the pulse width widens in a predictable man-ner. Pulse stretching is a function of input capacitance, but fortunately insensitive to temperature.

This behavior is demonstrated using the FT2563 evalua-tion board. This evaluation board uses a series 2k resistor to convert a voltage pulse to a current pulse as it is dif-ficult to obtain a fast current pulse generator. The input is terminated in 50Ω so that current pulses of known quan-tity are generated at the TIA input using a voltage source. Sweeping the TIA pulse input current from 2.8µA to 3mA, we see that as the current surpasses the 30µA saturation point, the output pulse width increases (Figure 7b).

Figure 7a.

INJ1

R2100Ω

R3100Ω

R12k

TIA

C10.1µF

C2OPT

25V 0603

6561 F03a

Figure 7b.

2.8µA

79µA

14µA29µA155µA

1mA3mA

WITH SERIES 50Ω, INTO 50Ω LOAD

10ns/DIV

PULSE AMPLITUDE

(200mV/DIV)

6561 G03b

Output Pulse Over Input Current

When we plot the pulse stretching (output response width – input pulse width), we see that the stretching is linearly proportional to the input current. Below, the saturation point of 30µA the pulse stretching falls to zero. Here we have used the simple FWHM (full width half max) criteria to establish the pulse width. The pulse width is taken at half of the maximum swing, usually around 0.45V. A more sophisticated algorithm could be used to gain greater accuracy assuming the pulse shape is accurately

captured by an ADC. A plot of pulse stretching vs input current with CIN = 0.5pF is shown in Figure 8a. Figure 8b shows pulse stretching with 4pF on input capacitance. current range in.

Figure 8a.


INPUT CURRENT (mA)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0123456789

10111213141516

PULS

E ST

RETC

HING

(nS)

6561 F08a



Figure 8b.

y = 10.5x + 2.0CIN = 4.0pF

USING FULL WIDTH = HALF MAX.TO DETERMINE OUTPUT PULSE WIDTH


INPUT CURRENT (mA)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0123456789

10111213141516

PULS

E ST

RETC

HING

(nS)

6561 F08b

Pulse Stretching CIN = 4pF, Using FWHM

The same pulse stretching has been demonstrated using optical excitation. Independently measuring the current generated during an optical pulse impinging on an APD is quite difficult. The parasitics of any measuring device will impair the actual pulse input. Refer to Figure 9. Using a balun across series resistor R48 feeding the APD, we can get an independent determination of APD current to the TIA for moderate laser input powers. Again, when this APD current is plotted versus pulse stretching, we find a nearly linear relationship under moderate illumination.



LTC6561

17Rev. B


U3R4850Ω1204

R4710k

1206

R7510k

1206

C450.047µF1206300V

C700.047µF1206300V

C461nF12061 2

3

4

5

2

3

4

5

6

7

8

GR

6

7

8

APD-ARRAY

E8HOLE FOR –300V

HOLE FOR GND

6561 F05a

E11

Using a calibrated laser source, we find that pulse stretch-ing continues even at extremely high laser power levels of 50 Watts! At high illumination levels, the relationship no longer appears perfectly linear, but the potential to measure these high power levels is possible. Of course, with any system, a calibration of optical input power to pulse stretching should be done as the optical gain is a strong function of the APD reverse bias, temperature and the choice of APD.

Pulse Width vs APD Current Optical Measurement

APD CURRENT (µA)0 2000 4000 6000 8000 10000

0102030405060708090

100110120130140150

PULS

E W

IDTH

(nS)

6561 F05b


TIME (µsec)0 1 2 3 4

0.0

0.2

0.4

0.6

0.8

1.0

1.2

PULS

E AM

PLIT

UDE

(V)

6561 F06

5µW5mW

5W50W

507µW

Figure 10. Pulse Width vs Input Hi Power Optical

Figure 9. Typical APD Bias Circuit



LTC6561

18Rev. B


APPLICATIONS INFORMATIONDC2849 4-Channel Demonstration Circuit for Optical Evaluation

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NOTE: UNLESS OTHERWISE SPECIFIED1. ALL RESISTORS ARE IN OHMS, 0402 ALL CAPACITORS ARE IN MICROFARADS, 0402

PCA ADDITIONAL PARTS

VCC

VCC

VCC VCC0

VCC0

VCC

VCC

VCC

APD1

APD2

APD3

APD4

DATE:

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TITLE: DEMO CIRCUIT SCHEMATIC,

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CUSTOMER NOTICEANALOG DEVISES HAS MADE A BEST EFFORT TO DESIGN ACIRCUIT THAT MEETS CUSTOMER-SUPPLIEDSPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'SRESPONSIBILITY TO VERIFY PROPER AND RELIABLEOPERATION IN THE ACTUAL APPLICATION. COMPONENTSUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAYSIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE ORRELIABILITY. CONTACT ANALOG DEVICES APPLICATIONS ENGINEERING FOR ASSISTANCE.

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DC2849A700-DC2849A_REV02

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DC2849A700-DC2849A_REV02

710-DC2849A_REV 02705-DC2849A_REV02N/A

R18 1k

J5O_MUXDNI

1

JP4O_MUXDISEN

1

2

3

R19 1k

C31uF0603

C13 1000pF

MP1 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)

C11 OPT

PCB1 PCB, DC2849A REV0x

R17 1k

C15 1000pF

LB1 LABELMP4 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)

R5 47.5

JP2

CHSEL0

01

1

2

3

R6 OPT

J3OUT1

R3OPT

J2CHSEL1

DNI

1

E1VCC

C10 1000pF

E3GND

Z1CLL4734A5.6V

1

2

C410uF0805

R1OPT

C16 OPT

C6 1000pF

U1LTC6561-UF

VCCO

1CH

SELO

2VC

C13

VREF

14

GND

5IN1

6

IN27

GND8

VREF29

VREF310

GND11

IN312

IN4

13

GND

14

VREF

415

VCC2

16

O_MU

X17

VCC0

18

NC 19OUTTERM 20

GND 21GND 22OUT 23

CHSEL1 24

GND 25

C210.1uF

C5 0.1uF


R9OPT

C191000pF

J4OUTTERMDNI

1

C18 OPT

C14 0.1uF

JP1VCC0_SELVCC EXT

1

2

3

C9 1000pF

C7 0.1uF

E4GND

JP3

CHSEL1

01

1

2

3

J1CHSEL0DNI

1

C20 1000pF


C23 1000pF

STNCL1 TOOL, STENCIL, 700-DC2849A REV0x

R4 0

R7 0

C24 0.1uF

R8 0

E2VCC0

C110uF0805

C21uF0603

R2 0

DC2849 Front Side DC2849 Back Side



LTC6561

19Rev. B


APPLICATIONS INFORMATIONDC2808 4-Channel Demonstration Circuit for Electrical Evaluation

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


PCA ADDITIONAL PARTS

VCC

VCC

VCC VCC0

VCC0

VCC

VCC

VCC

DATE:

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SHEET OF


APPROVALSPCB DES.

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CUSTOMER NOTICELINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN ACIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TOVERIFY PROPER AND RELIABLE OPERATION IN THE ACTUALAPPLICATION. COMPONENT SUBSTITUTION AND PRINTEDCIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUITPERFORMANCE OR RELIABILITY. CONTACT LINEARTECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY ANDSUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONESIZE:


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DC2808A700-DC2808A_REV03

710-DC2808A_REV03705-DC2808A_REV03N/A

<Variant Name>

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DC2808A700-DC2808A_REV03

710-DC2808A_REV03705-DC2808A_REV03N/A

<Variant Name>

C12OPT

R28 1k

C31uF0603

JP4

O_MIXDISEN

1

2

3

R7100

C10 1000pF

C15 1000pF

R5 2k


C7 0.1uF

C17 1000pF

LB1 LABEL

U1LTC6561-UF

VCCO

1CH

SELO

2VC

C13

VREF

14

GND

5IN1

6

IN27

GND8

VREF29

VREF310

GND11

IN312

IN4

13

GND

14

VREF

415

VCC2

16

O_MU

X17

VCC0

18

NC 19OUTTERM 20

GND 21GND 22OUT 23

CHSEL1 24

GND 25

C27 0.1uF25V0603


R9 47.5

C19 0.1uF

R18100

J4IN4 1 C30 0.1uF

25V0603

J7OUT1

J1IN1 1

R14100

J3IN3 1

C14 0.1uF

E1VCC

C11 1000pF

E3GND

C29 0.1uF25V0603

R20OPT

Z1CLL4734A5.6V

1

2

C8 0.1uF

C410uF0805

R10 OPT

C6 1000pF

R3100

PCB1 PCB, DC2808A REV03

R22OPT

R23OPT

C5 0.1uF


R27 1k

JP3

CHSEL110

1

2

3

C28 0.1uF25V0603

R8100

J2IN2 1

J8OUTTERM

DNI

1

R29 1k

JP1

VCC0_SELVCC EXT

1

2

3

C16 0.1uF

R21 OPT

C24OPT

STNCL1 TOOL, STENCIL, 700-DC2808A REV03

E4GND

C21OPT

R15 2k

C22 1000pF

R17100

R13100


C25 1000pF

C9OPT

C23 0.1uF

R11 2k

R19OPT

R4100

C26 0.1uF

E2VCC0

JP2

CHSEL010

1

2

3

C110uF0805

C21uF0603

R1 2k

INPUT 1

INPUT 4

+5V GND

INPUT 2

INPUT 4

LOW-NOISE SUPPLY



LTC6561

20Rev. B


APPLICATIONS INFORMATIONFT2724 16-Channel Demonstration Circuit for Optical or Electrical Evaluation

FT2724 Front Side FT2724 Back Side

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


VCC VCC

VCC VCC

VCC

VCC VCC

SIZE

DATE:

IC NO. REV.

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APPROVALS

PCB DES.

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THIS CIRCUIT IS PROPRIETARY TO ANALOG DEVICES AND

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LTC6561IUF

AK

GREG F.

R220

R190

R200

C80.047uF1206500V

C71000pF1206500V

R11 1kR12 1k

U4LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7GN

D8

VREF

29

VREF

310

GND

11IN

312

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

NC19

OUTT

ERM

20

GND

21

GND

22

OUT

23

CHSE

L124

GND

25

CN70.1uF X4

81

72

63

54R18

0

U1LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7

GND

8

VREF

29

VREF

310

GND

11

IN3

12

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

NC19

OUTT

ERM

20GN

D21

GND

22OU

T23

CHSE

L124

GND

25

R7 1k

E3 TMP35

R4 1k

CN10.1uF X4

81

72

63

54

R151001206

R280R32

0

R1310k1206

R260R30

0

R2 1k

R230

U2LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7

GND

8

VREF

29

VREF

310

GND

11

IN3

12

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

NC19

OUTT

ERM

20GN

D21

GND

22OU

T23

CHSE

L124

GND

25

J1

TSW-112-07-L-D

24681012141618202224

13579

11131517192123

R10 1k

U6 TMP35

SOT-23-5

VOUT1

+VS2

NC3

SHUTDOWN4

GND5

CN20.1uF X4

81

72

63

54

J2OUT

E2 GND

R210

C1

1000pF

U3LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7GN

D8

VREF

29

VREF

310

GND

11IN

312

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

NC19

OUTT

ERM

20

GND

21

GND

22

OUT

23

CHSE

L124

GND

25

U5 16AA0.4-9-SMD

C/ANOD1

NC2

C23

C44

C65

C86

C107

C128

C149

C1610

NC11

NC12

NC13

C1514

C1315

C1116

C917

C718

C519

C320

C121

G/RING22

C60.047uF1206500V

C21000pFC51000pF

R9 1k

C41000pF

GND

-300V

J3

NC6-P108-02

1

2

R8 1k

E1 VCC

R6 1kR5 1k

R3 1k

CN80.1uF X4

81

72

63

54R27

0

C3 0.1uF

R310

R1410k1206

R240

R170

R250R29

0

R16 10K0402

R1 1kCS0CS1CS2CS3CS4CS5CS6CS7OS0OS1OS2OS3

OS3 OS0

OS2 OS1 CS2

CS3

CS4

CS5

CS7

CS6

CS1

CS0

APD7APD5APD3APD1

APD16APD14

APD10

APD4

APD8

APD15APD13APD11APD9

APD12

APD6

APD2



LTC6561

21Rev. B


LB2800 16:4 Channel Demonstration Circuit for Optical Evaluation

FT2724 with Switch BoardLB2800 Back SideLB2800 Front Side


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A


VCC VCC

VCC VCC

VCC

VCC

SIZE

DATE:

IC NO. REV.

SHEET OF

TITLE:

APPROVALS

PCB DES.

APP ENG.

Fax: (408)434-0507Phone: (408)432-1900



SCHEMATIC


www.analog.com

ANALOGDEVICES


Milpitas, CA 95035

ADI CONFIDENTIAL - FOR CUSTOMER USE ONLY 2LB2800AFriday, February 16, 2018 1 1

RECEIVER TIA 16:4N/A

LTC6561IUF

AKNOE Q.

SIZE

DATE:

IC NO. REV.

SHEET OF

TITLE:

APPROVALS

PCB DES.

APP ENG.

Fax: (408)434-0507Phone: (408)432-1900



SCHEMATIC


www.analog.com

ANALOGDEVICES


Milpitas, CA 95035



LTC6561IUF

AKNOE Q.

SIZE

DATE:

IC NO. REV.

SHEET OF

TITLE:

APPROVALS

PCB DES.

APP ENG.

Fax: (408)434-0507Phone: (408)432-1900



SCHEMATIC


www.analog.com

ANALOGDEVICES


Milpitas, CA 95035



LTC6561IUF

AKNOE Q.

R19 OPT 0201

R35 1kR36 1kR27 OPT 0201

R34 1k

R25 OPT 0201

R33 1k

C26 0.1uF

C80.047uF1206500V

R40OPT

R8 1k

R11 1k

R38OPT

C71000pF1206500V

R12 1k

R18 OPT 0201

U4LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7GN

D8

VREF

29

VREF

310

GND

11IN

312

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

SHDN

19

OUTT

ERM

20

GND

21

GND

22

OUT

23

CHSE

L124

GND

25

CN71.0uF X4

81

72

63

54

R5 1k

J1OUT31

U1LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7

GND

8

VREF

29

VREF

310

GND

11

IN3

12

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

SHDN

19OU

TTER

M20

GND

21GN

D22

OUT

23CH

SEL1

24GN

D25

E3 TMP35

J6TSW-16-07-L-D

2468

1012141618202224

13579111315171921232526272829303132

R4 1k

CN11.0uF X4

81

72

63

54

R151001206

R23 OPT 0201

R1310k1206

C291uF

040216V

C25 0.1uF

R30 OPT 0201R21 OPT 0201

R2 1k

U2LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7

GND

8

VREF

29

VREF

310

GND

11

IN3

12

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

SHDN

19OU

TTER

M20

GND

21GN

D22

OUT

23CH

SEL1

24GN

D25

U6 TMP35

SOT-23-5

VOUT1

+VS2

NC3

SHUTDOWN4

GND5

R28 OPT 0201

R17 OPT 0201

CN21.0uF X4

81

72

63

54

R9 1k

R26 OPT 0201

E2 GND

C1

1000pF

U3LTC6561IUF-1

VCCO1

CHSEL02

VCC13

VREF14

GND5

IN16

IN2

7GN

D8

VREF

29

VREF

310

GND

11IN

312

IN413

GND14

VREF415

VCC216

O_MUX17

VCCO18

SHDN

19

OUTT

ERM

20

GND

21

GND

22

OUT

23

CHSE

L124

GND

25

C60.047uF1206500V

R39OPT

R7 1k

C21000pFC51000pF

J2OUT1 1

R37OPT

C41000pF

R6 1k

GND

-300V

J5

TERMINAL BLOCKHV-CON-282836-2

1

2

R10 1k

E1 VCC

C3 0.1uF

R20 OPT 0201

C2810uF

120616V

U5 16AA0.4-9-SMD

C/ANOD1

NC2

C23

C44

C65

C86

C107

C128

C149

C1610

NC11

NC12

NC13

C1514

C1315

C1116

C917

C718

C519

C320

C121

G/RING22

R32 OPT 0201

E4 GND

J3OUT41

R24 OPT 0201

R3 1k

R31 OPT 0201

CN81.0uF X4

81

72

63

54

J4OUT2 1 C27 0.1uF

R22 OPT 0201

R1410k1206

R29 OPT 0201

R16 10k0402

R1 1kCS0CS1

CS2CS3

OS3

OS3 OS0

OS2 OS1 CS2

CS3

CS4

CS5

CS7

CS6

CS1

CS0

APD5

CS6CS7

CS4CS5

OS1

OS2

OS0

SD1 SD3

SD3

SD2

SD4SD2

SD1

SD4

APD8APD10APD12

APD16

APD6APD4APD2

APD14

APD1APD3

APD7APD9APD11APD13APD15



LTC6561

22Rev. B


PACKAGE DESCRIPTION

4.00 ±0.10(4 SIDES)

NOTE:1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1TOP MARK(NOTE 6)

0.40 ±0.10

2423

1

2

BOTTOM VIEW—EXPOSED PAD

2.45 ±0.10(4-SIDES)

0.75 ±0.05 R = 0.115TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105 REV B

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.050.50 BSC

2.45 ±0.05(4 SIDES)3.10 ±0.05

4.50 ±0.05

PACKAGE OUTLINE

PIN 1 NOTCHR = 0.20 TYP OR 0.35 × 45° CHAMFER

UF Package24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697 Rev B)



LTC6561

23Rev. B


Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 09/18 Edited DescriptionEdited Absolute Maximum Ratings

12

B 11/18 Added H-Grade option (–40°C to 125°C) All



LTC6561

24Rev. B

For more information www.analog.com © ANALOG DEVICES, INC. 2018

D16964-0-11/18(B)www.analog.com

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PART NUMBER DESCRIPTION COMMENTS

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LTC6268 500MHz Ultra Low Bias Current FET Input Op Amp GBW = 500MHz, –3dB BW = 350MHz, Ib = ±3FA

LTC6268-10 4GHz Ultra Low Bias Current FET Input Op Amp De-Comped Version of the LTC6268, GBW = 4GHz

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GBW = 18MHz, Ib = 0.2pA, 0.1Hz-10Hz, Noise 550nVP-P

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6561 TA02

VCCO

47.5Ω

47.5Ω

CHSEL1,0 O_MUX

O_MUX(2)

OUT

LTC6561VCC1,2

GND

IN1

VREF1

IN2

VREF2

IN3

VREF3

IN4

TIA

TIA

TIA

TIA

VREF4

4:1MUX

GAIN

OUTTERM

OUTPUTSTAGE


APD ARRAY–150V

+

–

Typical Application with Multiplexed Output





https://www.analog.com/LTC6268.html?doc=LTC6561.pdf

https://www.analog.com/LTC6268-10?doc=LTC6561.pdf






https://www.analog.com/ADA4939-1?doc=LTC6561.pdf

https://www.analog.com/AD9694?doc=AD9694

https://www.analog.com/AD9695.html?doc=LTC6561.pdf

https://www.analog.com/HMCAD1511?doc=LTC6561.pdf

ltc6561 four-channel multiplexed transimpedance amplifier ... · gnd in3 order information tube...

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