Thin Solid Films 520 (2012) 3216–3221

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Thin Solid Films

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Low threading dislocation Ge on Si by combining deposition and etching

Yuji Yamamoto a,⁎, Grzegorz Kozlowski a, Peter Zaumseil a, Bernd Tillack a,b

a IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germanyb Technische Universität Berlin, HFT4, Einsteinufer 25, 10587 Berlin, Germany

⁎ Corresponding author. Tel.: +49 335 56 25 156; faE-mail address: yamamoto@ihp-microelectronics.co

0040-6090/$ – see front matter © 2011 Elsevier B.V. Alldoi:10.1016/j.tsf.2011.10.095

a b s t r a c t

a r t i c l e i n f o

Available online 29 October 2011

Keywords:Hetero epitaxyGermaniumChemical vapor depositionAnnealingEtchingDislocation

Blanket and selective Ge growth on Si is investigated using reduced pressure chemical vapor deposition. Toreduce the threading dislocation density (TDD) at low thickness, Ge deposition with cyclic annealing fol-lowed by HCl etching is performed. In the case of blanket Ge deposition, a TDD of 1.3×106 cm−2 is obtained,when the Ge layer is etched back from 4.5 μm thickness to 1.8 μm. The TDD is not increased relative to thesituation before etching. The root mean square of roughness of the 1.8 μm thick Ge is about 0.46 nm, whichis of the same level as before HCl etching. Further etching shows increased surface roughness caused bynon-uniform strain distribution near the interface due to misfit dislocations and threading dislocations.The TDD also becomes higher because the etchfront of Ge reaches areas with high dislocation density nearthe interface. In the case of selective Ge growth, a slightly lower TDD is observed in smaller windows causedby a weak pattern size dependence on Ge thickness. A significant decrease of TDD of selectively grown Ge isalso observed by increasing the Ge thickness. An about 10 times lower TDD at the same Ge thickness is dem-onstrated by applying a combination of deposition and etching processes during selective Ge growth.

© 2011 Elsevier B.V. All rights reserved.

1. Introduction

Heteroepitaxial growth of Ge on Si has generated great interest fordifferent applications such as optoelectronic devices [1] and CMOS tech-nologies [2]. However, 4.2% of lattice mismatch between Ge and Si gen-erates strain in the deposited Ge layer. In reference [3], it is reported thatdue to lattice mismatch, Ge atom adsorption causes local elastic defor-mation near the surface region in initial stages of the Ge layer growthand generates non-uniform local strain distribution. The non-uniformlocal strain distribution causes three-dimensional growth of Ge layer.Therefore, for thick relaxed Ge layer growth a low temperature seedlayer deposition is required to prevent island growth of Ge on Si. Thesurfactant action of hydrogen atoms [4] allows the deposition of two-dimensional Ge layers at low temperature [5]. Due to the lattice mis-match of 4.2% between Ge and Si the critical thickness of a Ge layer onSi surface is limited to several nm. Therefore, it leads to a high densityof misfit dislocations at the interface between Si and Ge and threadingdislocations (TD) in the deposited Ge layer. The TDs in Ge degeneratethe electrical properties (e.g. increase of dark current for optoelectronicsapplications) [6]. Thus low threading dislocation density (TDD) is crucialfor device applications. Various techniques are reported for low TDD Gedeposition such as post thermal cycling annealing [7–9], combinationof low-temperature, high-temperature deposition and annealing [10],cycled epitaxial Ge growth and annealing [11] and cyclic annealing

x: +49 335 56-25 661.m (Y. Yamamoto).

rights reserved.

during Ge growth [12]. Relatively thick layers are required to obtainlowest TDD, because most TDs are located and stay in the Ge layernear the interface. In a previous work, we reported about Ge depositiondirectly on blanket Si with low TDD (~7×105 cm−2) for 4.7 μm thick Geas well as low surface roughness (root mean square (RMS) of roughnessof about 0.45 nm) [12]. Integration of optoelectronics devices with thickGe layer into a CMOS flow could be challenging, because of difficultiesfor interconnections between optoelectronics and CMOS devices dueto a huge step height. Therefore, in this study we used a combinationof Ge deposition and etching to create thick Ge layers first, which arethan etched to realize the desiredfilm thicknesswith lowTDD. The etch-ing processwas investigated for Ge layers deposited onblanket Siwafersas well as for Ge layers deposited in a selective way on patternedwafers. In the case of selective Ge epitaxy (113) facet formation occursafter deposition and annealing. The facets are not removed by the etch-ing process. The potential advantage of this work compared to the com-bination of Ge growth and chemical mechanical polishing is the lowerprocess complexity, because Ge deposition and etching are performedin one reactor without interrupting the process. But this is possibleonly if the Ge layer is very smooth before etching [12]. Otherwise chem-icalmechanical polishing has to be applied to form a smooth surface [8].

2. Experimental details

Epitaxial growth of Ge is carried out using a single wafer reducedpressure (RP) chemical vapor deposition (CVD) system. Non-patternedand with 50 nm thick SiO2 patterned 200 mm Si (100) wafers, whosecoverage of SiO2 is ~97%, are used for blanket and selective Ge growth,

3217Y. Yamamoto et al. / Thin Solid Films 520 (2012) 3216–3221

respectively. After HF last clean, the wafer is baked at 1000 °C or 850 °Cin RP using H2 carrier gas to remove the native oxide for non-patternedand SiO2 patterned Si (100) wafers, respectively. Subsequently the sub-strate is cooled down to 300 °C in RP. To form a hydrogen-free Si surface,the carrier gas is switched from H2 to N2 at 600 °C during the coolingprocess. After the temperature stabilization, about 50 nm thick Ge is de-posited at 300 °C in RP using a GeH4–N2 gas mixture under the sameprocess condition as described in references [12] and [13], becauselow-temperature Ge growth is required to deposit a two-dimensionalGe layer on the Si surface [5,14]. After that the wafer is heated up to550 °C in H2 and the second Ge layer is deposited at 550 °C in RP withH2–GeH4 gasmixture. TheGe growth rates at 300 °C and 550 °C on blan-ket Si wafer are ~2 nm/min and ~20 nm/min, respectively, under stan-dard growth conditions. To minimize the TDD of the Ge layer, severalcycles of annealing (cyclic annealing) are performed in H2 for a fewmi-nutes in RP by interrupting the Ge growth [12]. The interruption is per-formed when the deposited Ge layer reaches a certain thickness.Therefore, more annealing cycles are performed for thicker Ge layer.The cyclic annealing temperature for blanket Ge deposition and selec-tive Ge deposition is 800 °C and 800 °C–860 °C, respectively. After thedeposition, the Ge layers of some samples are etched back by a HCl–H2

gas mixture in RP in the CVD reactor at various temperatures and HClpartial pressures for thinning. Cross section Scanning Electron Micro-scope (SEM) images and step profiler are used for Ge layer thicknessmeasurements. A Hitachi S-4500 SEM operating with an accelerationvoltage of 25 kV is used. A Philips CM 200 transmission electron micro-scope (TEM) operating at 200 kV and Secco defect etching are used forTDD evaluation. All TEM lamellaswere prepared bymechanical grindingand polishing combined with an ion milling process. To achieve reason-able sensitivity for TDD measurement, the process condition of Seccoetching is determined by comparing etch pit density and TDD obtainedby plan-view TEM [12]. A Veeco Digital Instruments Dimension 5000Atomic Force Microscope (AFM) is used for surface roughness analysis.Micro Raman spectroscopy with 633 nm laser wavelength is appliedto characterize the stress distribution of Ge from the surface to thedepth of about 30 nm. All micro-Raman measurements were done onthe InVia Renishaw spectrometer working in the backscattering geome-try. For the stress evaluation, a Ge (100) substrate is used as reference.X-ray diffraction (XRD) is used for characterization of crystallinity. AllXRD measurement are performed by using a SmartLab diffractometerfrom Rigaku equipped with a 9 kW rotating anode Cu source in linefocus geometry, a Ge (400)×2 crystal collimator, and a Ge (220)×2crystal analyzer. Specular ω/2Θ scans as well as ω scans of the Si (004)reflection are measured and combined to reciprocal space maps.

((a)

1.0 1.2 1.4100

101

102

450

500

550600

650

Etch Temp.:(oC)700

PHCl/PH2 : 1x10-2

Etc

h R

ate

(nm

/min

)

1/ x10-3 K-1)T (

Fig. 1. Ge etch rate as a function of (a) reciprocal temperature and (b)

3. Results and discussion

3.1. Blanket Ge growth and etching

An Arrhenius plot of the Ge etch rate for HCl at 450–700 °C and theetch rate as a function of HCl partial pressure are shown in Fig. 1(a)and (b). The Ge etch rate becomes higher with increasing HCl exposuretemperature (Fig. 1(a)). In a temperature region above 550 °C, the tem-perature dependence of the Ge etch rate becomes weaker and a trend ofsaturation is observed. This indicates a higher influence of the HCl masstransport on the Ge etching process. At lower temperature, the temper-ature dependence of the Ge etch rate is higher, which indicates that sur-face reactions havemajor impact on the process limitation of Ge etching.A similar trend is reported and explained as complex reaction mecha-nism in reference [15]. Further investigation is required to clarify thismechanism. At fixed growth temperature of 550 °C (Fig. 1(b)), the Geetch rate is linearly increasing with increasing HCl partial pressure. Forfurther experiments, HCl etching is performed at 550 °C because of bet-ter controllability of Ge etch rate.

Fig. 2 shows the TDD as a function of blanket Ge thickness. In thecase of Ge growth with cyclic annealing (○), the TDD is decreasingwith increasing Ge thickness and a value of about 7×105 cm−2 isachieved for 4.7 μm thick Ge [12]. A similar trend is also reported in ref-erences [8] and [16]. Compared to the postannealing process, a furtherreduction of TDD from 8×106 cm−2 to 7×105 cm−2 and no degrada-tion of surface roughness is obtained for 4.7 μm thick Ge by cyclicannealing [12]. Substrate bowing of ~350 μm is observed for 4.7 μmthick Ge deposited samples due to tensile strain caused by differencesof the thermal expansion coefficients of Si and Ge. This bending is notresulting in slips and cracks. Combining 4.5 μm thick Ge depositionand etching processes (□), the level of TDD is lower compared to theTDD of Ge layers of the same thickness deposited by cyclic annealingprocess. For example the TDD is reduced to 1.3×106 cm−2 for a samplethat was thinned to 1.8 μm, which is about one order of magnitudelower compared to deposited samples without etching. If the Ge layeris thinned further the TDD is increasing, but it is still lower than theTDD measured for Ge layers obtained by deposition only. During thethick Ge layer depositionwith cyclic annealing, migration of TDs occurs.A model of thickness dependence for the strain-relaxed Ge is reportedin reference[16]. In this paper, interaction of neighboring TDs is consid-ered as the driving force for TDs separation and following for reducedenergy states in relaxed layers [16]. With increasing Ge thickness, thestrain distribution near the surface region becomes more uniform andthe separation of TDs by migration occurs with less impact on external

0 4 8 120

100

200

300

400Etch Temp.: 550oC

Etc

h R

ate

(nm

/min

)

b)

PHCl / PH2 (x10-2)

HCl partial pressure. HCl etching is performed at reduced pressure.

0 1 2 3 4 5105

106

107

108

109

Cyc. Anl. Temp.: 800oC

Ge Grown with Cyc. Anl.

TD

D (

cm-2

)

Etch after 4.5 m Ge Depo.

Ge Thickness ( m)

Fig. 2. TDD as a function of Ge thickness. Blanket Ge is deposited. (○) shows the Gesample deposited with cyclic annealing process and (□) shows the sample with Ge de-position (4.5 μm) and etching. Cyclic annealing temperature is 800 °C.

3218 Y. Yamamoto et al. / Thin Solid Films 520 (2012) 3216–3221

strain energy. It seems that the density of TDs in the Ge layer near theinterface is also reduced due to migration of TDs in Ge layers depositedabove by cyclic annealing. Combining the growth of thickGe layerswith

(a)

(c)10 nm

5 nm

0 nm

RMS: 0.41nm

TDD: 1.1×106cm-2

RMS: 0.83nm

TDD: 5.5×106cm-2

<110> 2µm

<110> 2µm

10 nm

5 nm

0 nm

Fig. 3. AFM images of a sample after blanket Ge growth with cyclic annealing (a) and follo500 nm, respectively. b110> directions are shown by arrows.

subsequent HCl etching, makes it possible to take advantage of the lowTDD of thick Ge layers and to create the desired film thickness byetching.

AFM images of blanket Ge surfaces before and after etching areshown in Fig. 3(a)–(d). For the sample before HCl etching (Fig. 3(a))clear cross hatch patterns are visible. The RMS of roughness isabout 0.41 nm, which is in the range of values reported in [12]. Thestep height of the Ge (100) terrace is ~0.2 nm, which is about twicethe atomic-layer height of Ge (100) [8,12]. The surface TDD of theGe measured by Secco etching is 1.1×106 cm−2. In the case of thesample etched from 4.5 μm thickness down to 1.8 μm (Fig. 3(b)),the cross hatch pattern is smeared out. The Ge (100) terraces of dou-ble atomic-layer height are still remaining. The RMS of roughness isabout 0.46 nm and the TDD is 1.3×106 cm−2, which is comparableto the situation before HCl etching. By etching further to 1.3 μmand 500 nm (Fig. 3(c) and (d)), the cross hatch patterns are pro-nounced and the RMS of roughness increases to 0.83 nm and1.36 nm, respectively. The Ge (100) terraces of double atomic-layerheight are still visible even for the 500 nm thick Ge sample with asignificantly roughened surface. The TDD increases also to5.5×106 cm−2 and 8.2×107 cm−2, respectively. But as shown inFig. 2, the TDD is one order of magnitude lower compared to the con-ventional cyclic annealing process without etching. Even though theTDDs are 5.5×106 cm−2 and 8.2×107 cm−2 in Fig. 3(c) and (d), noreversed pyramid shape etch pits caused by the HCl etching asreported in reference [17] are observed. The reason for this differ-ence could be the different process conditions for HCl etching.

(b)

(d)

10 nm

5 nm

0 nm

RMS: 0.46nm

TDD: 1.3×106cm-2

<110> 2µm

10 nm

5 nm

0 nm

RMS: 1.36nm

TDD: 8.2×107cm-2

<110> 2µm

wed by etching (b)–(d). Ge thicknesses are (a) 4.5 μm, (b) 1.8 μm, (c) 1.3 μm and (d)

3219Y. Yamamoto et al. / Thin Solid Films 520 (2012) 3216–3221

To clarify the reason for the increase of surface roughness by HCletching especially for 1.3 μm and 500 nm thick Ge, stress distributionimages of micro Raman spectroscopy are shown in Fig. 4(a)–(d). Theaverage value of Raman peak shift of all samples of Fig. 4(a)–(d) relativeto the peak of the reference Ge (100) substrate was about 0.8 cm−1.This indicates that the Ge layers are slightly tensile strained. The tensilestrain is caused by differences of the thermal expansion coefficient be-tween Si and Ge [8,12]. Since the highest temperature of Ge depositionwith cyclic annealing and HCl etching process is 800 °C for all samples,the degree of strain in the Ge layer is in the same range for all samples. AGe sample before HCl etching does not show any cross hatch pattern ofstrain (Fig. 4(a)). After etching back to 1.8 μm thick Ge, a very weakcross hatch pattern is visible in the strain distribution. After furtheretching, the cross hatch pattern of strain becomes clearer and denser,which indicates a higher strain deviation in the Ge layer near the inter-face. The non-uniform strain distribution could be caused by secondarydislocations formed due to annihilation of TDs above themisfit disloca-tions at the Ge/Si interface. The possible reason for the increase of sur-face roughness by HCl etching is a fluctuation of the etch rate due tothe non-uniform cross hatch strain distribution in the Ge layer nearthe interface.

In order to discuss the crystallinity of the Ge layer in detail, XRD re-ciprocal mapping scan around the Si (400) and Ge (400) peaks areshown for a 4.5 μm thick Ge sample deposited by cyclic annealing(Fig. 5(a)) and a 1.8 μm thick Ge sample prepared by 4.5 μm thick Gedeposition followed by HCl etching (Fig. 5(b)). In Fig. 5(a), the Ge(400) peak position in Qz direction of 0.708 Å−1 indicates a tensilestrain of 0.11% due to thedifference of thermal expansion coefficient be-tweenGe and Si. Broadening of the Ge (400) peak in Qx direction is verysmall. This broadening is caused by the presence of tilted Ge (400)

((a)

((c)

10µm

<110>

<110>

10µm

Fig. 4. Two dimensional micro Raman images of stress distribution of samples after blanket G(a) 4.5 μm, (b) 1.8 μm, (c) 1.3 μm and (d) 500 nm, respectively. b110> directions are show

planes due to TDs. The full width at half maximum value (FWHM) inQx direction is 3.8×10−4 Å−1 only. Therefore, the steep Ge (400)peak of the 4.5 μm thick Ge layer before HCl etching is confirminggood crystallinity. In the case of the Ge sample after HCl etching(Fig. 5(b)), the Ge (400) peak position in Qz direction is 0.708 Å−1,which is identical to that before HCl etching and it indicates the samelevel of strain. The FWHM of the Ge (400) peak in Qx direction is4.1×10−4 Å−1, which is slightly higher than before HCl etching. Thissmall increase of the FWHM could be explained by the reduced thick-ness of the low TDD Ge region in the upper part of the Ge layer,whose TDD is ~1×10−6 cm−2. The diffuse scattering around the Ge(400) peak after HCl etching (Fig. 5(b)) is not pronounced comparedto that before etching (Fig. 5(a)). These results support the statementthat the crystallinity of the Ge layer after HCl etching is as good as ofthe sample before etching, and the TDD level is also as low as that beforeHCl etching. For both samples, a diffusion tail of Ge (400) peak towardthe Si (400) peak is observed. This diffusion tail indicates an intermixingof Ge and Si at the interface [8,12]. The length of the diffusion tail is notincreased after the HCl etching, which indicates that the Si intermixingis not proceeding during the etching process.

3.2. Selective Ge growth and etching

The window size dependence of TDD at different cyclic annealingtemperatures is shown in Fig. 6. The TDD decreases with increasingcyclic annealing temperature for all window sizes used. However,even though the thermal budget increases from 800 °C to 860 °C,the TDD reduction is about 50% only. For the same annealing temper-ature a lower TDD is obtained for smaller windows. A reduction ofabout 30% is observed for 10×10 μm2 compared to 100×100 μm2.

b)

d)

10µm <110>

<110> 10µm

e growth with cyclic annealing (a) and followed by etching (b)–(d). Ge thicknesses aren by arrows.

0.740

0.735

0.730

0.725

0.720

0.715

0.710

0.705

-0.005 0.000 0.005

Qx [1/Å]

-0.005 0.000 0.005

Qx [1/Å]

Qz

[1/Å

]

0.740

0.735

0.730

0.725

0.720

0.715

0.710

0.705Q

z [1

/Å]

1E6

1E5

1E4

1E3

1E2

1E1

1E0

(a) (b)

)004(iS)004(iS

Ge (400) Ge (400)

Fig. 5. XRD reciprocal space maps of Si(400) and Ge(400) diffraction of (a) 4.5 μm thick Ge deposited with cyclic annealing and (b) after HCl etching to 1.8 μmGe thickness. Si (400)and Ge (400) peaks between (a) and (b) are connected by straight dashed line for comparison of peak position in Qz direction.

3220 Y. Yamamoto et al. / Thin Solid Films 520 (2012) 3216–3221

Possible reasons of the TDD reduction in smaller windows are that theTDs in smaller window do easier to glide out to the sidewall and/orthe Ge thickness in smaller windows is higher due to microloading ef-fects of GeH4.

To distinguish the reasons of different TDD at different window size,growth rates of selectively deposited Ge in windows of different sizeare measured (Fig. 7). The growth rate increases with increasing GeH4

partial pressure for all window sizes used. At the same GeH4 partial pres-sure, the growth rate is increasing with downsizing the window size. Inthe case of standard GeH4 partial pressure, approximately a two times

100x100 100x50 50x50 25x25 10x100

1

2

3

TD

D (

x108 c

m-2

)

Window Size ( m2)

Annealing Temp.:(oC)

800

820

840

860

Fig. 6. TDD of Ge selectively grown with cyclic annealing process in windows of differ-ent sizes. Annealing temperature is varied. Ge thickness is 800 nm.

higher growth rate is observed for the patterned wafer compared tothat for blanket wafer. A low pattern size dependence of about 10% be-tween 100×100 μm2 and 10×10 μm2 is observed. However, the 10%higher Ge thicknesswould positively influence the lowering of TDD. Con-sidering TDD results of blanket Ge growth with cyclic annealing (Fig. 2(○)), the 10% higher Ge thickness at 800 nmaffects about 30% of TDD re-duction. Therefore, the lower TDDs in smallerwindows under our exper-imental condition are mainly caused by this thickness effect.

Fig. 8 shows the Ge thickness dependence (500 nm, 800 nm, and1300 nm) of TDD for different window sizes. As shown for blanket Gegrowth in Fig. 2, more than one order of magnitude of TDD reduction

100x100 100x50 50x50 25x25 10x10

101

102

Growth Temp.: 550oC

Ge

Gro

wth

Rat

e (n

m/m

in.)

Window Size ( m2)

PGeH4:

Std.

3/4

1/2

1/4

Fig. 7. Growth rate of selective Ge in windows of different sizes. PGeH4 is varied.

100x100 100x50 50x50 25x25 10x100

2

4

6

8

Annealing Temp.: 800oCT

DD

(x1

08 cm

-2)

Window Size ( m2)

Thickness (nm)

500

800

1300

Fig. 8. TDD of Ge selectively grown with cyclic annealing process in windows of differ-ent sizes. Cyclic annealing temperature is 800 °C.

Table 1TDD of Ge layers selectively grown with cyclic annealing and HCl etching process.a) and b) show the samples before etching and c) shows a sample after etching of sam-ple b). Cyclic annealing temperature is 800 °C. Window size is 50×50 μm2.

# Thickness before etching(nm)

Thickness after etching(nm)

TDD(cm−2)

a) 500 500 (w/o etch) 4.3×108

b) 1300 1300 (w/o etch) 3.9×107

c) 1300 500 4.1×107

3221Y. Yamamoto et al. / Thin Solid Films 520 (2012) 3216–3221

is observed by increasing the Ge thickness from 500 nm to 1300 nm forall windowsizes used. Thismeans that a drastic reduction of TDD is pos-sible by increasing the Ge thickness without increasing the thermalbudget. The TDDs of selectively grown Ge with cyclic annealing at500 nm, 800 nm, and 1300 nmare roughly of the same level as for blan-ket wafer. In the case of samples targeted to 500 and 800 nm thick Ge, aslightly lower TDD is obtained in smaller windows. This difference iscaused by the slightly higher Ge thickness due to microloading effectsas discussed in Fig. 7 already. In the case of the sample with 1300 nmthick Ge, the window size dependence of TDD is not clearly observed,because the thickness dependence of TDD at higher Ge thickness regionis smaller compared to lower thickness region. Relative high error barsof TDD values due to a lower number of counts of TDs in small windows(for TDD of 3×107 cm−2, only 30 etchpits exist in a 10×10 μm−2 win-dow by Secco defect etching) should be also taken into consideration.

In Table 1 are summarized TDDs of Ge layers selectively grown withcyclic annealing process before/after etching. For 1300 nm thick selectiveGe deposition followed by 800 nm etching a TDD of 4.1×107 cm−2 isobtained, which is of the same level as for 1300 nm thick selective Ge.This means that as shown for blanket Ge already, a 10 times lower TDDis obtained by deposition and etching processes compared to the Ge sam-ple of the same thickness without etching.

4. Conclusions

Blanket and selective Ge growth with low TDD on Si is investigat-ed using reduced pressure CVD by deposition with a cyclic annealingprocess followed by HCl etching. In the case of blanket Ge deposition,a TDD of 1.3×106 cm−2 is achieved for 1.8 μm thick Ge by etching

back from 4.5 μm thickness, which is of the same level as for the sam-ple before HCl etching. RMS of roughness of the 1.8 μm thick Ge is alsomaintained at the same level as that before HCl etching. The surfaceroughness increases by further HCl etching because of a non-uniform strain distribution near the interface due to misfit disloca-tions and TDs. The TDD also becomes higher because the etchfrontof Ge reaches dislocations that exist near the interface. In the caseof selective Ge growth, a slightly lower TDD is observed in smallerwindow caused by the small pattern size dependence of Ge growthrate. A significant decrease of TDD of selectively grown Ge is observedby increasing the Ge thickness. About ten times lower TDD at thesame Ge thickness is demonstrated by applying a combination of de-position and etching processes to selective Ge growth. The resultsshown here have high potential for Ge process integration intoCMOS process flows by enabling high quality thin Ge layers.

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