LOW POWER VLSI

LOW POWER VLSIseminar by Gowrav L(1MS13LVS03)1TOPIC Coverage (contents)4.1.3 - Circuit Activity Driven Architectural Transformations

4.1.4 - Architecture-Driven Voltage Scaling 09-04-2014MSRIT _LPVLSI Subject Seminar2IntroFilters in DSP circuits represented by state equations-Architectural transforms can be applied on theseRoy and Chatterjee proposed heuristic transforms-These transforms use commutative and associative laws of linear operations on linear time invariant digital circuits.

http://dl.acm.org/citation.cfm?id=16492309-04-2014MSRIT _LPVLSI Subject Seminar3

S1(t + 1) = c1s1(t) + c3s2(t) + ku(t). 09-04-2014MSRIT _LPVLSI Subject Seminar4Implementation TechniqueThe filter can be implemented using either word-parallel or bit-serial arithmetic.Word - ParallelIn the word- parallel case, each signal (arc) of the data flow graph of Figure 4.7 represents W bits of data comprising a data word.The W bits {bw, bw-1,.. ...,b1} are fed in parallel to the respective adders and multipliers. 09-04-2014MSRIT _LPVLSI Subject Seminar5

Modified Parallel Word IIR88888809-04-2014MSRIT _LPVLSI Subject Seminar6Cont.The delays are designed to hold W bits in parallel.

At time (t + 1) next frame, let z out of W bits have different logic values than at time t.

Signal activity is defined as the ratio of z over W and is given by(t)= z/W09-04-2014MSRIT _LPVLSI Subject Seminar7The variable (t) is a random variable for different values of t and represents a stochastic process.

The authors define the average activity (t, t + N) of a signal over N consecutive time frames as

09-04-2014MSRIT _LPVLSI Subject Seminar8For Serial-bit IIRIn case of bit-serial arithmetic, the bit values of the data word are transmitted serially over a single data line over consecutive time steps. Thus it is not inter-word differences in bit values, but intra-word bit differences that cause node activity. 09-04-2014MSRIT _LPVLSI Subject Seminar9FormulaeOver large values of N show that the average activity factor remains constant, showing that the stochastic process is strict sense stationary. Average Power for this case

09-04-2014MSRIT _LPVLSI Subject Seminar10Case 1

The architectural transforms on the DSP filters are based on the following observations obtained through extensive simulation 09-04-2014MSRIT _LPVLSI Subject Seminar11Consider a word- parallel computation tree I inputs (i1, i2,---, ii )and output

rational constants.

For simplicity, let I = 2L 1, where L is the number of levels in a perfectly balanced adder tree, as shown in Figure 4.8. If input values of the tree are mutually independent, then:

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Case 2 - Linear Array Adders

09-04-2014MSRIT _LPVLSI Subject Seminar13ConclusionNote that no assumptions were made regarding the implementation details of the adders or the multipliers. Assuming that the capacitances at the internal nodes are all equal, improvement of up to 23% in power dissipation can be achieved. 09-04-2014MSRIT _LPVLSI Subject Seminar14End of 4.1.3References :

09-04-2014MSRIT _LPVLSI Subject Seminar154.1.4 - Architecture-Driven Voltage Scaling P = CV2flarge improvement in power dissipation can be obtained if the supply voltage is scaled down, as Vdd appears as a square term in the expression for average power dissipation.

one immediate side effect is the increase in circuit delay due to the voltage reduction. 09-04-2014MSRIT _LPVLSI Subject Seminar16Problem -- Non LinearityIn the submicrometer range the interconnect capacitances do not scale proportionately and can become dominant.Hence, it is worth looking at architectural transformations to compensate for the delay to achieve lower power dissipation by scaling down the supply voltage Solution -- parallel or pipelined architecture. 09-04-2014MSRIT _LPVLSI Subject Seminar17Case

09-04-2014MSRIT _LPVLSI Subject Seminar18P = CV2f09-04-2014MSRIT _LPVLSI Subject Seminar19

Vdd scaled down from 5 to 2.9 VResultsThis method of using parallelism to reduce power has the overhead of more than twice the area and is not suitable for area constrained designs. 09-04-2014MSRIT _LPVLSI Subject Seminar20Alternate Approach - Pipelining

09-04-2014MSRIT _LPVLSI Subject Seminar21EffectsWith additional pipeline latch (Figure 4.12, the critical path becomes max[Tadder, Tcomparator ], allowing the adder and the comparator to operate at a slower speed. If one assumes the two delays to be equal, the supply voltage can again be reduced from 5 to 2.9 V, the voltage at which the delay doubles, with no loss in throughput. Due to the addition of the extra latch, if the effective capacitance increases by a factor of 1.15, then 09-04-2014MSRIT _LPVLSI Subject Seminar22

Results and ConclusionAs an added bonus in pipelining, increasing the levels of pipelining has the effect of reducing logic depth and hence power contributed due to hazards. An obvious extension is to use a combination of pipelining and parallelism to obtain area and power constrained design.09-04-2014MSRIT _LPVLSI Subject Seminar23Thank You References : LOW-POWER CMOS VLSI CIRCUIT DESIGN > Kaushik Roy Sharat C. Prasad

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