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A 2.4 GHz Low Noise Amplifier and Mixer for Blue tooth Application Jyotirmay Gadewadikar

Graduate Student, University of Texas at Arlington

Abstract The design of a 2.4 GHz Low Noise Amplifier and Mixer for bluetooth application using low cost 0.35µm is described. This paper briefly reviews basic principles of Low Noise Amplifiers and Mixer. The proposed designs use Gilbert Cell Architecture for Mixer and Inductive Degeneration for LNA. The simulation is done using Agilent’s Advance Design System. System level simulation capabilities of the software are described using Mixer Block. Introduction Research over the last ten years has resulted in attempts toward single-chip CMOS RF circuits for Bluetooth, global positioning system, digital enhanced cordless telecommunications and cellular applications. Use of CMOS for low-cost integration of a Blue Tooth RF transceiver front-end Mixer and LNA is quite popular. The choice of architecture, circuit topology design, and systematic optimization of the different blocks is necessary.

Figure 1 : Typical Block Diagram of a Heterodyne Receiver.

Fig 1 Shows the Block Diagram of a heterodyne receiver, following sections will describe the Low Noise Amplifiers and Mixer for the Bluetooth front end application including the system level simulations. LNA Design for BlueTooth Receiver The Low Noise Amplifier is the first block in the receiver. The signal from the antenna is amplified and downconverted by the mixer. The issues in the design of LNA are-

• Low Input Referred Noise, NF • High Gain • Adequate Linearity

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• Impedance Matching • Low Power Consumption

Design Specifications • RF Frequency = 2.4 GHz • Technology : 0.35 µm CMOS. • Supply voltage: 3.3V LNA Architecture- Inductive Source degeneration-

Fig: 2 Inductive Degeneration

We have used the inductive source degeneration architecture(Figure 2) for our design. With such an inductance, current flow lags behind an applied gate voltage. An important advantage of this method is that one then has control over the value of the real part of the impedance through choice of inductance. The input impedance has the following form Zin = sL + 1/s Cgs + gm/ Cgs * Lapprox = sL + 1/s Cgs + ωT * L (1) Hence the input impedance is that of a series RLC network, with a resistive term that is directly proportional to the inductance value. Capacitive degeneration contributes a negative resistance to the input impedance. Hence, any source-to-substrate capacitance offsets the positive resistance from inductive degeneration. Equation (1) shows that the input impedance is purely resistive only at resonance, so this method can provide only a narrowband impedance match. The inductance Ls is chosen to provide the desired input resistance (equal to Rs, the source resistance). Since the input impedance is purely resistive only at resonance, an additional degree of freedom, provided by inductance Lg, is needed to guarantee this condition. Now, at resonance, the gate-to-source voltage is Q times as large as the input voltage. The overall stage trans-conductance Gm under this condition is Gm= gm1Qin = gm1 / ω0 Cgs (Rs + Ls ωT Ls) = ωT / 2 ω0 Rs (2)

Where we have used the approximation that ωT is the ratio of gm1 to Cgs. Transistor sizing is a major factor, which affects the design characteristics.

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Cascoding transistor M2 is used to reduce the interaction of the tuned output with the tuned input and to reduce the effect of M1’s Cgd. The total node capacitance at the drain of M2 resonates with inductance Ld both to increase the gain at the center frequency and simultaneously to provide an additional level of highly desirable band pass filtering. Cb is a DC blocking capacitor which is present to prevent the upsetting the gate-to-source bias of M1. The value of Cb is chosen to have a negligible reactance at the signal frequency, and is sometimes implemented as an off-chip component. The bias transistors width and current are arbitrarily chosen as a tenth of that of the main transistor. Two competing considerations constrain the size of the cascoding transistor. The gate-drain overlap capacitance can reduce the impedance looking into the gate and drain of M1 considerably, degrading both the noise performance and input match. It is a straightforward matter to show that for equal sized common source and cascoding devices, the resistive component at the input is given by Re[Zin] = ωT Ls / (1 + 2 Cgd/ Cgs) (3) The degenerating inductance must therefore be increased to compensate for this. To suppress these consequences of the miller effect, one should normally use a relatively large cascoding device in order to reduce the gain of the common-source transistor. However, the parasitic source capacitance associated with a large device effectively increases the amplification of the cascoding device’s own internal noise at high frequencies. Merging the source region of the cascoding transistor with the drain region of the common source transistor is effective in reducing many of these problems and is mostly readily implemented by making the two devices equal. Noise Analysis-

Figure 3: Equivalent circuit for input stage noise calculations Input Impedance at resonance is given by-

(4) At the series resonance of the input circuit, the impedance is purely real and proportional to Ls. By choosing Ls appropriately, this real term can be made equal to 50 Ω. The gate

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inductance Lg is used to set the resonance frequency once Ls is chosen to satisfy the criterion of a 50- Ω input impedance. The Noise Figure of the LNA can be computed by analyzing the circuit shown in Fig 3. In this circuit RL represents the series resistance of the inductor Lg, Rg is the gate resistance of the NMOS device and Vs

2 represents the channel thermal noise of the device. To evaluate the output noise when the amplifier is driven by a 50- Ω source, we first evaluate the transconductance of the input stage. With the output current proportional to the voltage on Cgs, the input circuit takes the form of a series-resonant network Gm = gm1*Qin = gm1 / ω0 Cgs (Rs + ωTLs )= ωT/(2ωoRs) (5) where Qin is the effective Q of the amplifier input circuit. In this expression, which is valid at the series resonance ωo, Rl and Rg have been neglected relative to the source resistance, Rs. Using equation (5) for calculating the total output noise power density due to RL, Rg and the output impedance and calculating F using the equation F= Total Output Noise / Total Output Noise due to Source (6) The LNA noise factor can be shown to be -

(7) where gd0 is the zero-bias drain conductance of the device and γ is a bias-dependent factor. The gate inductance Lg is used to set the resonance frequency once Ls is chosen to satisfy the criterion of a 50-Ω input impedance. This equation for noise factor reveals several important features of this LNA architecture. Note that the dominant term in (7) is the last term, which arises from channel thermal noise. Surprisingly, this term is proportional to gd0. So, according to this expression, by reducing gd0 without modifying ωT, we can simultaneously improve noise figure and reduce power dissipation. We can achieve this result by scaling the width of the device while maintaining constant bias voltages on its terminals and leaving the channel length unchanged. This scaling is consistent with the condition of constant ωT, which depends only on the bias voltages on the device. However, this expression assumes that the amplifier is operated at the series resonance of its input circuit. So, a reduction in gd0 and, hence in Cgs must be compensated by an increase in Lg to maintain a constant resonant frequency. So, better noise performance and reduced power dissipation can be obtained by increasing the Q of the input circuit resonance. By applying device scaling in this fashion to improve noise performance, the linearity of the amplifier will tend to degrade due to increased signal levels across Cgs. However, short channel MOS devices operating in velocity saturation have a relatively constant transconductance with sufficient gate overdrive. This property is one advantage of implementing LNA’s with MOS devices. A second important feature in (7) is the inverse

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dependence on ωT2. Continued improvements in technology will therefore naturally lead

to improved noise performance at a given frequency of operation. Minimum Noise Factor Fmin (or NFmin) is given by,

(8) LNA Design and Simulation- The LNA has been implemented and simulated in a 0.35-µm CMOS technology provided through the MOSIS service. DC voltage biasing simulations were done to set proper bias for the circuit. S- parameter simulations were done to establish S(2,1), S(1,2), S(1,1), S(2,2), NF and NFmin values.

Figure 4: LNA Schematic

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Figure 5: LNA Schematic The complete schematic of the LNA is shown in Fig. 4. The amplifier is a two-stage, cascoded architecture. The drain of M2 is tuned by an on-chip spiral inductor, Ld . This inductor resonates with the total capacitance at the drain of M2, including Ld of M3. Transistor M3 serves as an open-drain output driver. M3 has a gate width, which is half the value of the width of M1. Ls sets the input impedance of the LNA and is critical to the operation of the amplifier. Lgnd and Lout are unwanted parasitics, so their values are kept minimum. Lvdd aids in supply filtering with M4, which acts as a supply bypass capacitor. A large value of inductance is needed for this, so Lvdd is kept high.

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The Simulated Results are shown in following figures below.

Figure 6: Forward Gain

Figure 7: Reverse Gain

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Figure 8: S(1,1)

Figure 9 : S(2,2)

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Figure 10: Noise Figure

Figure 11: NFmin

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Results- The LNA designed has the following characteristics- • Forward Gain , S(2,1) = 23.75 dB • Reverse Gain, S(1,2) = -37 dB • S(1,1) = -7.5 dB • S(2,2) = -2 dB • Noise Figure, NF = 4.25 dB • NFmin = 3 dB

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Mixer Design for Bluetooth receiver The Gilbert double-balanced mixer configuration is widely used in RFIC applications because of its compact layout and moderately high performance. Design of a CMOS Gilbert mixer has been done focusing on the parameters that influence the linearity of the signal path, the noise, and therefore the spurious-free dynamic range of the mixer. Exploring design tradeoffs that include biasing and device sizing, LO power, conversion gain, gain compression, intermodulation distortion. Design Objectives: • Understanding operations of MOSFET gilbert mixer. • Biasing considerations • Design for stability linearity and noise • Specify performance: NF, P1dB , Third Order Intercept. Choosing Mixer Circuit Topology: There are many different mixer circuit topologies and implementations that are suitable for use in receiver and transmitter systems. We have select one of the widely used double-balanced mixer topologies (Gilbert Cell) in our project. The design process presented here has more general applicability to other circuit approaches, both for mixers and amplifiers, in receiver applications. Design Specifications • Frequencies: RF =2.4 GHz IF =10.7 Mhz LO =2.3893 GHz • Technology : 0.35 µm CMOS. • Supply voltage: 3.3V MOSFET Model A BSIM 3.3 model was used for the 0.35 µm CMOS process. Parameters for the model were obtained from a digital CMOS process, so absolute accuracy for more analog applications involving distortion and noise is not to be assumed. But, relative accuracy is sufficient for exploring many of the design details and revealing general trends.(See Appendix for Detailed MOSFET MODEL used in the design) GILBERT MIXER An ideal double balanced mixer( Figure 12) simply consists of a switch driven by the local oscillator that reverses the polarity of the RF input at the LO frequency. To get the highest performance from the mixer we must make the RF to IF path as linear as

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possible and minimize the switching time of the LO switch. The ideal mixer (Fig 12) would not be troubled by noise (at the low end of the dynamic range) or intermodulation distortion (IMD) at the high end since the transconductors and resistors are linear and the switches are ideal. The ideal balanced structure cancels any output at the RF input frequency since it will average to zero. It also cancels out any LO frequency component since we are taking the IF output as a differential signal and the LO shows up as common mode.

Figure 12 : Ideal Double Balanced Mixer Mixer Fundamentals : Mixers perform frequency translations (conversion) by multiplication of an RF input signal with an LO signal. The trig relationship cos x sin y = (1/2) [sin(x + y) - sin(x - y)] provides the desired up and down translations. Let VRF(t)=VR cos(ωRF t) The circuit converts this into a current I=gm VRF (t) VIF (t) the out put is given by VIF (t)=2gmRLT(t)VRF (t)=AT(t)VRF(t) Where T(t) is LO switching function T(t) =T1(t)+T2(t)

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Figure 13: Sum of Switching Functions

If the LO is a square wave with 50% duty cycle, it is easily represented by its Fourier Series. The symmetry causes the even-order harmonics to drop out of the LO spectrum. When multiplied by a single frequency cosine at ωRF the desired sum and difference outputs will be obtained as shown in the fig13. There will be harmonics of the LO present at 3ωLO, 5ωLO, etc. that will also mix to produce outputs called “spurs” (an abbreviation for spurious signals). IF Output Spectrum

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Figure 14: IF Output Spectrum

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Ideal Conversion Gain : The second-order output spectral lines at ωLO+ωRF, ωLO-ωRF are the desired up conversion and downconversion products from the mixer. Typically, one of these outputs will be removed by IF filtering. Note that ideally there will not be any third-order or higher odd-order products in the mixer output since only odd LO harmonics are generated in a perfectly symmetric switching DB mixer. The DC component should also cancel. This reduces the number of spurious outputs when compared with other nonlinear or unbalanced mixer approaches making the selection of the LO and IF frequencies less restrictive. The ideal conversion gain (VIF/VR ) 2 = A2 (2/Π )2 = - 4 dB (if A=1). In real mixers, there is always some imbalance. This will produce some LO to IF or RF to IF feed through (thus, isolation is not perfect). Secondly, the RF to IF path is not perfectly linear. This will lead to inter-modulation distortion. Odd-order distortion (typically third and fifth order are most significant) will cause spurs within the IF bandwidth or cross-modulation when strong signals are present. Also, the LO switches are not perfectly linear, especially while in the transition region. This can add more distortion to the IF output and will increase loss due to the resistance of the switches. INTERMODULATION DISTORTION : • Inter modulation distortion consists of the higher order signal products that are generated when two signals are present at the mixer input, the IMD will be down and up converted by the LO as will the desired RF signal. • IMD generation is a good indicator of large signal performance of a mixer. • Absolute accuracy is highly dependent on the accuracy of the device model, but the relative accuracy is valuable for optimizing the circuit parameters for the best IMD performance. Design of MOS mixer considerarions : • Device width. • Biasing • Linearity of transconductance amplifier • Stability and input matching network. • Gain compression and IMD • Noise figure • Spurious free Dynamis range

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Gilbert Cell Schematic:

Figure 15 : Gilbert Cell

This is a schematic (Figure 15) of a MOSFET version of the Gilbert Cell.The upper FETs provide a fully balanced, phase-reversing current switch function. The lower FETs are the transconductance amplifier. Design decisions for Gilbert Cell : • Ibias(Bias Current) and device widths W1 and W2: We need to choose a W1 that will provide high gm, saturation at low VDS (for low power supply operation), and low noise. Large widths are preferred for noise, and the optimum width for noise with power constraints can be estimated from the MOS device parameters. Large widths also require large bias currents to obtain high gm. Choosing W1 = W2 is typically best. So, next we must investigate the minimum current required to keep all devices in saturation. • Linearity of signal path: Once the bias is determined, we will investigate linearization of the transconductance amplifier through source resistance and inductance. Resistance will increase the input voltage range where nearly linear gain can be obtained, but will reduce conversion gain to some degree. Source inductance will be used mainly to guarantee stability by forcing a positive real component into the input impedance. This also helps to make the input impedance

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easier to match. Device width and bias current: • Width estimation Expression for for the width of the optimum device: For CMOS width L=0.35 µm and Rg =50 Ω

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The device width of 800 m is estimated from a MOSFET noise mode. For this Width,having IDS is large enough to saturate the MOSFET (VDS > Vdsat). At the same time, design for low VDD operation is preffered, so large VDS is also undesirable. Finally, large VDS will increase hot electron effects at the drain thereby increasing noise. VDsat is the drain voltage at which the channel first reaches saturation. At saturation, the drain current no longer increases rapidly with further increase in VDS because the drain end of the channel has pinched off. It is necessary to insure that the device is in saturation in order to obtain high gm and low Cgd, beneficial for most active circuit implementations. To establish the device operating points gate to source and drain to source voltage is varied from 0 to 1.5 volts and 0 to 3 volts respectively (Figure 16). Aim of this simulation is to achieve maximum transconductance and to calculate saturation voltage.

Figure 16: Curve Tracing and DC Characterization

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Figure 17: Device Characterization Display Saturation voltage for the device is 1 volt so any drain to source voltage greater than 1 volt will keep the device in saturation region. The simulation setup can show the tranconductance values for given operating point, for the operating point shown (figure 17 )Gm=0.017,Vds=1.1V (greater than saturation value) Bias Current estimation: This involves DC analysis (figure 18) of differential MOS pair in order to find an acceptable bias current for a particular bias width Requires VDS>Vdsat Using differential amplifier to evaluate device I-V & gm. Using Ibias as the independent parameter(figure18 ).

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Figure 18: Differential Pair DC Analysis

Figure 19: Differential Pair DC Analysis Display

The figure 19 show VDS and gm as a function of IDS. VDD = 3.3V in this case, and

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the RD value was varied with IDS to maintain a constant drain voltage of 2.4V. Since both inputs of the diff pair are at the same voltage (2V in this example) we Define IDS = I_bias/2 as an Eqn in the display panel. I_bias is swept by controlling the current into a current mirror with an independent DC current source. The PARAMETER SWEEP controller can be used to vary W1. Also, we can include voltages at all device nodes in the data file by using the OPTIONS controller and setting OutputInternalNodes=yes. VDS is defined by another Eqn as VDS = MOSFET1.d - MOSFET1.s From the gm plot, we can see that gm increases directly with IDS and with W1. Also, VDS is well above the saturation knee (roughly 0.5V) for all currents and widths. At currents below about 4 mA, there is little benefit to increasing W1 beyond 600 µm, so we will choose this as our minimum bias current. Linearity of signal path(RF to IF) A transfer characteristic is simulated by sweeping the DC input voltage (figure 20) VDin = Vin - Vref. Vref = 2.0V. We would expect that by increasing the resistance RS, adding negative feedback, we would linearize the transfer characteristic by exchanging gain for linearity. In the simulation shown(Figure 21), RS values are stepped using a PARAMETER SWEEP controller from 1 to 101 ohms.

Figure 20: Set Up For Linearity Analysis

Figure 21 :Linearity Analysis Circuit

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Figure 22: Effect of change in Rs over linearity

Figure 22 shows that Gain (slope) becomes more linear over a wider input voltage range with increasing RS. Mixer Conversion Gain, Isolation, and Port Impedance This simulated the mixer input and output spectra, conversion gain isolation and all port impedances for a differential mixer. The following variables(Figure 23) will characterize the parameters

Figure 23: Variable Settings for Simulation

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Output Spectrum : The output spectrum has the down converted frequency component at 10.7 Mhz and at –35.474 dBm.

Figure 24: Output Spectrum

Input Spectrum : RF input at 2.4GHz is –33.370 dBm.

Figure 25: Input Spectrum

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Figure 26: Conversion Gain for Sum and Difference Components

Port to Port Isolation: Isolation better than 100 dB is a result of an unrealistic model for the mixer.Real circuit will be unbalanced to some extent.

Figure 27: Port to Port Isolation GAIN COMPRESSION SIMULATION: This schematic simulates the IF output power vs RF input power , and RF output power vs IF input power to show the gain compression behaviour. Harmonic balance (Figure 28 and figure 29) is the method of choice for simulation of mixers. By specifying the number of harmonics to be considered for the LO and RF input frequencies and the maximum order (highest order of sums and differences) to be retained, we get the frequency domain result of the mixer at all relevant frequencies. Maximum order corresponds to the highest order IM product (n + m) to be considered (nf[1] ± mf[2]). The simulation will run faster with lower order and fewer harmonics of the sources, but may be less accurate. We tested this by checking if the result changes significantly as you increase order or harmonics. The frequency with the highest power level (the LO) is always the first frequency to be designated in the harmonic balance controller. Other inputs follow sequencing from highest to lowest power.

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Figure 28: Sweep Plan (Coarse and Fine)

Figure 29: Harmonic Balance Settings

Figure 30: Variable Settings Equations are added to the display panel which select the IF frequency, calculating the differential IF output power, converting it to dBm, then subtracting the RF input power, also in dBm. conv_gain = dBm(V_IFout2/(2*RD) )-P_RF

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V_IFout is the differential output voltage at the IF output frequency. This frequency is selected from the data set using the mix function. The down-converted IF at 45 MHz is selected with: V_IFout = mix(Vout,-1,1). The indices in the curly brackets are ordered according to fundamental frequencies. Thus, -1,1 selects RF_freq-LO_freq The upper linear line shows the ideal If power for down conversion and the lower nonlinear one shows the real behaviour 1 dB compression point is the one where the difference between them is 1 dB.

Figure 31: 1 dB Compression Point Figure 31 identifies the 1 dB gain compression power to be about -2 dBm

Figure 32: Conversion Gain vs Available Source Power

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Figure 33: Conversion Gain vs IF Power

1 dB compression input power and associated conversion gain 1dB gain compression input power(dBm) Conversion Gain -1.865 -6.518 Inter Modulation Distortion Simulation We will be mainly concerned with the third-order IMD. This is especially troublesome since it can occur at frequencies within the IF bandwidth. If we have 2 input frequencies at 2.3995 and 2.4005 GHz. Third order products at 2f1 - f2 and 2f2 - f1 will be generated at 2.3895 and 2.4014 GHz. These may fall within the filter bandwidth of the IF filter and thus cause interference to a desired signal. Other odd-order products will also be of interest, but may be less reliably predicted unless the device model is precise enough to give accurate non linearity in the transfer characteristics up to the 2n-1th order.

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Figure 34 : Harmonic Balance Variable and RF Input Settings for IMD simulation

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Figure 35 : Circuit for IMD Simulation

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Figure 36 : Output Spectrum for Defined RF input

Third Order Intercept : A widely-used figure of merit for IMD is the third-order intercept (TOI) point. This is a fictitious signal level at which the fundamental and third-order product terms would intersect. In reality, the intercept power is 10 to 15 dBm higher than the P1dB gain compression power, so the circuit does not amplify or operate correctly at the IIP3 input level. The higher the TOI, the better the large signal capability of the mixer. It is common practice to extrapolate or calculate the intercept point from data taken at least 10 dBm below P1dB. One should check the slopes to verify that the data obeys the expected slope = 1 or slope = 3 behavior. When this is true, OIP3 = (PIF-PIMD)/2 + PIF. Also, the input and output intercepts are simply related by the gain: OIP3 = IIP3 + conversion gain. In the data display a, equations are used to select out the IF fundamental tone and the IMD tone, in this case, the upper sideband. The mix function now has 3 indices since there are 3 frequencies present: LO, RF1 and RF2. The dBm conversion again takes into account the actual differential output load resistance.

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Figure 37: Setting for Third Order Intercept Point

Figure 38 : Third Order Intercept

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Figure 39 : Conversion Gain

Noise Figure : This simulated all side band Noise figure since all imaged are included in noise and conversion gain. We have been concentrating on the large signal limitations of the mixer. Noise determines the other end of the mixer dynamic range. Noise figure is defined as the ratio between the input and output S/N ratio.

NF (dB) = 10 log[(S/N)in]/[(S/N)out]

Any real mixer or amplifier will degrade S/N because noise is added to the signal. The minimum input signal power is determined by noise. The noise is represented by a NF. The maximum signal power is limited by distortion, which we describe by IIP3.

Figure 40: Noise Figure Calculations

Results: • IIP3=-4dBm • Noise Figure=11.438 dB • 1 dB Compression Point : -2 dBm • Conversion Gain : -5.506 dB

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System Level Simulation: ADS has the facility to define the components like mixers and amplifiers which can be used for effective system level simulations. These smart components (Fig) contains the circuit, and they are represented as blocks having only predefine inputs and outputs parameters defining the component can be defined eg. We can define VDD, RD,W1,W2,RS and LS for the mixer component shown in the Figure 41 and Figure 42.

Figure 41 : Mixer Block

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Figure 42: Putting parameter values

These block can be defined for a given circuit topology and can be fited into the system level simulation diagram, selecting “Push Into Hierarchy”(Figure 43) will open up the circuit (Figure 45), After getting into circuit selecting “Pop out of Hierarchy”(Figure 44) will lead into to System level diagram again. The method is very effective in system level simulations and effect of individual component study.

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Figure 43: Getting Inside the block

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Figure 44 : Getting into the System Level

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Figure 45 : Circuit with defined ports Conclusion: Design and simulation of Low Noise Amplifier and Mixer has been done, Mixer Block has been simulated using system design capabilities of the tool

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REFFERENCES

[1] Pradeep B. Khannur and Koh Soo Long,” A 2.45GHz Fully- Differential CMOS Image Reject Mixer for Bluetooth application”, Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE , 2002. [2] Thomas H. Lee, ”The Design of CMOS Radio Frequency Integrated Circuits”, Cambridge University Press. [3] Steve Long “RFIC MOS Gilbert Cell Mixer Design.” Agilent . [4] John W.M.Rogers, Jose A.Macedo,Calvin Plett “A Completely Integrated 1.9 GHz Receiver Front-End With Monolithic Image reject Filter and VCO” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES,VOL. 50 January 2002.

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Appendix A: 0.35 µm CMOS Model

Figure 46: CMOS Model

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Figure 46(Continued): CMOS Model

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