logic-input cmos quad drivers - microchip...

M TC4467/TC4468/TC4469Logic-Input CMOS Quad Drivers

Features• High Peak Output Current: 1.2 A• Wide Operating Range:

- 4.5 V to 18 V• Symmetrical Rise/Fall Times: 25 nsec• Short, Equal Delay Times: 75 nsec• Latch-proof. Will Withstand 500 mA Inductive

Kickback• 3 Input Logic Choices:

- AND / NAND / AND + Inv• ESD Protection on All Pins: 2 kV

Applications• General Purpose CMOS Logic Buffer• Driving All Four MOSFETs in an H-Bridge• Direct Small Motor Driver• Relay or Peripheral Drivers• CCD Driver• Pin-Switching Network Driver

Package Types

General DescriptionThe TC4467/TC4468/TC4469 devices are a family offour-output CMOS buffers/MOSFET drivers with 1.2 Apeak drive capability. Unlike other MOSFET drivers,these devices have two inputs for each output. Theinputs are configured as logic gates: NAND (TC4467),AND (TC4468) and AND/INV (TC4469).

The TC4467/TC4468/TC4469 drivers can continuouslysource up to 250 mA into ground referenced loads.These devices are ideal for direct driving low currentmotors or driving MOSFETs in a H-bridge configurationfor higher current motor drive (see Section 5.0 fordetails). Having the logic gates onboard the driver canhelp to reduce component count in many designs.The TC4467/TC4468/TC4469 devices are very robustand highly latch-up resistant. They can tolerate up to5 V of noise spiking on the ground line and can handleup to 0.5 A of reverse current on the driver outputs.The TC4467/4468/4469 devices are available incommercial, industrial and military temperature ranges.

12345678

16

131211109

1A1B2A2B3A3B

GNDGND

VDD

1Y2Y3Y4Y4B4A

VDD1514

TC4467TC4468TC4469

16-Pin SOIC (Wide)

1

23

45

6

7

14

1312

1110

9

8

1A

1B2A

2B3A

3B

GND

VDD

1Y2Y

3Y4Y

4B

4A

TC4467TC4468TC4469

14-Pin PDIP/CERDIP

2002 Microchip Technology Inc. DS21425B-page 1

TC4467/TC4468/TC4469
Logic Diagrams
TC4468TC4467

Output

TC446XVDD

14

7

1Y13121B

1A

2Y12342B

2A

3Y11563B

3A

4Y10894B

4A

GND

TC4469

14

7

1Y13121B

1A

2Y12342B

2A

3Y11563B

3A

4Y10894B

4A

14

7

1Y13121B

1A

2Y12342B

2A

3Y11563B

3A

4Y10894B

4A

GND

VDD VDD VDD

6

GND

DS21425B-page 2 2002 Microchip Technology Inc.

TC4467/TC4468/TC4469
1.0 ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings†Supply Voltage ...............................................................+20 VInput Voltage ............................. (GND – 5 V) to (VDD + 0.3 V)Package Power Dissipation: (TA ≤ 70°C) PDIP...................................................................800 mW CERDIP .............................................................840 mW SOIC ..................................................................760 mWPackage Thermal Resistance: CERDIP RθJ-A ...................................................100°C/W CERDIP RθJ-C.....................................................23°C/W PDIP RθJ-A ..........................................................80°C/W PDIP RθJ-C ..........................................................35°C/W SOIC RθJ-A ..........................................................95°C/W SOIC RθJ-C..........................................................28°C/WOperating Temperature Range: C Version ...................................................0°C to +70°C E Version.................................................-40°C to +85°C M Version ..............................................-55°C to +125°CMaximum Chip Temperature....................................... +150°CStorage Temperature Range.........................-65°C to +150°C

†Notice: Stresses above those listed under "MaximumRatings" may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthose or any other conditions above those indicated in theoperation listings of this specification is not implied. Exposureto maximum rating conditions for extended periods may affectdevice reliability.

ELECTRICAL SPECIFICATIONSElectrical Characteristics: Unless otherwise noted, TA = +25°C, with 4.5 V ≤ VDD ≤ 18 V.

Parameters Sym Min Typ Max Units Conditions

InputLogic 1, High Input Voltage VIH 2.4 — VDD V Note 3Logic 0, Low Input Voltage VIL — — 0.8 V Note 3Input Current IIN -1.0 — +1.0 µA 0 V ≤ VIN ≤ VDD

OutputHigh Output Voltage VOH VDD – 0.025 — — V ILOAD = 100 µA (Note 1)Low Output Voltage VOL — — 0.15 V ILOAD = 10 mA (Note 1)Output Resistance RO — 10 15 Ω IOUT = 10 mA, VDD = 18 VPeak Output Current IPK — 1.2 — AContinuous Output Current IDC — — 300 mA Single Output

— — 500 Total PackageLatch-Up Protection Withstand Reverse Current

I — 500 — mA 4.5 V ≤ VDD ≤ 16 V

Switching Time (Note 1)Rise Time tR — 15 25 nsec Figure 4-1Fall Time tF — 15 25 nsec Figure 4-1Delay Time tD1 — 40 75 nsec Figure 4-1Delay Time tD2 — 40 75 nsec Figure 4-1Power SupplyPower Supply Current IS — 1.5 4 mAPower Supply Voltage VDD 4.5 — 18 V Note 2Note 1: Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to

drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching times are ensured by design.

2: When driving all four outputs simultaneously in the same direction, VDD will be limited to 16 V. This reduces the chance that internal dv/dt will cause high-power dissipation in the device.

3: The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 µsec to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.


TC4467/TC4468/TC4469
ELECTRICAL SPECIFICATIONS (OPERATING TEMPERATURES)
TRUTH TABLE

Electrical Characteristics: Unless otherwise noted, over operating temperature range with 4.5 V ≤ VDD ≤ 18 V.

Parameters Sym Min Typ Max Units Conditions

InputLogic 1, High Input Voltage VIH 2.4 — — V Note 3Logic 0, Low Input Voltage VIL — — 0.8 V Note 3Input Current IIN -10 — 10 µA 0 V ≤ VIN ≤ VDD

OutputHigh Output Voltage VOH VDD – 0.025 — — V ILOAD = 100 µA (Note 1)Low Output Voltage VOL — — 0.30 V ILOAD = 10 mA (Note 1)Output Resistance RO — 20 30 Ω IOUT = 10 mA, VDD = 18 VPeak Output Current IPK — 1.2 — AContinuous Output Current IDC — — 300 mA Single Output

— — 500 Total PackageLatch-Up Protection Withstand Reverse Current

I — 500 — mA 4.5 V ≤ VDD ≤ 16 V

Switching Time (Note 1)Rise Time tR — 15 50 nsec Figure 4-1Fall Time tF — 15 50 nsec Figure 4-1Delay Time tD1 — 40 100 nsec Figure 4-1Delay Time tD2 — 40 100 nsec Figure 4-1Power SupplyPower Supply Current IS — — 8 mAPower Supply Voltage VDD 4.5 — 18 V Note 2Note 1: Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to

drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching times are ensured by design.

2: When driving all four outputs simultaneously in the same direction, VDD will be limited to 16 V. This reduces the chance that internal dv/dt will cause high-power dissipation in the device.

3: The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 µsec to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.

Part No. TC4467 NAND TC4468 AND TC4469 AND/INV

Inputs A H H L L H H L L H H L LInputs B H L H L H L H L H L H L

Outputs TC446X L H H H H L L L L H L LLegend: H = High L = Low


TC4467/TC4468/TC4469
2.0 TYPICAL PERFORMANCE CURVES
Note: TA = +25°C, with 4.5 V ≤ VDD ≤ 18 V.

FIGURE 2-1: Rise Time vs. Supply Voltage.

FIGURE 2-2: Rise Time vs. Capacitive Load.

FIGURE 2-3: Rise/Fall Times vs. Temperature.

FIGURE 2-4: Fall Time vs. Supply Voltage.

FIGURE 2-5: Fall Time vs. Capacitive Load.

FIGURE 2-6: Propagation Delay Time vs. Supply Voltage.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed herein arenot tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

140

120

100

80

60

40

20

03 5 7 9 11 13 15 17 19

2200 pF0 p

p1600 pF

1000 pF

470 pF

100 pF

t RIS

E(n

sec)

VSUPPLY (V)

140

120

100

80

60

40

20

0100 1000 10,000

10 V15 V

VVV5 V

t RIS

E(n

sec)

CLOAD (pF)

0-50

TIM

E (

nse

c)

5

10

15

20

25

-25 0 25 50 75 100 125

tFALL

tRISE

VSUPPLY = 17.5 VCLOAD = 470 pF

TEMPERATURE (°C)

140

120

100

80

60

40

20

03 5 7 9 11 13 15 17 19

p100 pF

470 pF

1000 pF

1500 pF

2200 pF

t FA

LL

(nse

c)

VSUPPLY (V)

140

120

100

80

60

40

20

010000

1000 10,000

VVV5 V

10 V15 V

t FA

LL

(nse

c)

CLOAD (pF)

04

DE

LA

Y T

IME

(n

sec)

20

40

60

80

8 12 14 16 186 10

VSUPPLY (V)

ttD1

tD2

CCLOAD 470 pF = 4


TC4467/TC4468/TC4469
2.0 TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: TA = +25°C, with 4.5 V ≤ VDD ≤ 18 V.

FIGURE 2-7: Input Amplitude vs. Delay Times.

FIGURE 2-8: Quiescent Supply Current vs. Supply Voltage.

FIGURE 2-9: High-State Output Resistance.

FIGURE 2-10: Propagation Delay Times vs. Temperatures.

FIGURE 2-11: Quiescent Supply Current vs. Temperature.

FIGURE 2-12: Low-State Output Resistance.

140

120

100

80

60

40

20

01 9 10

DE

LA

Y T

IME

(n

sec)

2 3 4 5 6 7 8

INPUT FALLING

INPUT RISING

VDRIVE (V)

tD1

tD2

VDD V= 12 V

04

0.5

1.0

1.5

2.0

2.5

6 8 10 12 14 16 18

OUTPUTS = 1

OUTPUTS = 0

VSUPPLY (V)

I QU

IES

CE

NT

(mA

)

04 6 8 10 12 14 16 18

VSUPPLY (V)

5

10

15

20

25

30

35

RD

S(O

N)

(Ω)

TJ = +150°C

TJ = +25°C

70

20100 120

DE

LA

Y T

IME

(n

sec)

-40 -20 0 20 40 60 80

30

40

50

60

-60°C)

VDD = 17.5 V = 470 pF

VINtD1

tD2

3.5

0100 120-40 -20 0 20 40 60 80

3.0

2.5

2.0

1.5

1.0

0.5

OUTPUTS = 1

OUTPUTS = 0

-60

I QU

IES

CE

NT (

mA

)

TJUNCTION (°C)

VVDD = 17.5 V

04 6 8 10 12 14 16 18

5

10

15

20

25

30

35

VSUPPLY (V)

RD

S(O

N)

(Ω)

TJ = +150°C

TJ = +25°C


TC4467/TC4468/TC4469
2.0 TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: (Load on single output only).

FIGURE 2-13: Supply Current vs. Capacitive Load.



FIGURE 2-16: Supply Current vs. Frequency.



60

0100 1000 10,000

50

40

30

20

10

2 MHHz1 MHz1 MHz1 MH

5000 kHz

200 kHz

20 kHz

I SU

PP

LY

(mA

)

CLOAD (pF)

VDD = 18 V

60

0100 1000 10,000

50

40

30

20

10

2 MHz2 MHz

1 MHz

500 kHz

200 kHz

20 kHz

CLOAD (pF)

I SU

PP

LY

(mA

)

VDD V= 12 V

60

50

40

30

20

10

0100 1000 10,000

1 MHz500 kHz200 kHz20 kHz

2 MHz

I SU

PP

LY

(mA

)

CLOAD (pF)

VVDD V = 6 V

60

0100 1000FREQUENCY (kHz)

50

40

30

20

10

2200 pF

11000 pF

p100 pF

10 10,000

VDD = 18 V

I SU

PP

LY

(mA

)

60

010 100

FREQUENCY (kHz)

50

40

30

20

10

1000

2200 pF

pp1000 pF

100 pF

10,000

I SU

PP

LY

(mA

)

VDD V= 12 V

60

010 1000100

FREQUENCY (kHz)

50

40

30

20

10

2200 pF

1000 pF

100 pF

10,000

I SU

PP

LY

(mA

)

VVDD = 6 V


TC4467/TC4468/TC4469
3.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE

14-Pin PDIP, CERDIP

16-Pin SOIC (Wide) Description

Symbol Symbol

1A 1A Input A for Driver 1, TTL/CMOS Compatible Input1B 1B Input B for Driver 1, TTL/CMOS Compatible Input2A 2A Input A for Driver 2, TTL/CMOS Compatible Input2B 2B Input B for Driver 2, TTL/CMOS Compatible Input3A 3A Input A for Driver 3, TTL/CMOS Compatible Input3B 3B Input B for Driver 3, TTL/CMOS Compatible Input

GND GND Ground— GND Ground4A 4A Input A for Driver 4, TTL/CMOS Compatible Input4B 4B Input B for Driver 4, TTL/CMOS Compatible Input4Y 4Y Output for Driver 4, CMOS Push-Pull Output3Y 3Y Output for Driver 3, CMOS Push-Pull Output2Y 2Y Output for Driver 2, CMOS Push-Pull Output1Y 1Y Output for Driver 1, CMOS Push-Pull Output

VDD VDD Supply Input, 4.5 V to 18 V— VDD Supply Input, 4.5 V to 18 V


TC4467/TC4468/TC4469
4.0 DETAILED DESCRIPTION
4.1 Supply BypassingLarge currents are required to charge and dischargelarge capacitive loads quickly. For example, charging a1000 pF load to 18 V in 25 nsec requires 0.72 A fromthe device's power supply.

To ensure low supply impedance over a wide frequencyrange, a 1 µF film capacitor in parallel with one or twolow-inductance, 0.1 µF ceramic disk capacitors withshort lead lengths (<0.5 in.) normally provide adequatebypassing.

4.2 GroundingThe TC4467 and TC4469 contain inverting drivers.Potential drops developed in common groundimpedances from input to output will appear asnegative feedback and degrade switching speedcharacteristics. Instead, individual ground returns forinput and output circuits, or a ground plane, should beused.

4.3 Input StageThe input voltage level changes the no-load orquiescent supply current. The N-channel MOSFETinput stage transistor drives a 2.5 mA current sourceload. With logic “0” outputs, maximum quiescent supplycurrent is 4 mA. Logic “1” output level signals reducequiescent current to 1.4 mA, maximum. Unused driverinputs must be connected to VDD or VSS. Minimumpower dissipation occurs for logic “1” outputs.

The drivers are designed with 50 mV of hysteresis,which provides clean transitions and minimizes outputstage current spiking when changing states. Input volt-age thresholds are approximately 1.5 V, making anyvoltage greater than 1.5 V, up to VDD, a logic “1” input.Input current is less than 1 µA over this range.

4.4 Power DissipationThe supply current versus frequency and supplycurrent versus capacitive load characteristic curves willaid in determining power dissipation calculations.Microchip Technology's CMOS drivers have greatlyreduced quiescent DC power consumption.

Input signal duty cycle, power supply voltage and loadtype influence package power dissipation. Given powerdissipation and package thermal resistance, the maxi-mum ambient operating temperature is easilycalculated. The 14-pin plastic package junction-to-ambient thermal resistance is 83.3°C/W. At +70°C, thepackage is rated at 800 mW maximum dissipation.Maximum allowable chip temperature is +150°C.Three components make up total package powerdissipation:

1. Load-caused dissipation (PL).2. Quiescent power (PQ).3. Transition power (PT).A capacitive-load-caused dissipation (driving MOSFETgates), is a direct function of frequency, capacitive loadand supply voltage. The power dissipation is:

EQUATION

A resistive-load-caused dissipation for ground-referenced loads is a function of duty cycle, loadcurrent and load voltage. The power dissipation is:

EQUATION

PL fCVS2=

VS Supply Voltage=C Capacitive Load=f Switching Frequency=

PL D VS VL–( )IL=

IL Load Current=

D Duty Cycle=VS Supply Voltage=VL Load Voltage=


TC4467/TC4468/TC4469
A resistive-load-caused dissipation for supply-referenced loads is a function of duty cycle, loadcurrent and output voltage. The power dissipation is
EQUATION

Quiescent power dissipation depends on input signalduty cycle. Logic HIGH outputs result in a lower powerdissipation mode, with only 0.6 mA total current drain(all devices driven). Logic LOW outputs raise thecurrent to 4 mA maximum. The quiescent powerdissipation is:

EQUATION

Transition power dissipation arises in the complimen-tary configuration (TC446X) because the output stageN-channel and P-channel MOS transistors are ONsimultaneously for a very short period when the outputchanges. The transition power dissipation isapproximately:

EQUATION

Package power dissipation is the sum of load,quiescent and transition power dissipations. Anexample shows the relative magnitude for each term:

Maximum operating temperature is:

EQUATION

FIGURE 4-1: Switching Time Test Circuit.

PL DVOIL=

IL Load Current=VO Device Output Voltage=D Duty Cycle=

PQ VS D IH( ) 1 D–( )IL+( )=

IL Quiescent Current with all outputs HIGH=

IH Quiescent Current with all outputs LOW=

D Duty Cycle=VS Supply Voltage=

(4 mA max.)

(0.6 mA max.)

Note: Ambient operating temperature should notexceed +85°C for "EJD" device or +125°Cfor "MJD" device.

PT fVs 10 10 9–×( )=

VS 15 V=C 1000 pF Capacitive Load=

D 50%=f 200 kHz=

PD Package Power Dissipation=PL PQ PT+ +=45mW 35mW 30mW+ +=110mW=

TJ θJA PD( )– 141°C=

θJA Junction-to-ambient thernal resistance=

TJ Maximum allowable junction temperature= (+150°C )

(83.3°C/W) 14-pin plastic package

VOUT470 pF1B

1A

2B2A

3B3A

4B4A

1 µF Film 0.1 µF Ceramic

90%

10%

10% 10%

90%

+5 V

Input (A, B)

VDD

Output

0 V

0V

90%12

34

56

89

7

10

11

12

13

14

VDD

tRtD1

tFtD2

Input: 100 kHz, square wave, tRISE = tFALL ≤ 10 nsec


TC4467/TC4468/TC4469
5.0 APPLICATIONS INFORMATION
FIGURE 5-1: Stepper Motor Drive.

FIGURE 5-2: Quad Driver For H-bridge Motor Control.

+12 V

14

TC4469

13

12

11

10

7

9

8

65

43

21

Red

Gray

Yel

Blk

Motor

B

A

Airpax#M82102-P2

7.5/Step

5

13

+5 V to +15 V

14TC4469

Direction

PWM Speed

18 V

Fwd

13

12

11

10

7

98

65

43

21

Rev

MotorM


TC4467/TC4468/TC4469
6.0 PACKAGING INFORMATION
6.1 Package Marking Information

14-Lead PDIP (300 mil) Example:

14-Lead CERDIP (300 mil) Example:

Legend: XX...X Customer specific information*YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line thus limiting the number of available charactersfor customer specific information.

* Standard OTP marking consists of Microchip part number, year code, week code, facility code, maskrev#, and assembly code.

16-Lead SOIC (300 mil) Example:

XXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXYYWWNNN

TC4469COE

XXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXXXXXXXXXXXXXXXXX

YYWWNNN

TC4467CPD

YYWWNNN

TC4468EJD

YYWWNNN


TC4467/TC4468/TC4469
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1

n

D

1

2

eBβ

E

c

A

A1

B

B1

L

A2

p

α

Units INCHES* MILLIMETERSDimension Limits MIN NOM MAX MIN NOM MAX

Number of Pins n 14 14Pitch p .100 2.54Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68Base to Seating Plane A1 .015 0.38Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60Overall Length D .740 .750 .760 18.80 19.05 19.30Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43Lead Thickness c .008 .012 .015 0.20 0.29 0.38Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78Lower Lead Width B .014 .018 .022 0.36 0.46 0.56Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92Mold Draft Angle Top α 5 10 15 5 10 15

β 5 10 15 5 10 15Mold Draft Angle Bottom* Controlling Parameter

Notes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.JEDEC Equivalent: MS-001Drawing No. C04-005

§ Significant Characteristic


TC4467/TC4468/TC4469
14-Lead Ceramic Dual In-line – 300 mil (CERDIP)
.780 (19.81)

.740 (18.80)

.300 (7.62)

.230 (5.84)

.200 (5.08)

.160 (4.06)

.200 (5.08)

.125 (3.18)

.110 (2.79)

.090 (2.29).065 (1.65).045 (1.14)

.020 (0.51)

.016 (0.41)

.040 (1.02)

.020 (0.51)

.098 (2.49) MAX.

.030 (0.76) MIN.

14-Pin CERDIP (Narrow)

.400 (10.16).320 (8.13)

.015 (0.38)

.008 (0.20)3° MIN.

PIN 1

.320 (8.13)

.290 (7.37)

.150 (3.81)MIN.

Dimensions: inches (mm)


TC4467/TC4468/TC4469
16-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot Angle φ 0 4 8 0 4 8

1512015120βMold Draft Angle Bottom1512015120αMold Draft Angle Top

0.510.420.36.020.017.014BLead Width0.330.280.23.013.011.009cLead Thickness

1.270.840.41.050.033.016LFoot Length0.740.500.25.029.020.010hChamfer Distance

10.4910.3010.10.413.406.398DOverall Length7.597.497.39.299.295.291E1Molded Package Width

10.6710.3410.01.420.407.394EOverall Width0.300.200.10.012.008.004A1Standoff §2.392.312.24.094.091.088A2Molded Package Thickness2.642.502.36.104.099.093AOverall Height

1.27.050pPitch1616nNumber of Pins

MAXNOMMINMAXNOMMINDimension LimitsMILLIMETERSINCHES*Units

Lβ

c

φ

h

45°

1

2

D

p

nB

E1

E

α

A2

A1

A

* Controlling Parameter

Notes:Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.JEDEC Equivalent: MS-013Drawing No. C04-102

§ Significant Characteristic


TC4467/TC4468/TC4469
NOTES:

TC4467/TC4468/TC4469
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2002 Microchip Technology Inc. DS21425B-page17

TC4467/TC4468/TC4469
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3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader ResponseTotal Pages Sent

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DS21425BTC4467/TC4468/TC4469

DS21425B-page18 2002 Microchip Technology Inc.

TC4467/TC4468/TC4469
PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-72773. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification SystemRegister on our web site (www.microchip.com/cn) to receive the most current information on our products.

PART NO. X XX

PackageTemperatureRange

Device

Device: TC4467: 1.2A Quad MOSFET Driver, NAND

TC4468: 1.2A Quad MOSFET Driver, ANDTC4469: 1.2A Quad MOSFET Driver, AND/INV

Temperature Range: C = 0°C to +70°CE = -40°C to +85°C (CERDIP only)M = -55°C to +125°C (CERDIP only)

Package: PD = Plastic DIP, (300 mil body), 14-leadJD = Ceramic DIP, (300 mil body), 14-leadOE = SOIC (Wide), 16-leadOE713 = SOIC (Wide), 16-lead (Tape and Reel)

Examples:a) TC4467COE: Commerical Temperature,

SOIC package.b) TC4467CPD: Commercial Temperature,

PDIP package.c) TC4467MJD: Military Temperature,

Ceramic DIP package.

a) TC4468COE713: Tape and Reel, Commerical Temp., SOIC package.

b) TC4468CPD: Commercial Temperature, PDIP package.

a) TC4469COE: Commercial Temperature, SOIC package.

b) TC4469CPD: Commercial Temperature, PDIP package.

2002 Microchip Technology Inc. DS21425B-page19

TC4467/TC4468/TC4469
NOTES:


TC4467/TC4468/TC4469

Information contained in this publication regarding deviceapplications and the like is intended through suggestion onlyand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.No representation or warranty is given and no liability isassumed by Microchip Technology Incorporated with respectto the accuracy or use of such information, or infringement ofpatents or other intellectual property rights arising from suchuse or otherwise. Use of Microchip’s products as critical com-ponents in life support systems is not authorized except withexpress written approval by Microchip. No licenses are con-veyed, implicitly or otherwise, under any intellectual propertyrights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,KEELOQ, microID, MPLAB, MXDEV, PIC, PICmicro,PICMASTER, PICSTART, PRO MATE, SEEVAL and TheEmbedded Control Solutions Company are registered trade-marks of Microchip Technology Incorporated in the U.S.A. andother countries.

dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,MPLINK, MPSIM, MXLAB, PICC, PICDEM, PICDEM.net,rfPIC, Select Mode and Total Endurance are trademarks ofMicrochip Technology Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service markof Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of theirrespective companies.

© 2002, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.


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