logic gate sizingjcf/ensino/disciplinas/... · relative dimensions of logic gates i a cmos logic...

Logic Gate SizingThe method of logical effort

João Canas Ferreira

University of PortoFaculty of Engineering

March 2016

Topics

1 Modeling CMOS Gates

2 Chain of logic gates

João Canas Ferreira (FEUP) Logic Gate Sizing March 2016 2 / 22

Relative dimensions of logic gates

I A CMOS logic gate may be characterized by four parameters:1 input capacitance Cin2 intrinsic output capacitance Cp3 pull-up resistance Rup4 pull-down resistance Rdn

I For each type of logic gate we can define a template (a reference gate)1 input capacitance Ct2 intrinsic output capacitance Cpt3 symmetric output resistance Rt = Rupt = Rdnt

I For a sized gate (a× larger):1 Cin = a× Ct2 Rup = Rdn = Rout = Rt/a3 Cp = a× Cpt


Propagation delay model (1)I Absolute propagation delay of a logic gate:

tpabs = 0.69 Rout(Cout + Cp) = 0.69 Rout Cout + 0.69 Rout Cp

For each gate type, this can be written in terms of the template:

tpabs = 0.69(

Rta

)Cin

CoutCin

+ 0.69(

Rta

)(a× Cpt)

tpabs = 0.69 Rt Ct f + 0.69 Rt Cpt

I Let’s map this to an equation of the form tpabs = τ (g× f + p)I f = Cout/Cin

I g =RtCt

R(inv)t C(inv)

t

p =RtCpt

R(inv)t C(inv)

t

I τ = 0.69× R(inv)t C(inv)

t (parameters of the template inverter)

I d = g× f + p propagation delay in units of τ


Propagation delay model (2)Gate delay

d = h + p

h: effort delay p: intrinsic delay

Logical efforth = g× f

g: logical effort f: effective fan-out

d = g× f + p

I Logical effort depends only on gate topology, not its size.I Intrinsic delay is constant for each gate type.I Effective fan-out depends on the relation between load and input

capacitance (size of the gate).I By definition, ginv = 1.I pinv = γ, the relation between input and output capacitance of the

inverter.João Canas Ferreira (FEUP) Logic Gate Sizing March 2016 5 / 22

Definitions of logical effort

The following definitions of logical effort are all equivalent:

I Definition 1: The logical effort of a gate is how many times the outputcurrent of that gate is lower than the output current of an inverter withthe same input capacitance.

I Definition 2: The logical effort of a gate is given by the relation of itsinput capacitance to the input capacitance of an inverter with the sameoutput current.

I Definition 3: The logical effort of a gate is given by the slope of its delayvs. fan-out curve divided by the slope of the corresponding curve for aninverter.


Logical effort of some basic gatesThe logical effort of a gate is given by the relation of its input capacitance tothe input capacitance of an inverter with the same output current.

2

1a

x

2

2

2

2

x

a

b

4

4

1

1

a

b

x

(a ) (b) (c)

g=1 g=4/3 g=5/3


Summary of the logical effort of some basic gates

Number of inputs

1 2 3 n

inverter 1

nand 4/3 5/3 (n+2)/3

nor 5/3 7/3 (2n+1)/3

xor 4 12


Graphical model

Source: [Sutherland99]

(Illustrates definition 3)João Canas Ferreira (FEUP) Logic Gate Sizing March 2016 9 / 22

Estimation of the intrinsic delayThe intrinsic delay of some type of logic gate is X times the intrinsic delay ofthe template inverter pinv where X is :

the ratio between the sum of the diffusion areas (proportional totheir widths) of sources or drains connected to the output node ofthe gate to the corresponding areas of the template inverter.(Condition for having the same output current as the template inverter.)

p =(∑

W1 + β

)pinv

with

β =(W/L)p(W/L)n

I Estimation assumes that all transistors have the same length of thediffusion areas (contacts as close as possible to the channel).

I For better results, calibrate the model from simulation data.


Table of estimated intrinsic delays

Gate Intrinsic delay

Inverter pinv

n-input NAND n× pinv

n-input NOR n× pinv

n-input XOR or XNOR n× 2(n–1) × pinv


ExamplesI Find the delay of the FO4 (fan-out of 4) inverter

d = f× g + p = 1× 4 + pinv = 4 + 1 = 5

I Find the delay of a NOR4 gate that drives 10 identical gates

d = f× g + p = 3× 10 + 4× 1 = 34

I Find the frequency of oscillation of a ring with N identical inverters (Nodd)For each inverter:

d = f× g + p = 1× 1 + pinv = 2

Propagation delay around the ring:

T = N× d× τ

Frequency of oscillation:

F =1

2× N× d× τ


Topics

1 Modeling CMOS Gates

2 Chain of logic gates


Branching effortProblem: when sizing a logic path it is necessary to account for the loadsimposed by gates that do not belong to that path.

Ci

Ctotal

Coff

Con

a dimensionar

21

à When sizing the gates on the path, thesize of logic gate 1 must take into accountnot just the load of gate 2, but also theload Coff (which is constant as the gate isnot being sized).

Define b, the branching effort, as

b =Cpath + Coff

Cpath

Then, the effective fan-out of gate 1 is:

f1 =Cpath + Coff

Cin=

Cpath

Cin×

Cpath + Coff

Cpath= fpercurso × b


Minimizing the delay of two gates

Gate

1

Gate

2

C1

g1

p1

Input capacitance:

Logical effort:

Parasitic delay:

C2

g2

p2

C3


D = (g1f1 + p1) + (g2f2 + p2) f1 =C2C1

f2 =C3C2

f1f2 =C3C1

= F

D = (g1f1 + p1) +(

g2Ff1

+ p2

)δDδf1

= g1 –g2F

f21= 0 ⇒ g1f1 = g2f2

In generalI Delay is minimized when each stage has the same effort h = g× f.I This fact is independent of the size and intrinsic delays;

it is valid for any number of stages and branching effort (included in f).João Canas Ferreira (FEUP) Logic Gate Sizing March 2016 15 / 22

Optimum delay

For a path of N logic gates:

I f1f2 · · · fN = BF with B = b1b2 · · · bNI Path effort: H = (g1f1)(g2f2) · · · (gNfN) = GBF

with G = g1g2 · · · gNI H does not depend on the size of the gates.I The value of H is not changed by inserting inverters.

à All stages bear the same optimum effort h: H = h1/N

or h = N√H

à The minimum delay is:

D =∑

i

(h + pi) = NH(1/N) + P with P =∑

i

pi


Optimum number of stages

à Scenario: path with n1 stages and n2 inverters, N = n1 + n2

à Assume you can change n2, because it does not change the path effort (H)

D = NH(1/N) +

( n1∑i=1

pi

)+ (N – n1)pinv

δDδN

= –H(1/N) ln(H(1/N)) + H(1/N) + pinv = 0

à Let ρ be the stage effort delay for the optimum number of stages:

ρ = H(1/N):

pinv + ρ(1 – ln(ρ)) = 0

à The value of ρ that satisfies this equation is the stage effort delay (h) forall stages of the path: it is independent of other path characteristics.


Pragmatic aspects

I If pinv = 0 then ρ = e = 2.718

I Approximation: ρ ≈ 0.71 pinv + 2.82

I For pinv = 1 we get ρ ≈ 3.59

I Another approximation: N ≈ log4(H)

I Use table:

N(

1/N√

H + pinv

)=

(N + 1)(

1/(N+1)√

H + pinv

)I Fan-out of each stage: fi = h/gi

I If there is branching at the output of

that stage: fi =h

b gi

pinv

N 0.0 0.6 0.8 1.0

14.0 5.13 5.48 5.83

211.4 17.7 20.0 22.3

331.6 59.4 70.4 82.2

486.7 196 245 300

5237 647 848 1090

6648 2130 2930 3920

71770 6980 10100 14200

84820 22900 34700 51000

913100 74900 120000 184000

Path effort H


Example: path optimization

A

B

C

zy

C


I G = g0g1g2 = (4/3)3 = 2.37 B = 1 F = 1I H = 2.37 ⇒ D = 3×2.371/3+3×2pinv = 10I h = 4/3I z = C× (4/3)/(4/3) = C y = C

C

2C

2

C

2

C

2


à Assumes β = 2


Example: implementation of a logic function

(a )

(b)

(c)

g =

p = 8

g = 1

p = 1

g = 1

p = 1

g =

p = 2

g =

p = 2

g =

p = 2

g =

p = 2

g = 2

p = 4

5

3

4

3

5

3

4

3

10

3


I D = N (FBG)1/N + PI (a) D = 2 (3.33 F)1/2 + 9I (b) D = 2 (3.33 F)1/2 + 6I (c) D = 4 (2.86 F)1/4 + 7

I F = 1: use (b) D = 9.65I F = 12: use (c) D = 16.77


Logical effort: summary

I Determine the path effort: H = BFG

I Determine the optimum number of stages: N ≈ log4(H)

I Find the optimum stage effort delay: h = N√H

I Draw the logic path

I Find the input capacitance of each gate: Cin = Coutb× g

h

I If necessary, find the sizes of the transistors(using information from the template).


References

à Some figures come from the following books:

Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2ndedition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/

Sutherland99 I. Sutherland, B. Sproull and D. Harris, Logical Effort, MorganKaufmann Publishers, 1999.


http://bwrc.eecs.berkeley.edu/icbook/

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