Lithography Simulation-Based Full-Chip Design AnalysesPresenter: Puneet Sharma (sharma@ucsd.edu)Average Gate-width (WAvg) computation

Diffusion boundary may not be straight match diffusion area in dotted rectangle (a, b > misalignment tolerance)Average width = separation b/w computed diffusion boundariesAverage Gate-length (LAvg) computationTake intersection b/w diffusion and poly get gateGate not rectangular rectilinearize (midpoint-sum approx.)

LAvg computed from gate-lengths of slices after rectilinearization Specific to analysis objective. Two modes:Expression mode: computed using analytical expressionse.g., for delay objective: LAvg = WAvg/i(Wi/Li) for capacitance objective: LAvg = i(WiLi)/WAvgLookup-table mode: computed using table of device on- and off- currents for different gate-lengths and gate-widthsMapping to a cell in libraryEach cell instance prints different uniquification of each instance need to reconstruct hierarchyEquivalent gate-length (LEq) computation: derived from LAvgs of devices in the cell. Specific to analysis objective. LEq for objective:setup is max. of LAvgs. hold is min. of LAvgs.capacitance is computed to match the gate arealeakage is computed to match the total leakage can consider stacking effect to weigh devices differentlyFor each cell, variant from library selected that has closest gate-length to LEq of cell, and master updated in output Verilog

Inputs:Litho-simulated GDSDrawn layout: to correlate GDS with designStd. cell GDS and SPICE netlists: to run LVS find location of each device in a cell layoutStd. cell library w/ gate-length changed for devices in cellsObjective: type of analysis to be performed e.g., setup time, hold time, leakage, dynamic powerOutputs:Objective-specific Verilog: Verilog with cell masters modified to better estimate on-silicon power/performanceSPEF: modified parasiticsDevice Analyses: For each cell, analyzes litho-simulated poly layer to estimate gate-length of cells devices searches library for similar cell with non-nominal gate-lengths (cell variant) modifies master in VerilogInterconnect Analyses: For each interconnect, analyzes impact of non-ideal geometry on parasitics updates SPEFLithography simulation not connected to design we proposed a novel flow to link lithography simulation w/ off-the-shelf analyses toolsFor device analyses, device rectilinearized and LAvg computed. Devices in each cell considered to find LEq of cell and closest library variant usedFor interconnect analyses, impact of change in dimension on capacitance and resistance estimated using field-solver for template configurations and SPEF database modifiedLithography simulation-based analyses more accurate and adequately fastOngoing work:Consider impact of slice location on LAvg computationTransistor-level delay and power modeling to replace or supplement library chacterizationImprove speed and accuracy of interconnect analysesP. Gupta, A. B. Kahng, S. Nakagawa, S. Shah, P. SharmaBlaze DFM Inc., Sunnyvale, CAECE Department, U.C. San DiegoEECS Department, U. of MichiganTiming and power sign-off before RETSimilarity b/w drawn and printed design poor due to RETs and process variations Large difference b/w signed-off and on-silicon power & delayLithography simulation predicts on-silicon geometries at different process cornersHowever, lithography simulation purely geometry-based and not connected to design in any wayWe use lithography simulation w/ off-the-shelf design analysis tools to predict on-silicon performance & power Facilitates more accurate estimation lesser guardbandingPrevious work: Yang et al. DAC 05 similar flow suggested; several non-trivial details lacking; timing analysis only (for critical paths); no interconnects consideredInvokes device analyses per instance and interconnect analyses for SPEF databaseCan perform caching and distributed processingMixed-mode objectiveSeparate Verilogs generated for different objectives difficult to manage and non-standard mixed-mode objective generates one Verilog accurate for all objectives as follows:Step 1: hold objective for hold-critical cellsStep 2: setup objective for setup-critical cellsStep 3: capacitance objective for fanout cells of hold and setup critical cells not assigned objectiveStep 4: leakage/dynamic power for all other cellsLayout of a small circuit litho-simulated at 0nm and 200nm defocusAnalyses for setup and leakage objectives; color annotations show LEq

Practical runtime: 70K cell design in 1hrParasitic-change lookup table: predicts change in capacitance and resistance given change in interconnect width and spacingParameters: width, width and spacing of right and left neighbors, layer, densities of above and below layersTable created by field-solver simulations for geometries generated for a technologyLithography simulation-based parasitic extractionSPEF segment to routing segment mapping: for each routing segment in SPEF, corresponding geometries in drawn and litho-simulated layouts are found using SPEF node coordinatesShape rectilinearization: litho-simulated routing segments not rectilinear perform rectilinearization similar to gate-polySPEF database modification: parasitic change computed from lookup table for each slice (from rectilinearization) parasitic network reduction update SPEF databaseMotivationOverviewFull-Chip AnalysesConclusions & Ongoing WorkSimulated DiffusionContourDrawn DiffusionBoundaryDrawn PolyComputed DiffusionBoundaryEffective DiffusionAreaRectilinearizeMidpoint-sumapproximationSetup, Defocus = 0nmSetup, Defocus = 200nmLeakage, Defocus = 0nmLeakage, Defocus = 200nmCycle time0.351nsCycle time0.363nsLeakage1.488mWLeakage2.789mW