layout-aware scan-based delay fault testing puneet gupta 1 andrew b. kahng 1 ion mandoiu 2 puneet...
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Layout-aware Scan-based Layout-aware Scan-based Delay Fault TestingDelay Fault Testing
Puneet GuptaPuneet Gupta11
Andrew B. KahngAndrew B. Kahng11
Ion MandoiuIon Mandoiu22
Puneet SharmaPuneet Sharma11
1 ECE Department, University of California – San Diego2 CSE Department, University of Connecticut, Storrs
http://vlsicad.ucsd.edu
OutlineOutline
IntroductionIntroduction Problem formulationsProblem formulations Multi-fragment greedy algorithmMulti-fragment greedy algorithm Experiments and resultsExperiments and results Future directionsFuture directions
Delay Fault TestingDelay Fault Testing
Delay fault: Delay fault: failure of a failure of a path to meet timingpath to meet timing
Initialization VectorInitialization Vector
11 00 00 11
11 11
High clock speeds + High clock speeds + increasing variabilityincreasing variabilityDelay fault testing importantDelay fault testing important
Pair of vectors requiredPair of vectors required Initialization vectorInitialization vector Launch vectorLaunch vector
Launch VectorLaunch Vector
11
00
Scan-based Delay Fault TestingScan-based Delay Fault Testing
Utilizes standard shift-Utilizes standard shift-scan architecturescan architecture
Launch vector Launch vector produced in two ways:produced in two ways: From circuit logicFrom circuit logic
Functional justificationFunctional justification
From scan chainFrom scan chain Scan justificationScan justification
Functional JustificationFunctional Justification
Launch vector Launch vector generated by the generated by the circuit logiccircuit logic
1. Scan-in initialization vector
No effect of scan No effect of scan orderorder
2. Give system CLK to generate launch vector
3. Give system CLK, capture result
4. Scan-out result
11
00
00
1111
11
11
00
Not all paths testableNot all paths testable
Difficult to produce Difficult to produce vector pairsvector pairs
Scan JustificationScan Justification Launch vector generated by shifting initialization vectorLaunch vector generated by shifting initialization vector
1. Scan-in initialization vector2. Give scan CLK to generate
launch vector3. Give system CLK, capture
result4. Scan-out result
Given scan order, not all Given scan order, not all vector pairs usablevector pairs usable
Coverage:Coverage: %age of vector pairs %age of vector pairs usableusable
Initialization: 1 0 0 1 0 Launch: 1 0 1 1 0
11 00 00 11 0011 11 00 00 11
11
11
00
11
00
00
00
11
Increasing Scan CoverageIncreasing Scan Coverage Scan orderScan order
Initialization: 1 0 0 1 0 Launch: 1 0 1 1 0
11 00 00 11 0011 11 00 00 11
Don’t caresDon’t cares
Initialization: 1 0 x 1 1 Launch: 1 1 x 1 1 11 00 11 11 11
11 11 00 11 11
Dummy flopsDummy flops
Initialization: 0 0 0 0 1 Launch: 0 1 0 0 1
11 00 00 11 0011 00 11 11 00
00 00 00 00 1100 11 00 00 11
1100
Scan Order ObjectivesScan Order Objectives
Coverage driven, layout obliviousCoverage driven, layout oblivious Gupta et al, Cheng et al, …Gupta et al, Cheng et al, …
WL: 10.09 mm, Cov: 100.00%
WL: 1.22 mm, Cov: 56.80%
Layout driven, coverage obliviousLayout driven, coverage oblivious QPlace, Boese et al., Kobayashi et al., …QPlace, Boese et al., Kobayashi et al., …
WL: 1.46 mm, Cov: 100.00%
Layout + Coverage driven Our approach
OutlineOutline
IntroductionIntroduction Problem formulationsProblem formulations Multi-fragment greedy algorithmMulti-fragment greedy algorithm Experiments and resultsExperiments and results Future directionsFuture directions
Scan Chain OrderingScan Chain Ordering Modeled as TSP with flops as citiesModeled as TSP with flops as cities
TSP objectiveTSP objective Minimize WL:Minimize WL: MinWL MinWL (Boese et al.)(Boese et al.) Minimize #dummy for 100% coverage:Minimize #dummy for 100% coverage: CompleteDFC CompleteDFC (Gupta et al.)(Gupta et al.) This paper: Minimize WL + Maximize coverage:This paper: Minimize WL + Maximize coverage: MaxDFC MaxDFC
u(i)=0 & v(j)=1 where, u: Initialization vectoror u(i)=1 & v(j)=0 v: Launch vector
Dummy insertion in an edge makes all vector pairs compatible with itDummy insertion in an edge makes all vector pairs compatible with it
Vector pair incompatible with an edgeVector pair incompatible with an edge A vector pair is incompatible with an edge eA vector pair is incompatible with an edge e ijij if placing flop j after if placing flop j after
flop i in the scan chain causes it to become unusableflop i in the scan chain causes it to become unusable Formally, vector pair Formally, vector pair (u, v)(u, v) is incompatible with e is incompatible with eijij if if
MinWL MinWL (e.g., Boese et al.)(e.g., Boese et al.) GivenGiven
Set of n placed flip-flops F, Scan-in SI, Scan-out SO Find
Scan chain ordering of F {SI, SO}, starting with SI ending with SO
Such that Total scan chain length minimizedTotal scan chain length minimized
ee lw
CompleteDFC CompleteDFC (Gupta et al.)(Gupta et al.) GivenGiven
Set of Set of n n flip-flops flip-flops F,F, Scan-in Scan-in SI, SI, Scan-out Scan-out SOSO Set of m delay fault vector pairs Set of m delay fault vector pairs
FindFind Scan chain ordering Scan chain ordering of F of F {SI, SO}, starting with SI ending {SI, SO}, starting with SI ending
with SOwith SO Such thatSuch that
# dummy flops required for 100% coverage minimized# dummy flops required for 100% coverage minimized
otherwise
e with leincompatib pair vector any if
0
1 we
MaxDFCMaxDFC GivenGiven
Set of Set of n n placed flip-flops placed flip-flops F ,F , Scan-in Scan-in SI, SI, Scan-out Scan-out SOSO Set of Set of mm delay fault vector pairs, delay fault vector pairs, each with a weight each with a weight wwtt, , t t Upped bound on #dummies,Upped bound on #dummies, D D
FindFind Scan chain ordering Scan chain ordering of of FF { {SISI, , SOSO}, starting with }, starting with SISI ending with ending with
SOSO Set ofSet of alive vector pairs, C alive vector pairs, C
Such thatSuch that Scan length minimizedScan length minimized Sum of weights of alive vector pairs maximizedSum of weights of alive vector pairs maximized Vectors pairs incompatible with at most D edgesVectors pairs incompatible with at most D edges
pairsble Vector#Incompatil
lw
ee
OutlineOutline
IntroductionIntroduction Problem formulationsProblem formulations Multi-fragment greedy algorithmMulti-fragment greedy algorithm Experiments and resultsExperiments and results Future directionsFuture directions
Three Phase MFG - OverviewThree Phase MFG - Overview Phase IPhase I
Produce D+1 Produce D+1 short, high coverageshort, high coverage scan chain scan chain fragmentsfragments
Based on multi-fragment algorithm for TSPBased on multi-fragment algorithm for TSP Data structuresData structures
Edge-vector incompatibility matrixEdge-vector incompatibility matrix Edge bucketsEdge buckets
Phase IIPhase II Stitch D+1 fragments using D dummies minimizing Stitch D+1 fragments using D dummies minimizing
WLWL Phase IIIPhase III
Further reduce scan chain WLFurther reduce scan chain WL
Three Phase MFG – Phase IThree Phase MFG – Phase Iinitialize edge-vector incompatibility matrixinitialize edge-vector incompatibility matrixdistribute edges in buckets based on #incompatible vector pairsdistribute edges in buckets based on #incompatible vector pairswhilewhile #fragments > #dummies+1 #fragments > #dummies+1
pop shortest edge epop shortest edge e ijij from first non-empty bucket from first non-empty bucket
ifif( eij is admissible in tour )( eij is admissible in tour )add eadd eijij to tour to tour
remove vectors incompatible with eremove vectors incompatible with e ijij from edge-vector matrix from edge-vector matrix
promote edges with which removed vectors were incompatiblepromote edges with which removed vectors were incompatible
1122 00 00 00 00 11
1133 00 00 11 00 11
2233 11 00 00 00 00
2211 00 11 00 00 00
3311 00 00 00 00 11
3322 11 11 00 00 00
1
2
3 50
200
3001133
2233
+5 vectors, 0 dummies edge-vector matrix
0 1 2
buckets
1122
22113311
3322
Three Phase MFG – Phase IThree Phase MFG – Phase I ScalabilityScalability
Use small #edges, w(e) < TUse small #edges, w(e) < T If #frags < #dummies + 1, rerun with threshold=MIf #frags < #dummies + 1, rerun with threshold=MTT Quite insensitive to T, MQuite insensitive to T, M
Three Phase MFG – Phase IIThree Phase MFG – Phase II Target: Stitch D+1 fragments, minimizing WLTarget: Stitch D+1 fragments, minimizing WL
5 6
8 9
1 2 3
7
1011
4
ApproachApproach ATSP with fragments as citiesATSP with fragments as cities
1
2
3
500500300300
600600
600600
100100600600
D1
D2
wwee WL required to connect fragments WL required to connect fragments Small #citiesSmall #cities
Quick even with high quality TSP solverQuick even with high quality TSP solver
Three Phase MFG – Phase IIIThree Phase MFG – Phase III
Target: Further reduce scan WLTarget: Further reduce scan WL ApproachApproach
Create TSP instance with flops as citiesCreate TSP instance with flops as cities Throw in edges compatible with all Throw in edges compatible with all alivealive faults faults wwee WL of edge e WL of edge e
5 6
8 9
1
7
1011
42 3
D1
D2
5 6
8 9
1
7
1011
42 3
D1
D2
5 6
8 9
1
7
1011
42 3
D1
D2
OutlineOutline
IntroductionIntroduction Problem formulationsProblem formulations Multi-fragment greedy algorithmMulti-fragment greedy algorithm Experiments and resultsExperiments and results Future directionsFuture directions
Experimental FlowsExperimental Flows
Comparison of three flowsComparison of three flows MinWL MinWL (Boese et al.)(Boese et al.)
Reference min WL tourReference min WL tour CompleteDFC CompleteDFC (Gupta et al.)(Gupta et al.)
Reference full coverage tourReference full coverage tour MaxDFCMaxDFC
TestcasesTestcases
TestcaseTestcase # cells# cells # flops# flops # paths# paths Functional coverageFunctional coverage
s38417s38417 62916291 15641564 552552 0.54%0.54%
s13207s13207 16481648 627627 4949 8.16%8.16%
s9234s9234 529529 145145 361361 22.71%22.71%
AESAES 1046510465 554554 30503050 58.03%58.03%
DES3DES3 39123912 128128 14041404 7.69%7.69%
SynthesisSynthesisDesign CompilerDesign Compiler
STASTAPrimeTimePrimeTime
ATPGATPGTetraMAXTetraMAX
PlacementPlacementQPlaceQPlace
SourceSource
all vectorsall vectors
scanscanvectorsvectors
flopfloplocationslocations
pathspaths
func vectorsfunc vectors
Results: s38417Results: s38417
13.03 14.11
353.33
0
50
100
150
200
250
300
350
400
MinWL MaxDFC CompleteDFC
Functional Coverage
0.54.%
Scan Coverage23.86%
Uncovered0.00%
WirelengthWirelength
CoverageCoverageFunctional Coverage
0.54%
Scan Coverage
0.00%
Uncovered99.46% MinWL MaxDFC
Results: aesResults: aes
Functional Coverage58.03%Scan
Coverage8.75%
Uncovered33.22% Scan
Coverage42.97%
Functional Coverage58.03%
Uncovered0%
WirelengthWirelength
CoverageCoverage
5.84 7.5
118.26
0
20
40
60
80
100
120
MinWL MaxDFC CompleteDFC
MinWL MaxDFC
Dummy-Coverage TradeoffDummy-Coverage Tradeoff
Proposed ILP formulationProposed ILP formulation
Coverage vs #Dummies
0
20
40
60
80
100
120
0 5 10 15 20 25 30 35 40 45 50
#Dummies
Coverage
s38417
OutlineOutline
IntroductionIntroduction Problem formulationsProblem formulations Multi-fragment greedy algorithmMulti-fragment greedy algorithm Experiments and resultsExperiments and results Future directionsFuture directions
ConclusionsConclusions
We proposed an algorithm to simultaneously We proposed an algorithm to simultaneously reduce WL and increase delay fault coveragereduce WL and increase delay fault coverage
Significant increase in coverage with 10-30% WL Significant increase in coverage with 10-30% WL increaseincrease
Explored tradeoff b/w coverage and dummy Explored tradeoff b/w coverage and dummy insertioninsertion
Future DirectionsFuture Directions
Extension to multiple scan chainsExtension to multiple scan chains Congestion aware scan orderingCongestion aware scan ordering Modifications to use compacted and/or Modifications to use compacted and/or
redundant vectorsredundant vectors