lightning talk on java memory consistency model java day kiev 2014

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Brief introduction into what Memory Model is about and why it matters and when. Explanation why it was changed in Tiger and how. Also informs where to look for more and offers definition. I've gave this talk at PJUG and Java Day Kiev in 2014.

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Page 1: Lightning talk on Java Memory Consistency Model Java Day Kiev 2014
Page 2: Lightning talk on Java Memory Consistency Model Java Day Kiev 2014

@LAFK_pl, Polish JUG, May 2014 2

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MANAGEMENT!!

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Posted in 2012...

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... and still not corrected

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Leslie Lamport

● Distributed system clocks

● Happens-before

● Sequential Consistency

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Bill Pugh

● FindBugs

● Java Memory Model is broken● Final - Volatile● Double-checked

locking

● New JMM

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Sarita Adve

● Java Memory Model is broken

● Number of great papers on memory (consistency) models

● Best definition of MCM I found

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Within these 15-20 minutes

Intro

Memory model means?

Hardware

Java stuff

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Memory model?

If NOT about GC then...

what's it about?

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Memory CONSISTENCY

● Allowed optimizations● Possible behaviours / executions of a (possibly

multithreaded!) program● Which cores / threads see which values● How to make it consistent for us, programmers

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Where it matters?

● Javac / Jython / ...● JIT

● Hardware of course

● So JMM is a LANGUAGE memory consistency model

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Hardware

● CISC or RISC CPU● Number of registers● Caches size or type● How many functional units per CPU● Pipeline:

● Instruction decode > address decode > memory fetch > register fetch > compute ...

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Program / code optimizations?

● Reorder ● (e.g. prescient store)

● Remove what's unnecessary ● (e.g. synchronize)

● Replace instructions / shorten machine code● Function optimizations

● (e.g. Inlining)

● ...

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Exemplary CPU

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Barriers / fences

„once memory has been pushed to the cache then a protocol of messages will occur to ensure all caches are coherent for any shared data. The techniques for making memory visible from a processor core are known as memory barriers or fences.

– Martin Thompson, Mechanical Sympathy

differs per architecture / CPU / cache type!

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Barriers / Fences

● CPU instruction● Means „Flush now!”

● Forces update● Starts cache

coherency protocols

● Read / Write / Full

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Summarizing Java Language Spec:

● Describes whether the execution trace is a legal execution of the program

● Works by examining each read and checking write observed by that read

● Write is valid when it follows certain rules● Describes possible behaviours of the program

● Implementor adhering to above can optimize code as he likes

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What rules?

● Write is valid when it follows certain rules

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Before, or after?

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Before, or after?

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JSR-133 = new JM(C)M

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Class Reordering { int x = 0, y = 0; public void writer() { x = 1; y = 2; }

public void reader() { int r1 = y; // HERE: y == 2 => x == ? int r2 = x; }}

Reordering - classic example

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What was wrong with old JM(C)M?

You took a look, read the specs entire and...

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New Java Memory Model● SC on single-core and single-thread CPU is

fine but it doesn't cut it now● To ensure visibility, JVM JMM spec ensures:

● final ● volatile ● synchronized

are done well this time

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Barriers in Java – rules

● JMM● volatile – sfence after write, lfence before read

● final – sfence after init (field visibility)

● Atomic instructions (like lock) = mfence

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Further topics

● Why MCM and not a threading library? H.Boehm

● Better MCM? Sarita Adve● Possible optimizations and their gains● Performance of Java and hardware MCMs?

Clashes?● JMCM rules in more detail