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System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
LEON3-FT Processor System
LEON_3FTCore
8 Reg. Windows
LEON_3FTCore
8 Reg. Windows
FT MemoryController
FT MemoryController
8 x
GP
IO8
x G
PIO
GPIOEJTAG
2 kByteI- Cache
2 kByteI- Cache
2 kByteD- Cache
2 kByteD- Cache
AHB APB
1 x 24bitTimer
1 x 24bitTimer
UART 0UART 0
EDAC SRAMEDAC SRAM FLASHFLASH
Serial 0
Serial 1 UART 1UART 1
Bri
dg
eB
rid
ge
Scan TestScan TestFT Add-onFT Add-on
FT Add-onFT Add-on
Scan-I/F
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
• Installation of the release
• Adaptation of the configuration tool (to include IHP’s library)
• Implementation of data and instruction caches
• Logic synthesis of the design
• Implementation of scan chain
• Generation of the chip layout
• Simulation (functional, post-synthesis and post-layout net-list)
• Scan test vectors generation (ATPG)
• Scan test simulation
• Adaptation of testbenches
• EVCD test vectors generation
• Test specification
• Documentation
Implementation Details
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Double Modular Redundancy
• Double Modular Redundancy with self-voting has 20% lower failure-free probability, 37% lower power consumption and 16% lower silicon area overhead than Triple Modular Redundancy
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Protection Against Single Event Latchup
• Single event latchup effect requires design of a special power switch (SPS) cell
• Memories, EDACs and logic must be duplicated
• SPSs are placed under the cross-over points of the power stripes and standard cells
• SPS network is connected to the rest of power network in the power routing phase
• If VDD_C is short-circuited, T5 conducts high current
• Feedback line from Vdd1 = VDD_C causes T2 to switch on when this voltage is above the threshold voltage
• Automatically, T1 triggers Tstart output
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Chip Features
LEON-3
Area (mm2) 22
Number of signal ports 105
Number of power ports 20
Number of scan ports 1 (3)
Transistors (x106) 0.83
Cache Memory (kB) 6
Scanable Flip-Flops (x103) 15
Power/Frequency (mW/MHz) 6.2
Max Frequency (MHz) 160
Cache Array
Size (KB)
No. of Words
Data Width
Address Width
I/D Data 2.5 512 36 of 40 9
I/D Tag 0.5 128 29 of 32 7
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
SOC Design-for-Testability
• What is Scan-through-TAP?
Use of IEEE Standard 1149.1 user instruction to concatenate the internal scan chain with the BSR chain to perform a single chainoperation
• What do we achieve implementing Scan-through-TAP?
Reduction of the scan pins number
Accessibility of the internal scan chains through the TAP controller
Single shift path through for burn-in and diagnostics
• What kind of EDA tools do we need?
Standard synthesis, DFT, BSD, and ATPG tools
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
DFT/BSD in SOC Design Flow
yes
ApplicationsApplications
SystemSpecification
SystemSpecification
Library DatabaseLibrary Database
New ModulesCustomisable Modules
(synthesisable RTL code)
Configurable Modules
(synthesisable RTL code)Predefined Modules
(synthesised net-list, SDFand/or LEF)
Predefined Modules
(memory and custom blocks)
Simulation OK?Simulation OK?
HDL Model DefinitionHDL Top Module Definition
Logic Synthesis
Simulation OK?Simulation OK?
Layout Synthesis
no
yes
no
Simulation OK?Simulation OK?
Final ChipLayout
yes
no
Test BenchesTest BenchesLayout
Re-synthesisSufficient? yes
LogicRe-synthesis
Sufficient? yes
no
no
New Modules
ATPG
DFT/BSD
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Scan Insertion Flow
• Read in synthesized design
• Define clock constraints
• Define scan chain
• Insert scan chains
• Write out scan test protocol and netlist for TetraMAX
Read Design
Create Test Protocol
Specify Scan Architecture
Insert Scan Paths
Handoff Design
DFT DRC
Preview
DFT DRC
Coverage
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Boundary Scan Insertion Flow
Set BSD STT specifications
Preview BSD
Insert BSD logic
(Synthesis integrated)
BSD Gate Level
Netlist
Read Pin Map
Check IEEE 1149.1 Std
compliance
BSDL File
BSD PatternsBSDL File
BSD Patterns
1149.1 BSD Inserted design
Lib
Read design netlist
Lib
• Preview your JTAG design
• Insert your JTAG logic
• Write out final netlist
• Write BSDL file and patterns (optional)
• Check compliance to IEEE 1149.1 STD
• Write BSDL file and BSD patterns
• Write the STIL protocol file for ATPG
• Read technology synthesis libraries
• Read scanned ready netlist with IOs
• Set TAP FSM specification
• Set STT specification
• Read pin map for die package BSR order
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Scan-Through-TAP Register
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
STT Test Patterns
Netlist &
SPF
TetraMAXTetraMAX® ATPGATPG
ATPG
Patterns
RTL
Design Compiler
BSD CompilerBSD Compiler
JTAG InsertionJTAG Insertion
DFT CompilerDFT CompilerTest SynthesisTest Synthesis
Functional
Patterns
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Implementation Results
• Single scan register made of around 15000 scan flip-flops
• Boundary scan register of 151 cell
• 5 TAP instructions
BYPASS
EXTEST
PRELOAD
SAMPLE
STT
• 32000 BSD functional test patterns
• 1151 ATPG test patterns
• Chip area overhead below 7%
Caused by insertion of scan flip-flops and boundary scan logic
• Combined fault coverage is slightly above 94%
System-on-Chip Design, Guest lecture at University of Kragujevac, Technical Faculty Cacak, 01.10.-05.10.2012
Links for More Information
• http://www.tandem-projekt.de
• http://www.ict-mimax.eu
• http://www.mips.com
• http://www.gaisler.com
• http://www.arm.com
• http://www.tensilica.com