lecture1-v1

+

Chapter 1:Introduction to Digital Design

+ Integrated Circuits (IC) An integrated circuit (IC) consists of complex electronic

circuitries and their interconnections. William Shockley et al. of Bell Laboratories invented

transistor in 1948. Most current IC are built with MOSFET transistors. Types of ICs: Microprocessors, Cores, Memory chips, ASICs

Application-Specific Integrated Circuit (ASIC) is a microchip designed and used in a wide-range of

applications, including auto emission control, environmental monitoring, and personal digital assistants (PDAs).

http://searchcio-midmarket.techtarget.com/definition/microchip

http://searchmobilecomputing.techtarget.com/definition/personal-digital-assistant

+ IC Technology Integration ICs have been commercially available since early 1960s.

Since then, IC design and fabrication technologies have been developed at a phenomenal rate.

More and more transistors are packed in a chip- SSI, MSI, LSI, and VLSI. Currently there are millions of transistors in a single chip. E.g., Intel Core i7 (Quad) processor has 731 million

transistors using 45 nm technology. E.g., Intel Pentium IV processor has 40 million transistors

using 0.13um technology

Integration Scale

Number of Transistors Examples

SSI < 10 Logic gatesMSI 10 – 1,000 Adders, countersLSI 1,000 –

10,000 MultipliersVLSI > 10,000 Microprocessors

+Moore’s Law Maximum number of

transistors on a chip approximately doubles every eighteen months.

This prediction has been accurate for the last four decades.

Downscaling not yields a higher integration density but also a higher transistor drive current for faster switching speeds and lowering the production cost.

+Design StylesFull-Custom ASICs

Some (possibly all) logic cells are customized and all mask layers are customized

When does it make sense?• there are no suitable existing

cell libraries available• existing logic cells are not

fast enough• logic cells are not small

enough• logic cells consume too

much power ASIC is so specialized that

some circuits must be custom designed

Full-custom ASIC Structure

+Design Styles Semicustom ASICs

All logic cells are predesigned (defined in cell library) and some (possibly all) of the mask layers are customized

Types: Standard-cell based and Gate-array-based ASICs

Programmable ASICs All logic cells are

predesigned (defined in cell library) and none of the mask layers are customized

Types: PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array)

+ What is a PLD? Programmable Logic Device is a

circuit which can be configured by the user to perform a logic function.

Most ‘standard’ PLDs consist of an AND array followed by an OR array, either (or both) of which is programmable.

Inputs are fed into the AND array, which performs the desired AND functions and generates product terms. The product terms are then fed

into the OR array. In the OR array, the outputs of the

various product terms are combined to produce the desired outputs.

PLDs standard ICs, available in

standard configurations sold in high volume to many

different customers PLDs may be configured or

programmed to create a part customized to specific application

How to program and erase programming Silicon antifuses SRAM EPROM or EEPROM Flash Memory

+ Field-Programmable Gate Arrays (FPGA) A field-programmable gate array (FPGA) is an

integrated circuit designed to be configured by a customer or a designer after manufacturing—hence "field-programmable".

The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC)

http://en.wikipedia.org/wiki/Integrated_circuit

http://en.wikipedia.org/wiki/Field-programmable

http://en.wikipedia.org/wiki/Hardware_description_language

http://en.wikipedia.org/wiki/Application-specific_integrated_circuit

L-1: INTRODUCTION 2013/2014-1

Field-Programmable Gate Arrays (FPGA)

• FPGA- a step above the PLD in complexity;

it is usually larger and more complex than a PLD- rapidly growing in importance

• Characteristics- none of mask layers are customized

- a method for programming basic cellsand the interconnect

- the core is regular arrayof programmable basic logic cells(combinational + sequential)

- a matrix of programmable interconnectthat surrounds the basic cells

- programmable I/O cells around the core- design turnaround is a few hours

CAD & ASIC Design 18


General FPGA chip architecture

a.k.a. CLB --“configurable logic block”


+Digital IC – Implementation Alternatives

Digital Implementation Alternatives

Standard Components

VLSI Integrated Circruits

System-on-Chip (SoC)

Fixed Applications

Programmable Applications

Reconfigurable ASIC

Structured ASIC

Semi-custom VLSI

Fully-custom VLSI

Logic Gates & Logic Modules

Software programming

Hardware programming

Masked Gate Array (MGA)

Standard Cell-based Design

Prefabricated Reconfigurable

Microchip

CMOSTTLECL

PLAPLDROM

FPGACPLD

Microprocessor & EPROM

Channeled GASea-of-gates

GA Master slice

+ Digital IC – Implementation Alternatives Various implementation of digital logic designs Traditional off-the-shelf IC chips, e.g., SSI and MSI TTL,

perform a fixed operation defined by the device manufacturer.

Application-specific Integrated Circuits (ASICs) are customized ICs whose internal functional operation is user-defined.

CPLD or FPGA requires user hardware programming to perform the desired operation.

The circuit-level design of a VLSI or ASIC chip involves circuit components design, placement, and interconnect routing.

+ Cont… Full-custom VLSI uses circuit elements, e.g.,

transistors and connections as the primitive components. Offers a designer flexibility to optimize circuit characteristics,

placement, and their interconnects, as long as certain design rules are satisfied.

Very time consuming for complex ICs and requires a full knowledge of the operation of the components at the circuit level.

Semicustom design uses a library of circuit-level cells (standard cells) - specified by their functions and characteristics. The use of standard cells at the logic level simplifies the design

process, but reduces design flexibility.

+ Cont… Another

semicustom style is the gate-array design.

Basic components (usually basic gates) are placed on a regular structure within a chip, and the design consists of determining the connections between the gates.

a

b

c

d

c'

b'

a' abd

a'c

c'd

z

y

(z = a + b)

(y = abc + a'c + c'd)Horizontal routing

channel

Vertical routingchannel

+ Cont…A combination of full-custom and semicustom design

is best, where the critical portions of the system are designed using full-custom.

IC TYPE Mask layers customized

Logic cells customized

Fabricationlead time

Full-custom VLSI All Some > 2 monthsStandard Cell-based ASIC

All None ~2 months

Masked Gate Arrays

Some None ~1 to 2 weeks

FPGA / CPLD None None -

+Digital Design Abstraction New techniques must be

used when we move from a small-scale to large-scale designs

Digital designers use two techniques Design abstraction Hierarchical modular

design To facilitate both these

techniques, need electronic design

automation (EDA) or computer-aided design (CAD) tools.

+Design Abstraction At each design level,

the internal details of a complex module may be abstracted away and replaced by a black box view or model.

This model contains virtually all the information needed to deal with the block at the next (lower) level of the design hierarchy.

Design abstraction is crucial in hardware system design.

Hardware designers use these multiple levels of design abstraction,

to meet performance goals for very large designs and reduce design lead times.

+Hierarchical Modular Design Technique

The solution to working in any complex environment is modularization (divide and conquer)

The complexity of design is broken down (divided) into a hierarchy of modules – general (top) to specific (bottom).

Benefits to; Focus on a single

module at a time Create customized

low-level modules for design reuse.

+ Computer-Aided Design (CAD) Electronic Design Automation (EDA) systems.

Makes design process efficient, timely, and economical.

CAD tools are intended to support all phases of a digital design: Description (specification), Design (synthesis), including various optimizations to reduce

cost and improve performance, Verification (by simulation or formal approach) with respect to

its specification.

These three phases typically require several passes to obtain a suitable implementation.

+ HDL (Hardware Description Language) It is replacing

schematic capture

Today, VHDL and Verilog are the two widely used languages.

Schematic Design vs. HDL Design The traditional way is by (schematic capture) -

logic diagram of the system (modules and their interconnects).

An alternative is using hardware-description language (HDL), e.g., VHDL and Verilog are the two languages widely used to model and design digital hardware.

HDLs offer/allow Reduction in development time and allows

more exploration of design alternatives. Description in higher levels of abstraction. A mean to standardize or method of specifying

a design. Representation of sequential logic and

manipulation of data type.

+ Computer-Aided Design (CAD) Electronic Design Automation (EDA) systems. Makes design process efficient, timely, and economical. CAD tools are intended to support all phases of a digital

design: Description (specification), Design (synthesis), including various optimizations to reduce

cost and improve performance, Verification (by simulation or formal approach) with respect

to its specification. These three phases typically require several passes to obtain a

suitable implementation.


CAD Methodology with HDL

Design entry in HDL format (e.g. Altera Quartus II™). HDL behavioural simulation (e.g. Icarus + GTKWave).

Synthesis (e.g., Altera Quartus II, Synopsys FPGA Express),converting the code to a logic netlist file.

Functional simulation to verify for design correctness (e.g.Altera Quartus II).

Implementation - converting netlist file to a physicaldesign to the target implementation technology.

Timing Simulation - the physical layout is verified withtiming information.



Logic Synthesis Flow from RTL to Gate

RTL Description

Translation

UnoptimizedIntermediateRepresentation

LogicOptimization

DesignConstraints

(Timing, Area, Power)

Technology Mappingand Optimization

Gate-level Netlist(Optimized Gate-Level

Representation)

Technology Library(library of available

gates, and leaf-levelcells)




RTL description input to logic synthesis tool after the functionality isverified.

RTL description is converted to an intermediate, internal representation. Allocated internal resources.

Area, timing, and power design constraints not considered.

Optimized to remove redundant logic. Until this step, the designdescription is independent of a specific target technology.

● In technology mapping step, the design is mapped to the desired targettechnology. This is called technology mapping.




● Also, the implementation should satisfy design constraints such as timing,area, and power - technology optimization or technology-dependentoptimization.

● Translation, logic optimization, and technology mapping are performedinternally in the logic synthesis tool and are not visible to the designer.



Evolving Trends

GateIncreasing

Design Densityand Complexity Electronic System

Level - ESL(systemC/

systemverilog)

Behaviouralor Algorithmic

Synthesis

Register-TransferLevel - RTL

(VHDL/ Verilog)

Schematic-based

Simple HDL,PLA-based(eg ABEL)

Count

1 M

500K

100K

10K

1K

1970's 1980's 1990's 2000


lecture1-v1

Documents