lecture no. 7

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1 Lecture No. 7 Computer Logic Design Logic Gates

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Lecture No. 7. Computer Logic Design Logic Gates. NAND Gate. Contraction of NOT-AND Standard logic symbol Output is LOW only when all inputs are HIGH Bubble indicates ACTIVE LOW output Output level is opposite to that of the AND gate. E. NAND Gate. - PowerPoint PPT Presentation

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Page 1: Lecture No. 7

1

Lecture No. 7

Computer Logic Design

Logic Gates

Page 2: Lecture No. 7

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NAND Gate

• Contraction of NOT-AND

• Standard logic symbol

• Output is LOW only when all inputs are HIGH

• Bubble indicates ACTIVE LOW output

• Output level is opposite to that of the AND gate

BAF

NCBAF ....

BAF

NCBAF ....

E

Page 3: Lecture No. 7

3

NAND Gate

• The truth table for a two input NAND gate

InputMiddle Output Output

A B E F

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

Page 4: Lecture No. 7

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NAND Gate

• Timing diagram of NAND gate

t0 t4 t5 t6t1 t2 t3

A

B

F

Page 5: Lecture No. 7

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NAND Gate

• NAND gate application example– Device Failure Alarm System

– When all the fans are working, the input to the NAND gate is 111 and the output is 0

– If any one of the fan stops working, the output of the NAND gate becomes 1, which activates the alarm

ALARM

Page 6: Lecture No. 7

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NAND Gate as Negative-OR

• The truth table for a two input NAND gate looks awfully similar to an OR gate with the inputs inverted.

Input NAND Output

A B F

0 0 1

0 1 1

1 0 1

1 1 0

Input OR Output

A B F

1 1 1

1 0 1

0 1 1

0 0 0

Page 7: Lecture No. 7

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NAND Gate as Negative-OR

Bubble signifies ACTIVE LOW INPUT

Page 8: Lecture No. 7

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NAND Gate as a Universal Gate

• NAND gate can be used to perform all the fundamental gate operations (NOT, AND, OR)– Universal NAND gate

Page 9: Lecture No. 7

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NAND as NOT Gate

Input Output

A B F

0 0 1

0 1 1

1 0 1

1 1 0

Join all the input pins of the NAND gate together

Page 10: Lecture No. 7

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NAND as AND Gate

• Using NAND gate to perform the AND gate operation

• Remember NAND is NOT-AND. What if we inverse this one more level? NOT-(NOT-AND) = AND

• Accomplished by applying a NOT operation (implemented through NAND gate) to the output of the NAND gate

1 2

Page 11: Lecture No. 7

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NAND as OR Gate

• Using NAND gate to perform the OR gate operation

– Can we form NOR gate as well?

Page 12: Lecture No. 7

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NOR Gate

• Contraction of NOT-OR• The standard logic symbol

• Produces a LOW output when one or more of its input is HIGH

• Bubble indicates ACTIVE LOW output• The output logic is opposite to that of the OR gate

BAF

NCBAF ....

Page 13: Lecture No. 7

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NOR Gate

• Truth table for a two input NOR gate

Input Output

A B F

0 0 1

0 1 0

1 0 0

1 1 0

Page 14: Lecture No. 7

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NOR Gate

• Timing diagram of a NOR gate

t0 t4 t5 t6t1 t2 t3

Page 15: Lecture No. 7

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NOR Gate as Negative-AND

• The truth table for a two input NOR gate looks awfully similar to an AND gate with the inputs inverted.

Input NOR Output

A B F

0 0 1

0 1 0

1 0 0

1 1 0

Input AND Output

A B F

1 1 1

1 0 0

0 1 0

0 0 0

Page 16: Lecture No. 7

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NOR Gate as Negative-AND

Bubble signifies ACTIVE LOW INPUT

Page 17: Lecture No. 7

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NOR Gate as a Universal Gate

• NOR gate can be used to perform all the fundamental gate operations (NOT, AND, OR)– Universal NOR gate

Page 18: Lecture No. 7

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NOR as NOT Gate

Input Output

A B F

0 0 1

0 1 0

1 0 0

1 1 0

Join all the input pins of the NOR gate together

Page 19: Lecture No. 7

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NOR as OR Gate

• Using NOR gate to perform the OR gate operation• Remember NOR is NOT-OR. What if we inverse

this one more level? NOT-(NOT-OR) = OR

• Accomplished by applying a NOT operation (implemented through NOR gate) to the output of the NOR gate

Page 20: Lecture No. 7

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NOR as AND Gate

• Using NOR gate to perform the AND gate operation

– Can we form NAND gate as well?

Page 21: Lecture No. 7

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XOR Gate• Exclusive OR (XOR for short)

– Standard logic symbol

– This gate has only two inputs

– Logical expression

– The output is HIGH only when the two the inputs are at opposite logic level

BAF

Page 22: Lecture No. 7

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XOR Gate

• The truth table for XOR Gate

Input Output

A B F

0 0 0

0 1 1

1 0 1

1 1 0

Page 23: Lecture No. 7

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XOR Gate

• Timing diagram of XOR gate

t0 t4 t5 t6t1 t2 t3

Page 24: Lecture No. 7

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XNOR Gate

• Exclusive-NOR (XNOR for short)– Standard logic symbol

This gate has only two inputs

– Logical expression

– The output is LOW only when the two inputs are at opposite logic level

BAF

Page 25: Lecture No. 7

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XNOR Gate

• Truth table for XNOR gate

Input Output

A B F

0 0 1

0 1 0

1 0 0

1 1 1

Page 26: Lecture No. 7

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XNOR Gate

• Timing diagram of XNOR gate

t0 t4 t5 t6t1 t2 t3

Page 27: Lecture No. 7

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Summary of logic gates• Fundamental logic gates

– AND– OR– NOT

• Universal gates– NAND– NOR

• Other gates– XOR– XNOR

• Standard logic symbol• Logical/Boolean expression• Truth table• Application example