Lecture 9

RTL Design Methodology

Sorting Example

2ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 10.2, Design Examples

• P. Chu, FPGA Prototyping by VHDL Examples

Chapter 6, FSMD

Structure of a Typical Digital System

Datapath(Execution

Unit)

Controller(Control

Unit)

Data Inputs

Data Outputs

Control & Status Inputs

Control & Status Outputs

Control Signals

StatusSignals

Hardware Design with RTL VHDL

Pseudocode

Datapath Controller

Block

diagram

Block

diagram

State diagram

or ASM chart

VHDL code VHDL code VHDL code

Interface

Steps of the Design Process

1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, the Controller, and the Top

Unit8. Testbench of the Datapath, the Controller, and the Top Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing

Steps of the Design ProcessPracticed in Class Today

1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, the Controller, and the

Top Unit8. Testbench of the Datapath, the Controller, and the Top

Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing

Sorting

example

Sorting - Required Interface

Sorting

Clock

Resetn

DataInN

DataOut

N

DoneRAdd

L

WrInit

S(0=initialization 1=computations)

Rd

Sorting - Required Interface

Simulation results for the sort operation (1)Loading memory and starting sorting

Simulation results for the sort operation (2)Completing sorting and reading out memory

Before

sorting

During Sorting After

sorting

Address

0

1

2

3

3 3 2 2 1 1 1 1

2 2 3 3 3 3 2 2

4 4 4 4 4 4 4 3

1 1 1 1 2 2 3 4

i=0 i=0 i=0 i=1 i=1 i=2

j=1 j=2 j=3 j=2 j=3 j=3

MiMj

Legend:position of memory

indexed by i

position of memory

indexed by j

Sorting - Example

Pseudocode

for i = 0 tok 2 doA = ; for j = i + 1 tok 1 do

B = Mj ; if B < A then

Mi = B ; Mj = A ; A = Mi ;

endif ; endfor;

endfor;

–

-[load input data]

[read output data]

for i = 0 to 2 doA = Mi ; for j = i + 1 to3 do

B = Mj ; if B < A then

Mi = B ; Mj = A ; A = Mi ;

endif ; endfor;

endfor;

[load input data]

[read output data]

FOR k = 4 FOR any k ≥ 2

Mi

Pseudocode

wait for s=1for i=0 to k-2 do

A = Mi

for j=i+1 to k-1 doB = Mj

if A > B thenMi = BMj = AA = Mi

end ifend for

end forDonewait for s=0go to the beginning

DIN

DOUT

ADDR

WE

CLK

ENCLK RST

ENCLK RST

A>B

01 s

WrInit

Clock

Clock

Clock

Resetn Resetn

Wr

1 0 Bout

EA EB

AgtB

Addr

s

0

10

1

DataIn RAdd

Rd

DataOut

Csel

ENCLK

LDRST

Resetn

ENCLK

LDRST

Resetn

LiEi

Clock

LjEj

Clock

= k-2 = k-1

zi zj

NL

L

LL

N N

N

N

N

ABMux

A B

i

j

Mij

Din

We

0

L

+1

Block diagram of the Datapath

N

Clock Resetn

DataOut

N

WrInit s

Done

Wr

Li

Ei

Lj

Ej

EA

EB

Bout

Csel

Datapath Controller

RAddr

L

zi

Interface with the division into the Datapath and the Controller

DataIn Rd

AgtB

zj