lecture 13 picoblaze i/o & interrupt interface
DESCRIPTION
Lecture 13 PicoBlaze I/O & Interrupt Interface. ECE 448 – FPGA and ASIC Design with VHDL. Required reading. P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface. Output Decoding of Four Output Registers. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/1.jpg)
ECE 448 – FPGA and ASIC Design with VHDL
Lecture 13
PicoBlaze I/O & Interrupt Interface
![Page 2: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/2.jpg)
2ECE 448 – FPGA and ASIC Design with VHDL
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 16, PicoBlaze I/O Interface
Chapter 17, PicoBlaze Interrupt Interface
![Page 3: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/3.jpg)
3
Output Decoding of Four Output Registers
ECE 448 – FPGA and ASIC Design with VHDL
![Page 4: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/4.jpg)
4
Timing Diagram of an Output Instruction
ECE 448 – FPGA and ASIC Design with VHDL
![Page 5: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/5.jpg)
5
Truth Table of a Decoding Circuit
ECE 448 – FPGA and ASIC Design with VHDL
![Page 6: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/6.jpg)
6
Block Diagram of Four Continuous-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL
![Page 7: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/7.jpg)
7
Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL
![Page 8: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/8.jpg)
8
Block Diagram of Four Single-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL
![Page 9: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/9.jpg)
9
FIFO Interface
ECE 448 – FPGA and ASIC Design with VHDL
FIFO
clk rst
8din dout
full empty
write read
clk rst
8
![Page 10: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/10.jpg)
10
Operation of the First-Word Fall-Through FIFO
ECE 448 – FPGA and ASIC Design with VHDL
![Page 11: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/11.jpg)
11
Operation of the “Standard” FIFO
ECE 448 – FPGA and ASIC Design with VHDL
−−−−−
A B C D
![Page 12: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/12.jpg)
12
Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL
![Page 13: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/13.jpg)
13
Timing Diagram of an Interrupt Event
ECE 448 – FPGA and ASIC Design with VHDL
![Page 14: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/14.jpg)
14ECE 448 – FPGA and ASIC Design with VHDL
![Page 15: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/15.jpg)
15
Interrupt Interface with a Single Event
ECE 448 – FPGA and ASIC Design with VHDL
![Page 16: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/16.jpg)
16
Interrupt Interface with Two Requests
ECE 448 – FPGA and ASIC Design with VHDL
![Page 17: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/17.jpg)
17
Time-Multiplexed Seven Segment Display
ECE 448 – FPGA and ASIC Design with VHDL
![Page 18: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/18.jpg)
18
Block Diagram of the Hexadecimal Time-Multiplexing Circuit
ECE 448 – FPGA and ASIC Design with VHDL
![Page 19: Lecture 13 PicoBlaze I/O & Interrupt Interface](https://reader035.vdocuments.site/reader035/viewer/2022062808/56815438550346895dc239f8/html5/thumbnails/19.jpg)
19
Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter
ECE 448 – FPGA and ASIC Design with VHDL