lecture 11: sequential circuit design

Lecture 11:

Sequential Circuit Design

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 2

Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking

CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Sequential Logic

11: Sequential Circuits 3


Sequencing Combinational logic

– output depends on current inputs Sequential logic

– output depends on current and previous inputs– Requires separating previous, current, future– Called state or tokens– Ex: FSM, pipeline

CL

clk

in out

clk clk clk

CL CL

PipelineFinite State Machine


Sequencing Cont. If tokens moved through pipeline at constant speed,

no sequencing elements would be necessary Ex: fiber-optic cable

– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– But dispersion sets min time between pulses

This is called wave pipelining in circuits In most circuits, dispersion is high

– Delay fast tokens so they don’t catch slow ones.


Sequencing Overhead Use flip-flops to delay fast tokens so they move

through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay

– Called sequencing overhead Some people call this clocking overhead

– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence


Sequencing Elements Latch: Level sensitive

– a.k.a. transparent latch, D latch Flip-flop (or Register): edge triggered

– A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams

– Transparent– Opaque– Edge-trigger

D

Flo

p

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)

D

Flo

p

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)


Latch versus Register Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

Register

stores data when clock rises

Clk Clk

D D

Q Q


Latches



Timing Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q


Characterizing Timing



Latch Design Pass Transistor Latch Pros

+ Tiny+ Low clock load

Cons– Vt drop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion input

D Q

Used in 1970’s


Latch Design Transmission gate

+ No Vt drop

- Requires inverted clock D Q


Latch Design Inverting buffer

+ Restoring

+ No backdriving

+ Fixes either• Output noise sensitivity• Or diffusion input

– Inverted output

D

XQ

D Q


Latch Design Tristate feedback

+ Static– Backdriving risk

Static latches are now essential

because of leakage

QDX


Latch Design Buffered input

+ Fixes diffusion input

+ Noninverting

QDX


Latch Design Buffered output

+ No backdriving

Widely used in standard cells

+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading

Q

D X


Latch Design Datapath latch

+ smaller

+ faster

- unbuffered input

Q

D X


Flip-Flop Design Flip-flop is built as pair of back-to-back latches

D Q

X

D

X

Q

Q


Enable Enable: ignore clock when en = 0

– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skew

D Q

Latc

h

D Q

en

en

Latc

hDQ

0

1

en

Latc

h

D Q

en

DQ

0

1

enD Q

en

Flo

p

Flo

p

Flo

p

Symbol Multiplexer Design Clock Gating Design


Reset Force output low when reset asserted Synchronous vs. asynchronous

D

Q

Q

reset

D

Q

D

reset

Q

Dreset

reset

reset

Synchronous R

esetA

synchronous Reset

Sym

bol Flo

p

D Q

Latc

h

D Q

reset reset

Q

reset


Set / Reset Set forces output high when enabled

Flip-flop with asynchronous set and reset

D

Q

reset

setreset

set


Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches

Flip-F

lopsF

lop

Latc

h

Flo

p

clk

1

2

p

clk clk

Latc

h

Latc

h

p p

1 12

2-Phase T

ransparent LatchesP

ulsed Latches

Combinational Logic

CombinationalLogic

CombinationalLogic

Combinational Logic

Latc

h

Latc

h

Tc

Tc/2

tnonoverlap tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1


Timing Diagrams

Flo

p

A

Y

tpdCombinational

LogicA Y

D Q

clk clk

D

Q

Latc

h

D Q

clkclk

D

Q

tcd

tsetup thold

tccq

tpcq

tccq

tsetup tholdtpcq

tpdqtcdq

tpdLogic Prop. Delay

tcdLogic Cont. Delay

tpcqLatch/Flop Clk->Q Prop. Delay

tccqLatch/Flop Clk->Q Cont. Delay

tpdqLatch D->Q Prop. Delay

tcdqLatch D->Q Cont. Delay

tsetupLatch/Flop Setup Time

tholdLatch/Flop Hold Time

Contamination and Propagation Delays


Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

setup

sequencing overhead

pd c pcqt T t t


Max Delay: 2-Phase Latches

Tc

Q1

L1

1

2

L2 L3

1 12

CombinationalLogic 1


Q2 Q3D1 D2 D3

Q1

D2

Q2

D3

D1

tpd1

tpdq1

tpd2

tpdq2

1 2

sequencing overhead

2pd pd pd c pdqt t t T t


Max Delay: Pulsed Latches

Tc

Q1 Q2D1 D2

Q1

D2

D1

p

p p

Combinational LogicL1 L2

tpw

(a) tpw > tsetup

Q1

D2

(b) tpw < tsetup

Tc

tpd

tpdq

tpcq

tpd tsetup

setup

sequencing overhead

max ,pd c pdq pcq pwt T t t t t


Min-Delay: Flip-Flops

holdcd ccqt t t CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq


Min-Delay: 2-Phase Latches

1, 2 hold nonoverlapcd cd ccqt t t t t CL

Q1

D2

D2

Q1

1

L1

2

L2

1

2

tnonoverlap

tcd

thold

tccq

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.

But a flop is made of two latches!


Min-Delay: Pulsed Latches

holdcd ccq pwt t t t CL

Q1

D2

Q1

D2

p tpw

p

L1

p

L2tcd

thold

tccq

Hold time increased by pulse width


Itanium 2 ALU



Combinational Logic Delays

Element Propagation Delay Contamination Delay

Adder 590 ps 100 ps

Result Mux 60 ps 35 ps

Early Bypass Mux 110 ps 95 ps

Middle Bypass Mux 80 ps 55 ps

Late Bypass Mux 70 ps 45 ps

2 mm Wire 100 ps 65 ps



Time Borrowing In a flop-based system:

– Data launches on one rising edge– Must setup before next rising edge– If it arrives late, system fails– If it arrives early, time is wasted– Flops have hard edges

In a latch-based system– Data can pass through latch while transparent– Long cycle of logic can borrow time into next– As long as each loop completes in one cycle


Time Borrowing Example

Latc

h

Latc

h

Latc

h

Combinational LogicCombinational

Logic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(a)

(b)

Latc

h

Latc

hCombinational Logic Combinational

Logic

Loops may borrow time internally but must complete within the cycle

1

2

1 1

1

2

2


How Much Borrowing?

Q1

L1

1

2

L2

1 2

Combinational Logic 1Q2D1 D2

D2

Tc

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

borrow setup nonoverlap2cT

t t t

2-Phase Latches

borrow setuppwt t t

Pulsed Latches


Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time

– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing


Skew: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tskew

CL

Q1

D2

F1

clk

Q1

F2

clk

D2

clk

tskew

tsetup

tpcq

tpdq

tcd

thold

tccq

setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t


Skew: Latches

Q1

L1

1

2

L2 L3

1 12



Q2 Q3D1 D2 D3

sequencing overhead

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

2

,

2

pd c pdq

cd cd ccq

c

t T t

t t t t t t

Tt t t t

2-Phase Latches

setup skew

sequencing overhead

hold skew

borrow setup skew

max ,pd c pdq pcq pw

cd pw ccq

pw

t T t t t t t

t t t t t

t t t t

Pulsed Latches


Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important

– No tools to analyze clock skew An easy way to guarantee hold times is to use 2-

phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2)


Safe Flip-Flop Past years used flip-flop with nonoverlapping clocks

– Slow – nonoverlap adds to setup time– But no hold times

In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk

D

X

Q

Q


Adaptive Sequencing

Designers include timing margin– Voltage– Temperature– Process variation– Data dependency– Tool inaccuracies

Alternative: run faster and check for near failures– Idea introduced as “Razor”

• Increase frequency until at the verge of error• Can reduce cycle time by ~30%

D Q

ERR

p

p

D

Q

X

ERR

X


Conventional CMOS Latches



More CMOS Latches



Clocked CMOS Latches Sometimes called C2MOS Actually, similar to (d) in that it is tristate



Conventional CMOS Flip-Flops



CMOS Flip-Flops This design has a potential race condition. Is more likely if there is skew between the two

phases of the clock. One alternative is NORA (NO Race) flip-flop. The other alternative is to use non-overlapping

clocks.



NORA Flip-flops



Pulse Generators



Pulsed Latches The Naffziger pulsed latch is used in Itanium 2

processors. It consists of the latch from (k) and the generator from (b). The pulse width is 1/6 the clock cycle.

The pulse generator of (d) is used in the NEC RISC processor.

Note that pulses are very fast and have to be distributed in the latch.

The Partovi pulsed latch (used on the AMD K6 and Athlon) builds the pulse generator into the latch.



Pulsed Latches



Resettable Latches and Flip-flops

There are two types of reset:– Asynchronous– Synchronous

Settable latches and flip-flops force the output high rather than low.



Resettable Latches and Flip-flops



Asynchronous Set and Reset



Enabled Latches and Flip-flops



Logic in Latches The sequencing overhead can be reduced by

incorporating logic into latches. The DEC Alpha 21164 used a whole assortment of

such latches.



Klass Semidynamic FF (SDFF)

A cross between pulsed latch and a flip-flop. Used in Sun UltraSparc III along with built in logic.



SDFF Similar to the Partovi pulsed latch. However, it uses a dynamic NAND gate. Faster than the Partovi pulsed latch. Worse skew tolerance and time borrowing capability.



Differential Flip-flops



Differential Flip-flops

The design in (a) was used in the Alpha 21164. The SR latch formed by the NAND gates is just a

salve and can be replaced by inverters if necessary. The StrongArm 110 processor adds the weak nMOS

transistor to reduce the risk when the inputs switch while the clock is high.

The AMD K6 uses the design in (b) at the interface between static and domino logic.



Dual Edge Triggered FFs

DET flip flops have a similar thoroughput at half the clock frequency.



DET FFs Zhao implicitly pulsed DET FF.



Radiation Hardened FFs



Some Design Guides Dynamic latches and registers have been avoided

since the 0.35 m technology node.– Use static latches and register.

Include provisions for testing– We will study these later.

Clock distribution, especially multiple phases are problematic.– We will study later.

Unless required performance is at the cutting edge, use registers.



Some Design Guides Pulsed latches are best in terms of performance.

– Remember that they have long hold times. Extra circuitry may be necessary for short logic

paths.



Characterizing Delays



Characterizing Delays The set-up time cannot be crisply defined. If the data changes slightly less than a set-up time

before the clock edge, the register will still capture the correct value, but its clock-Q delay will be high.

Note that tDQ has a minimum when the slope of tCQ is -1.

tsetup is defined as the tDC at this point.

The propagation delay is the tCQ at this point.

The contamination delay tccq is the minimum tCQ that occurs when the input arrives early.

The hold time is the minimum delay from clock to D11: Sequential Circuits 67

€

tDQ = tDC + tCQ


Characterizing Delays The aperture width, ta is the width of the window

around the clock edge during which the data must not transition if the register is to produce the correct output with a propagation delay less than tpcq.


€

tar = tsetup1 + thold 0

taf = tsetup 0 + thold1


Characterizing Delays If the data arrives before the clock rises (tDCr > 0), it

must wait for the clock. In this region, tCrQ is nearly constant and tDQ

increases as the data arrives earlier. If the data arrives after the clock rises, tDQ is

essentially independent of arrival time. The data must set up before the falling edge of the

clock. If the data arrives too close to the falling edge, tDQ

increases.



Characterizing Delays Choose the setup time before the knee of the curve,

for example 5% greater than its minimum value. Pulsed latches have different definitions, but they

can be converter to ordinary latches by adding or subtracting pulse widths.


€

tsetup −virtual = tsetup − tpw

tpcq −virtual = tpdq + t pw − tsetup( )

tpdq −virtual = tsetup −virtual + t pcq −virtual = t pdq

thold −virtual = thold + tpw


Delay Trade-offs



State Retention Registers



Level Conversion



Design Margins Designers derate their circuits by about 30% to cope

with variations. Adaptive sequential elements seek to reduce this

margin. Dynamic voltage scaling

– Precharacterize the circuit– Canary circuit– Double sampling the input



Adaptive Sequencing



Adaptive Sequencing (a) shows the conceptual diagram of a razor flip-flop,

while (b) is the timing diagram. The razor flip-flop has the drawback that it may

become metastable if D changes during the aperture.

An improvement is double sampling with time borrowing (DSTB).

(d) shows the Razor II pulsed latch.



Synchronizers A synchronizer is a circuit that accepts an input that

can change at arbitrary times and produces an output aligned to its clock.

This is impossible to do in a finite time.



Metastability



Metastability The cross-coupled inverters behave like an amplifier

with gain G when A is near the metastable voltage Vm.

The delay can be modeled with an RC network. Let the initial voltage be A and a small offset from

the metastable point be a(0).


€

A 0( ) = Vm + a 0( )

Ga t( ) − a t( )R

= Cda t( )

dt

a t( ) = a 0( )etτ s

τ s ≡RC

G −1


Metastability Assume that the node reaches a legal logic level

when The time to reach this level is

Note that the speed is given by the RC time constant.

High GBW is required.


€

a t( ) ≥ ΔV

€

tDQ = τ s ln ΔV − ln a 0( )[ ]

€

P tDQ > ′ t ( ) =T0

Tc

e− ′ t

τ s


Synchronizers



Synchronizers The probability of a synchronizer failure is

The mean time between failures is


€

P failure( ) = NT0

Tc

e−

Tc −tsetup( )

τ s

€

MTBF =1

P failure( )=

Tce

Tc −tsetup

τ s

NT0


Degrees of SynchronyClassification Periodic f Description

Synchronous Yes 0 0 Signal has same frequency and phase as clock.Example: register to register on chip.

Mesosynchronous Yes Constant 0 Signal has same frequency, but is out of phase with clock. Safe to sample by delaying.Example: chip tp chip where both chips are using the same clock.

Plesiosynchronous

Yes Variesslowly

Small Signal has nearly the same frequency. Phase drifts slowly with time. Safe to sample signal if it is delayed by a variable, but predictable amount.Example: Board to board with same frequency but different crystals.

Periodic Yes Variesrapidly

Large Signal is periodic at arbitrary frequency. Board to board with different crystals.

Asynchronous No Unknown Unknown Signal changes arbitrarily.11: Sequential Circuits 88


Asynchronous Domains



Two-Phase Handshake



Arbiters An arbiter decides which of the two inputs came first.



Pipelining



Wave Pipelining



Schmitt Triggers



Noise Suppression



CMOS Schmitt Trigger



Schmitt Trigger Simulated VTC

2.5

VX (V) VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis.The effect of varying the ratio of the

PMOS device M4 . The width isk* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

Vx (V)

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5


CMOS Schmitt Trigger 2



Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T


Transition-Triggered Monostable

DELAY

td

In

Outtd


Monostable Trigger (RC-based)VDD

InOutA B

C

R

In

B

Outt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.


Astable Multivibrators (Oscillators)



Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC


Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pHL (

nsec

)

propagation delay as a functionof control voltage


Differential Delay Element and VCO

in2

two stage VCO

v1

v2

v3

v4

Vctrl

Vo2 Vo1

in1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

20.51.5

V1 V2 V3 V4

time (ns)2.5 3.5


Pitfalls and Fallacies Incompletely reporting flip-flop delay. Failing to check hold times. Choosing a sequencing method too late in the

design. Failing to synchronize asynchronous inputs. Building faulty synchronizers.



Summary Flip-Flops:

– Very easy to use, supported by all tools 2-Phase Transparent Latches:

– Lots of skew tolerance and time borrowing Pulsed Latches:

– Fast, some skew tol & borrow, hold time risk

lecture 11: sequential circuit design

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