lecture 10 processor microarchitecture (part 1)
TRANSCRIPT
Xuan ‘Silvia’ Zhang Washington University in St. Louis
http://classes.engineering.wustl.edu/ese566/
Lecture 10 Processor Microarchitecture (Part 1)
Key Concepts in Computer Architecture
• Transaction latency – the time to complete a single transaction
• Execution time/total latency – the time to complete a sequence of transactions
• Throughput – the number of transaction executed per unit time
2
Analyzing Processor Performance
3
Analyzing Processor Performance
4
Transactions and Steps
• Each instruction as a transaction • Executing a transaction involves a sequence of steps
5
Microarchitecture: Control/Datapath Split
6
7
PARCv1 Single-Cycle Processor
8
High-level Idea for Single-Cycle Processors
9
Single-Cycle Datapath
• Implement ADDU instruction • Implement ADDIU instruction
10
Single-Cycle Datapath
• Implement ADDU instruction • Implement ADDIU instruction
11
Adding MUL Instruction
12
Adding LW and SW Instructions
13
Adding J Instruction
14
Adding JAL and JR Instructions
15
Adding BNE Instruction
16
Quiz: Adding a New Auto-Incrementing Load Instruction
17
Single-Cycle Processor Control Unit
18
Estimating Cycle Time—Longest Critical Path
19
20
PARCv1 FSM Processor
21
22
FSM Processor Datapath
• Implement fetch sequence
23
FSM Processor Datapath
• Implement ADDU sequence
24
Full Datapath for PARCv1 FSM Processor
25
26
27
Adding a Complex Instruction
28
Quiz: Adding a New Auto-Incrementing Load Instruction
29
Questions?
Comments?
Discussion?
30
Acknowledgement
Cornell University, ECE 4750
31