lecture 2: mips processor example - walla walla …curt.nelson/engr434/lecture/2 mips... · 2: mips...
TRANSCRIPT
![Page 1: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/1.jpg)
Lecture 2: MIPS Processor Example
![Page 2: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/2.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 2
Outline q Design Partitioning q MIPS Processor Example
– Architecture – Microarchitecture – Logic Design – Circuit Design – Physical Design
q Fabrication, Packaging, Testing
![Page 3: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/3.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 3
Activity 2 q Sketch a stick diagram for a 4-input NOR gate
AVDD
GND
B C
Y
D
![Page 4: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/4.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 4
Coping with Complexity q How to design System-on-Chip?
– Many millions (even billions!) of transistors – Tens to hundreds of engineers
q Structured Design q Design Partitioning
![Page 5: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/5.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 5
Structured Design q Hierarchy: Divide and Conquer
– Recursively divide system into modules q Regularity
– Reuse modules wherever possible – Ex: Standard cell library
q Modularity: well-formed interfaces – Allows modules to be treated as black boxes
q Locality – Physical and temporal
![Page 6: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/6.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 6
Design Partitioning q Architecture: User’s perspective, what does it do?
– Instruction set, registers – MIPS, x86, Alpha, PIC, ARM, …
q Microarchitecture – Single cycle, multcycle, pipelined, superscalar?
q Logic: how are functional blocks constructed – Ripple carry, carry lookahead, carry select adders
q Circuit: how are transistors used – Complementary CMOS, pass transistors, domino
q Physical: chip layout – Datapaths, memories, random logic
![Page 7: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/7.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 7
Gajski Y-Chart
![Page 8: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/8.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 8
MIPS Architecture q Example: subset of MIPS processor architecture
– Drawn from Patterson & Hennessy q MIPS is a 32-bit architecture with 32 registers
– Consider 8-bit subset using 8-bit datapath – Only implement 8 registers ($0 - $7) – $0 hardwired to 00000000 – 8-bit program counter
q You’ll build this processor in the labs – Illustrate the key concepts in VLSI design
![Page 9: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/9.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 9
Instruction Set
![Page 10: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/10.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 10
Instruction Encoding q 32-bit instruction encoding
– Requires four cycles to fetch on 8-bit datapath
format example encoding
R
I
J
0 ra rb rd 0 funct
op
op
ra rb imm
6
6
6
65 5 5 5
5 5 16
26
add $rd, $ra, $rb
beq $ra, $rb, imm
j dest dest
![Page 11: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/11.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 11
Fibonacci (C) f0 = 1; f-1 = -1 fn = fn-1 + fn-2
f = 1, 1, 2, 3, 5, 8, 13, …
![Page 12: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/12.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 12
Fibonacci (Assembly) q 1st statement: n = 8 q How do we translate this to assembly?
![Page 13: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/13.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 13
Fibonacci (Binary) q 1st statement: addi $3, $0, 8 q How do we translate this to machine language?
– Hint: use instruction encodings below
format example encoding
R
I
J
0 ra rb rd 0 funct
op
op
ra rb imm
6
6
6
65 5 5 5
5 5 16
26
add $rd, $ra, $rb
beq $ra, $rb, imm
j dest dest
![Page 14: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/14.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 14
Fibonacci (Binary) q Machine language program
![Page 15: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/15.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 15
MIPS Microarchitecture q Multicycle µarchitecture ( [Paterson04], [Harris07] )
![Page 16: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/16.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 16
Multicycle Controller
PCWritePCSource = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCondPCSource = 01
ALUSrcA =1ALUSrcB = 00ALUOp= 10
RegDst = 1RegWrite
MemtoReg = 0MemWriteIorD = 1
MemReadIorD = 1
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst=0RegWrite
MemtoReg=1
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
MemReadALUSrcA = 0IorD = 0IRWrite3
ALUSrcB = 01ALUOp = 00PCWrite
PCSource = 00
Instruction fetch
Instruction decode/register fetch
Jumpcompletion
BranchcompletionExecution
Memory addresscomputation
Memoryaccess
Memoryaccess R-type completion
Write-back step
(Op= 'LB
') or(Op
= 'SB') (Op
= R-typ
e)
(Op= 'BEQ')
(Op='J')
(Op = 'S B')
(Op='LB')
7
0
4
121195
1086
Reset
MemReadALUSrcA = 0IorD = 0IRWrite2
ALUSrcB = 01ALUOp = 00PCWrite
PCSource = 00
1MemReadALUSrcA = 0IorD = 0IRWrite1
ALUSrcB = 01ALUOp = 00PCWrite
PCSource = 00
2MemReadALUSrcA = 0IorD = 0IRWrite0
ALUSrcB = 01ALUOp = 00PCWrite
PCSource = 00
3
![Page 17: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/17.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 17
Logic Design q Start at top level
– Hierarchically decompose MIPS into units q Top-level interface
reset
ph1
ph2
crystaloscillator
2-phaseclockgenerator MIPS
processor adr
writedata
memdata
externalmemory
memreadmemwrite
8
8
8
![Page 18: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/18.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 18
Block Diagram
![Page 19: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/19.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 19
Hierarchical Design mips
controller alucontrol datapath
standardcell library
bitslice zipper
alu
and2
flopinv4x
mux2
mux4
ramslice
fulladder
nand2nor2
or2
inv
tri
![Page 20: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/20.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 20
HDLs q Hardware Description Languages
– Widely used in logic design – Verilog and VHDL
q Describe hardware using code – Document logic functions – Simulate logic before building – Synthesize code into gates and layout
• Requires a library of standard cells
![Page 21: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/21.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 21
Verilog Example module fulladder(input a, b, c, output s, cout); sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule module carry(input a, b, c, output cout) assign cout = (a&b) | (a&c) | (b&c); endmodule
a b
c
s
cout carrysum
s
a b c
cout
fulladder
![Page 22: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/22.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 22
Circuit Design q How should logic be implemented?
– NANDs and NORs vs. ANDs and ORs? – Fan-in and fan-out? – How wide should transistors be?
q These choices affect speed, area, power q Logic synthesis makes these choices for you
– Good enough for many applications – Hand-crafted circuits are still better
![Page 23: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/23.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 23
Example: Carry Logic q assign cout = (a&b) | (a&c) | (b&c);
ab
ac
bc
cout
x
y
z
g1
g2
g3
g4
Transistors? Gate Delays?
a b
c
c
a b
b
a
a
b
coutcn
n1 n2
n3
n4
n5 n6
p6p5
p4
p3
p2p1
i1
i3
i2
i4
![Page 24: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/24.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 24
Gate-level Netlist module carry(input a, b, c, output cout)
wire x, y, z;
and g1(x, a, b); and g2(y, a, c); and g3(z, b, c); or g4(cout, x, y, z);
endmodule
ab
ac
bc
cout
x
y
z
g1
g2
g3
g4
![Page 25: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/25.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 25
Transistor-Level Netlist
a b
c
c
a b
b
a
a
b
coutcn
n1 n2
n3
n4
n5 n6
p6p5
p4
p3
p2p1
i1
i3
i2
i4
module carry(input a, b, c, output cout)
wire i1, i2, i3, i4, cn;
tranif1 n1(i1, 0, a); tranif1 n2(i1, 0, b); tranif1 n3(cn, i1, c); tranif1 n4(i2, 0, b); tranif1 n5(cn, i2, a); tranif0 p1(i3, 1, a); tranif0 p2(i3, 1, b); tranif0 p3(cn, i3, c); tranif0 p4(i4, 1, b); tranif0 p5(cn, i4, a); tranif1 n6(cout, 0, cn); tranif0 p6(cout, 1, cn);
endmodule
![Page 26: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/26.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 26
SPICE Netlist .SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF .ENDS
![Page 27: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/27.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 27
Physical Design q Floorplan q Standard cells
– Place & route q Datapaths
– Slice planning q Area estimation
![Page 28: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/28.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 28
MIPS Floorplan
![Page 29: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/29.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 29
MIPS Layout
![Page 30: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/30.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 30
Standard Cells q Uniform cell height q Uniform well height q M1 VDD and GND rails q M2 Access to I/Os q Well / substrate taps q Exploits regularity
![Page 31: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/31.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 31
Synthesized Controller q Synthesize HDL into gate-level netlist q Place & Route using standard cell library
![Page 32: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/32.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 32
Pitch Matching q Synthesized controller area is mostly wires
– Design is smaller if wires run through/over cells – Smaller = faster, lower power as well!
q Design snap-together cells for datapaths and arrays – Plan wires into cells – Connect by abutment
• Exploits locality • Takes lots of effort
A A A A
A A A A
A A A A
A A A A
B
B
B
B
C C D
![Page 33: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/33.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 33
MIPS Datapath q 8-bit datapath built from 8 bitslices (regularity) q Zipper at top drives control signals to datapath
![Page 34: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/34.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 34
Slice Plans q Slice plan for bitslice
– Cell ordering, dimensions, wiring tracks – Arrange cells for wiring locality
![Page 35: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/35.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 35
Area Estimation q Need area estimates to make floorplan
– Compare to another block you already designed – Or estimate from transistor counts – Budget room for large wiring tracks – Your mileage may vary; derate by 2x for class.
![Page 36: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/36.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 36
Design Verification q Fabrication is slow & expensive
– MOSIS 0.6µm: $1000, 3 months – 65 nm: $3M, 1 month
q Debugging chips is very hard – Limited visibility into operation
q Prove design is right before building! – Logic simulation – Ckt. simulation / formal verification – Layout vs. schematic comparison – Design & electrical rule checks
q Verification is > 50% of effort on most chips!
Specification
ArchitectureDesign
LogicDesign
CircuitDesign
PhysicalDesign
=
=
=
=
Function
Function
Function
FunctionTimingPower
![Page 37: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/37.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 37
Fabrication & Packaging q Tapeout final layout q Fabrication
– 6, 8, 12” wafers – Optimized for throughput,
not latency (10 weeks!) – Cut into individual dice
q Packaging – Bond gold wires from die I/O pads to package
![Page 38: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/38.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 38
Testing q Test that chip operates
– Design errors – Manufacturing errors
q A single dust particle or wafer defect kills a die – Yields from 90% to < 10% – Depends on die size, maturity of process – Test each part before shipping to customer
![Page 39: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/39.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 39
Custom vs. Synthesis q 8-bit Implementations
![Page 40: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/40.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 40
MIPS R3000 Processor q 32-bit 2nd generation commercial processor (1988) q Led by John Hennessy (Stanford, MIPS Founder) q 32-64 KB Caches q 1.2 µm process q 111K Transistors q Up to 12-40 MHz q 66 mm2 die q 145 I/O Pins q VDD = 5 V q 4 Watts q SGI Workstations
http://gecko54000.free.fr/?documentations=1988_MIPS_R3000
![Page 41: Lecture 2: MIPS Processor Example - Walla Walla …curt.nelson/engr434/lecture/2 mips... · 2: MIPS Processor Example CMOS VLSI Design 4th ... – Microarchitecture – Logic Design](https://reader031.vdocuments.site/reader031/viewer/2022021901/5b7b4e627f8b9adb4c8c5a90/html5/thumbnails/41.jpg)
CMOS VLSI Design CMOS VLSI Design 4th Ed. 2: MIPS Processor Example 41
Summary q Design Partitioning q MIPS Processor Example
– Architecture – Microarchitecture – Logic Design – Circuit Design – Physical Design
q Fabrication, Packaging, Testing