This course is basically about silicon chip fabrication,

the technologies used to manufacture ICs.

INTRODUCTION

It is not sufficient any longer to think a silicon oxidation simply a chemical reaction between silicon and oxygen that grows SiO2.Today we must understand that detailed bonding between silicon and oxygen atoms and kinetics that drive this reaction on atomic basis.

EE439/539

IC Fabrication Technology: Brief History

• 1940s - setting the stage - the initial inventions that made integrated circuits possible.

• In 1945, Bell Labs established a group to develop a semiconductor replacement for the vacuum tube. The group led by William Shockley, included, John Bardeen, Walter Brattain and others.

• In 1947 Bardeen and Brattain and Shockley succeeded in creating an amplifying circuit utilizing a point-contact "transfer resistance" device that later became known as a transistor.

• In 1951 Shockley developed the junction transistor, a more practical form of the transistor.

• By 1954 the transistor was an essential component of the telephone system and the transistor first appeared in hearing aids followed by radios.

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The transistor invented at Bell lab. in 1947

In 1956 the importance of the invention of the transistor by Bardeen, Brattain and Shockley was recognized by the Nobel Prize in physics. 

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1958 - Integrated circuit invented September 12th 1958 Jack Kilby at Texas instrument had built a simple oscillator IC with five integrated components (resistors, capacitors, distributed capacitors and transistors)In 2000 the importance of the IC was recognized when Kilby shared the Nobel prize in physics with two others. Kilby was sited by the Nobel committee "for his part in the invention of the integrated circuit

a simple oscillator IC

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1959 - Planar technology invented

• Kilby's invention had a serious drawback, the individual circuit elements were connected together with gold wires making the circuit difficult to scale up to any complexity.

• By late 1958 Jean Hoerni at Fairchild had developed a structure with N and P junctions formed in silicon. Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions.

• In 1959, Robert Noyce also of Fairchild had the idea to evaporate a thin metal layer over the circuits created by Hoerni's process.

• The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Planar technology set the stage for complex integrated circuits and is the process used today. 

Planar technology

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IC Fabrication Technology: History (cont.)• 1960 - Epitaxial deposition developed

• Bell Labs developed the technique of Epitaxial Deposition whereby a single crystal layer of material is deposited on a crystalline substrate. Epitaxial deposition is widely used in bipolar and sub-micron CMOS fabrication.  

• 1960 - First MOSFET fabricated

• Kahng at Bell Labs fabricates the first MOSFET. • 1961 - First commercial ICs

• Fairchild and Texas Instruments both introduce commercial ICs. • 1962 - Transistor-Transistor Logic invented

• 1962 - Semiconductor industry surpasses $1-billion in sales • 1963 - First MOS IC

• RCA produces the first PMOS IC.

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1963 - CMOS invented • Frank Wanlass at Fairchild Semiconductor originated and published the idea

of complementary-MOS (CMOS).

• It occurred to Wanlass that a complementary circuit of NMOS and PMOS would draw very little current. Initially Wanlass tried to make a monolithic solution, but eventually he was forced to prove the concept with discrete devices.

• Enhancement mode NMOS transistors were not yet available and so Wanlass was used a depletion mode device biased to the off-state.

• Amazingly CMOS shrank standby power by six orders of magnitude over equivalent bipolar or PMOS logic gates.

• On June 18, 1963 Wanlass applied for a patent. On December 5th 1967 Wanlass was issued U.S. Patent # 3,356,858 for "Low Stand-By Power Complementary Field Effect Circuitry".

• CMOS forms the basis of the vast majority of all high density ICs manufactured today.

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1965 - Moore's law

• In 1965 Gordon Moore, director of research and development at Fairchild Semiconductor wrote a paper for Electronics entitled "Cramming more components onto integrated circuits".

• In the paper Moore observed that "The complexity for minimum component cost has increased at a rate of roughly a factor of two per year". This observation became known as Moore's law, the number of components per IC double every year.

• Moore's law was later amended to, the number of components per IC doubles every 18 months.

• Moore's law hold to this day.

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1971 - Microprocessor invented • The combination of the Busicom (Japanese calculator

company) and the Intel came together and by 1971 the 4004 the first 4-bit microprocessor was in production. The 4004 processor required roughly 2,300 transistors to implement, used a silicon gate PMOS process with 10µm linewidths, had a 108KHz clock speed. In 1974 Intel introduced the 8080, the first commercially successful microprocessor.

• 1972 - Intel 8008

• The 8008 was the 8 bit successor to the 4004 and was used in the Mark-8 computer, one of the first home computers.

• The 8008 had 3,500 transistors, a 200kHz clock speed

and a 15.2mm2 die size.

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1993-first Pentium processor invented

• 1993 - Intel Pentium I• The Pentium is the first processor from Intel capable of executing more than 1 instruction per clock cycle. The Pentium

was manufactured in a silicon gate BiCMOS process with 0.8µm linewidths, required 18 mask layers and had 1 polysilicon layer and 3 metal layers, the Pentium had 3.1 million transistors, a 60 to 66MHz clock speed and a 264mm2 die size.

• 1994 - Semiconductor Industry passes $100-billion.

• 1994 - 64Mbit DRAM

• The 64Mbit DRAM was produced on a CMOS process with 3 to 5 polysilicon layers, 2 to 3 metal layers and 0.35µm minimum features. The resulting product had a 1.5µm2 memory cell size.

• 1997 - Intel Pentium II• The Pentium II was manufactured in a silicon gate CMOS process with 0.35µm linewidths, required 16 mask layers and

had 1 polysilicon layer and 4 metal layers, the Pentium II had 7.5 million transistors, a 233 to 300MHz clock speed and a 209mm2 die size.

• 1998 - 256Mbit DRAM

• The 256Mbit DRAM was produced on a CMOS process with 4 to 5 polysilicon layers, 2 to 3 metal layers and 0.25µm minimum features.The product had a die size of approximately 204mm2.

• 1999 - Intel Pentium III• The Pentium III returned to a more standard PGA package and integrated the cache on chip. The Pentium III was

manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium III had 28 million transistors, a 500 to 900MHz clock speed and a 140mm2 die size.

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2000 - Intel Pentium 4 • The Pentium 4 introduced

an integer unit running at twice the processor speed. The Pentium 4 was manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium 4 had 42 million transistors, a 1,400 to 2,500MHz clock speed and a 224mm2 die size

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Die size trends12

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Cell Construction Layers Product Process

type Line width (µm)

Transis tors (K)

Mask layers Proc/bus

(bits) Clock (MHz)

Voltage (V)

Cache (Kbits) Poly Metal

Die size (mm

) 1971 4004 PMOS 10 2.3 --- 4 0.108 12 0 1 1 13.5 1972 8008 PMOS 10 3.5 --- 8 0.2 12 0 1 1 15.2 1974 8080 NMOS 6.0 6.0 --- 8 2 12 0 1 1 20.0 1976 8085 NMOS 3.0 6.5 --- 8 0.37 5 0 1 1 20.0 1978 8086 NMOS 3.0 29 --- 16 5-10 5 0 1 1 28.6 1979 8088 NMOS 3.0 29 --- 16/8 5-8 5 0 1 1 28.6 1982 80286 CMOS 1.5 134 --- 16 6-12 5 0 1 2 68.7 1985 80386DX CMOS 1.5 275 10 32 16-33 5 0 1 2 104.0 1989 80486DX CMOS 1.0 1,200 12 32 25-50 5 0 1 3 163.0 1992 80486DX2 CMOS 0.8 1,200 --- 32 50-66 5 0 1 3 81.0 1993 Pentium BiCMOS 0.8 3,100 18 32/64 60-66 5 0 1 3 264.0

1994 80486DX4 CMOS 0.5 1,600 32 75-100 5 0 1 3

1995 Pentium Pro BiCMOS 0.35 5,500 20 32/64 150-

200 --- 0 1 4 310.0

1997 Pentium II CMOS 0.35 7,500 16 32/64 233-300 --- 0 1 4 209.0

1998 Celeron CMOS 0.25 19,000 19 32/64 300-333 --- 128 1 5

1999 Pentium III CMOS 0.18 28,000 21 32/64 500-

733 --- 256 1 6 140.0

2000 Pentium 4 CMOS 0.18 42,000 21 32/64 1,400-1,500 --- 256 1 6 224

Microprocessor trends 13

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year

Cell Construction # of Layers Year Product Process

type Line width (µm)

Transis tors (K)

Mask layers Trans Type Size

(µm) Poly Metal

Die size

(mm2)

1970 1Kbit PMOS 8.0 4 6 3T P 2,400 1 1 9.7 1974 4Kbit NMOS 8.0 8 6 1T P 1,280 1 1 14.5 1976 16Kbit NMOS 5.0 16 7 1T P 500 2 1 19.4 1979 64Kbit NMOS 3.0 66 8-10 1T P 180 2 1 31.0

1982 256Kbit NMOS CMOS

2.0 1.5 262 --- 1T P 70

40 2 1 45.0 25.3

1986 1Mbit CMOS 1.2 1,049 18 1T P, S, T 25 2-3 1 70.0

1988 1991 1994 1996

4Mbit CMOS

0.80 0.50 0.35 0.30

4,194 20-25 1T S, T 12

4.69 2.30 1.69

2-3 2 95.0 37.1 18.2 13.4

1991 1994 1996

16Mbit CMOS 0.50 0.35 0.30

16.777 --- 1T S, F, T 4.2 2.06 1.51

3-4 2 130.0 63.7 46.8

1994 1996 1997 1998 1999 2000

64Mbit CMOS

0.35 0.30 0.25 0.23 0.18 0.15

67,109 --- 1T H, C, F, T

1.5 1.1 0.77 0.65 0.40 0.28

3-5 2-3

150.0 110.0 77.0 65.0 40.0 36.0

1997 1998 1999 2000 2001

128Mbit CMOS

0.25 0.23 0.18 0.15 0.13

131,072 --- 1T H, C, F, T --- 4-5 2-3

102 86 53 40 35

1998 1999 2000 2001 2002 2003

256Mbit CMOS

0.23 0.18 0.15 0.13 0.11 0.09

262,144 --- 1T HC, T, HK, PI --- 4-5 2-3

173.0 106.0 73.0 55.0 40 35

DRAM trends 14

Lecture #1

Crystalline or contaminate defects will kill the operation of an IC, so it is imperative that the silicon is ultra-pure. In order to create the best possible quality of silicon, a pure layer of silicon is grown on the raw wafer via an epitaxial growth process. This is known as the epi-layer. This layer is very thin - approximately 3 percent or less of the wafer thickness. As device complexity grows, the need for epi-wafers increases.

Basic lithography process flow

Defects kill yield and drive up manufacturing cost, so defect inspection is vital in the Fab.

Wafer probe or test is the first time that chips are tested to see if they function as they were designed to do.

Redundancy Repair is a process step almost exclusively used for memory chips

each pad on the die is connected to a corresponding pin on the package frame via a thin gold or aluminum wire (approx. 0.001" diameter).

Example: Detailed process sequence for CMOS

1.Grow epi layer– Ultra-pure single-

crystal silicon

2.Implant n-well

Detailed process sequence (con’t)

3.Define active area

4.Grow field oxide– For isolation

Detailed process sequence (con’t)

5.Grow gate oxide

6.Pattern polysilicon

Detailed process sequence (con’t)

7.Form pFETs

8.Form nFETs

Detailed process sequence (con’t)

9.Deposit LTO by CVD – LTO is low-

temperature oxide– CVD is chemical

vapor deposition

10. Deposit Metal1– Usually aluminum

Detailed process sequence (con’t)

11. Via definition– Deposit LTO– Make via cuts

12. Deposit Metal2– Usually aluminum

13. Overglass (not shown)– Coat entire chip with Si3N4

– Make pad openings in Si3N4

An inverter