lect2 up280 (100328)
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Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 280 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OPAMPS
LECTURE ORGANIZATIONOutline• Introduction• Examples of differential output op amps• Common mode output voltage stabilization• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 384-393
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONWhy Differential Output Op Amps?• Cancellation of common mode signals including clock feedthrough• Increased signal swing
v1
v2
v1-v2t
t
t
A
-AA
-A
2A
-2A Fig. 7.3-1
• Cancellation of even-order harmonicsSymbol:
-
+vin vout+
-
-
+
-
+
Fig. 7.3-1A
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Output Voltage StabilizationIf the common mode gain not small, it may cause the common mode output voltage to
be poorly defined.Illustration:
VDD
vod
t
070506-01
VSS
0
VDDvod
t
VSS
0
VDD
vod
t
VSS
0
CM output voltage properly defined,Vcm = 0
CM output voltage too large,Vcm= 0.5VDD
CM output voltage too small, Vcm= 0.5VSS
Remember that:vOUT = Avd(vID) ± Acm(vCM)
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-4
CMOS Analog Circuit Design © P.E. Allen - 2010
EXAMPLES OF DIFFERENTIAL OUTPUT OP AMPS (OTA’S)Two-Stage, Miller, Differential-In, Differential-Out Op Amp
Note that theupper ICMR is
VDD - VSGP + VTN
(OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)
The maximum peak-to-peak output voltage 2·OCMR
Conversion between differential outputs and single-ended outputs:
vod CL
+
-+-+
-vid
+
-vo1 2CL
+
-+-+
-vid
+
-
vo2+
-2CL
Fig. 7.3-4
vi1 M1 M2
M3 M4
M5
M6M8
VDD
VSS
VBN+-
Cc
M9
Cc
VBP+-
vi2
vo1voRzRz
M7
Fig. 7.3-3
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output
vi1M1 M2
M3 M4
M5
M6
M7
VDD
VSS
VBN+
-
Cc
M9
Cc
VBP+-
vi2
vo1 vo2RzRz
M8
Fig. 7.3-6
M10 M12
M13
M14
Comments:• Able to actively source and sink output current• Output quiescent current poorly defined
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Folded-Cascode, Differential Output Op Amp
060717-01
VPB1
M4 M5
I6 VPB2
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10 M11
+−vIN
vOUT
VNB1
I1 I2
M1 M2
M3I3
CL
VNB1
+−CL
• No longer has the low-frequency asymmetry in signal path gains.• Class A
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded-Cascode, Differential Output Op Amp
What about the A amplifier?Below is the upper A amplifier:
060718-02
VDD
VPB1
VPB2 VPB2
VNB1 VBias
vin+ vin
-
vout+vout
- M1M2 M3
M4
M5 M6
M7 M8
M9 M10
M11M12
Note that VBias controls the dc voltage at theinput of the A amplifier through the negativefeedback loop.
• Balanced inputs• Class A
060718-01
vOUT
M4M5
M3
M7
M8 M9
M10 M11
M6
VDD
VPB1
+
−vIN
M1 M2
VNB1
A+− +
−
+− +
−A
+−
VPB1
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Push-Pull Cascode Op Amp with Differential-OutputsVDD
VSS
VBias
R2 M22
M23
R1
M19
M20
M1 M2
M3 M4M5 M6M7 M8
M9 M10
M11
M12M13
M14
M15 M16M17
M18
M21
vo1vi1 vi2
vo2
Fig. 7.3-8
• Output quiescent currents are well defined• Self-biased circuits can be replaced with VNB2 and VPB2
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Folded-Cascode, Push-Pull, Differential Output Op Amp
060717-02
VPB1
M6 M7
I6
VPB2I4
I7
I9M8 M9
VNB2
M10 M11
M12 M13
+−vIN
vOUTVNB1
I3
I2
M2 M3
M5I5
CL+−CL
I1
M1
VNB2
M18M19
M20M21
VPB1
M14 M15
I16 VPB2
I14 I15
VDD
I17M16 M17
M4
I8
0.5gm1vin
0.5gm3vin
0.5gm2vin
0.5gm4vin
0.5gm3vin
0.5gm4vin0.5gm2vin
0.5gm1vin
I6 = I7 = I14 = I15 > 0.5I5I5 = I1 + I2 + I3 + I4
Av = gmRout(diff)
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded-Cascode with Push-Pull Outputs
060718-06
VPB1
M6 M7
M8 M9
M20
M19
M18
M21
+−vIN
VNB1
M2 M3
M5CL+−CL
M1
VNB2M14
M17M16
M15
VPB1
M10 M11
VPB2
VDD
M12 M13M4
vOUT
A+− +
−
+− +
−AVNB2
• Gain approaches gm3rds
3
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Cross-Coupled Differential Amplifier StageThe cross-coupled input stage allows the push-pull output quiescent current to be welldefined.
Operation:Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2
Using the notation for ac, dc, and total variables gives,vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)
If gm1 = gm2 = gm3 = gm4, then half of the differential input is applied across eachtransistor with the correct polarity.
i1 = gm1vid
2 = gm4vid
2 and i2 = -gm2vid
2 = -gm3vid
2
M1 M2
M3 M4
VGS2
VSG4
VGS1
VSG3
i1
i1i2
i2
vi1 vi2
Fig. 7.3-9
vGS1+
-
vSG4+
-vSG3
+
-
vGS2+
-
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Class AB, Differential Output Op Amp using a Cross-Coupled Differential InputStage
M1 M2
M3 M4
M5 M6
M7
VDD
VSS
VBias+
-
R1
M24
M25
R2
M27
M28
M8M9 M10
M11 M12
M13
M14
M15
M16
M17 M18
M19 M20
M21 M22
M26
M23
vo2
vi2vi1
vo1
Fig. 7.3-10
Quiescent output currents are defined by the current in the input cross-coupleddifferential amplifier.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-13
CMOS Analog Circuit Design © P.E. Allen - 2010
COMMON MODE OUTPUT VOLTAGE STABILIZATIONCommon Mode Feedback Circuits
Because the common mode gain is undefined, any common mode signal at the inputcan cause the output common mode voltage to be improperly defined. The commonmode output voltage is stabilized by sensing the common mode output voltage and usingnegative feedback to adjust the common mode voltage to the desired value.Model for the Output of Differential Output Op Amps:
VDD
io1(source) Ro1
vo1
io1(sink) Ro3
io2(source)
io2(sink)
Ro2
Ro4
vo2
VDD
io1(source) Ro1
vo1
Io1(sink) Ro3
io2(source)
Io2(sink)
Ro2
Ro4
vo2
Class A Output Push-Pull Output 060718-08
Roi represents the self-resistance of the output sink/sources.
1.) If the common mode output voltage increases the sourcing current is too large.2.) If the common mode output voltage decreases the sinking current is too large.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Conceptual View of Common-Mode Feedback
060718-09
VDD
VCMREF
+
−
vo2vo1
OutputStageModel
Common ModeSensing Circuit
Function of the common-mode feedback circuit:1.) If the common-mode output voltage increases, decrease the upper currents sources orincrease the lower current sink until the common-mode voltage is equal to VCMREF.
2.) If the common-mode output voltage decreases, increase the upper currents sources ordecrease the lower current sink until the common-mode voltage is equal to VCMREF.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-ModeFeedback
vi1 M1 M2
M3 M4
M5
M6M7
VDD
VSS
VBN+-
Cc
M9
Cc
VBP+
-
vi2
vo1vo2RzRz
M8
Fig. 7.3-12
M10 M11
Comments:• Simple• Unreferenced – value of common mode output voltage determined by the circuit
characteristics
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Feedback CircuitsImplementation of common mode feedback circuit:
060718-10
vi1M1 M2
M3 M4
M5
VDD
IBias
VCM
vo1
MC2A
MC2B
MC1
MC3MC4
MC5MB
I3 I4IC4IC3
Common-mode feed-back circuit
Ro1 Ro2
vi2
vo2
This scheme can be applied to any differential output amplifier.CM Loop Gain = -gmC1Ro1 which can be large if the output of the differential outputamplifier is cascaded or a gain-enhanced cascode.The common-mode loop gain may need to be compensated for proper dynamicperformance.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Common Mode Feedback Circuits – ContinuedThe previous circuit suffers when the input common mode voltage is low because thetransistors MC2A and MC2B have a poor negative input common mode voltage.The following circuit alleviates this disadvantage:
060718-11
vi1M1 M2
M3 M4
M5
VDD
IBias
VCM
vo2vo1
vi2MC2MC1
MC3
MC4
MC5MB
I3 I4IC4IC3
Common-mode feed-back circuit
RCM1 RCM2
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-18
CMOS Analog Circuit Design © P.E. Allen - 2010
An Improved Common-Mode Feedback CircuitThe resistance loading of the previous circuit can be avoided in the following CMfeedback implementation:
VDD
060718-12
VCMREFRCM RCM
vo1 vo2
CM Correction Circuitry
M1 M2 M3 M4
M5 M6
This circuit is capable of sustaining a large differential voltage without loading the outputof the differential output op amp.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the CM Feedback CircuitConsider the following CM feedback circuit implementation:
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VPB1
M4 M5
VPB2
VDD
M6 M7
VNB2M8
M10M11
+−vIN
vOUT
VNB1
M1 M2
M3 VCMREF
+−
M9
M12
M13 M14
M15 M16
CcCc
The CM feedback path has two poles – one at the gates of M10 and M11 and thedominant output pole of the differential output op amp.Can compensate with Miller capacitors as shown.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Improved CM Feedback Frequency ResponseThe circuit on the previous page can be modified to eliminate the pole at the gates ofM10 and M11 as follows:
060718-14
VPB1
M4 M5
VPB2
VDD
M6 M7
VNB2M8
M10 M11
+−vin
vo1
VNB1
M1 M2
M3
VCMREF
M9
M12
M13 M14
M16M15
VNB1
VNB2
M17
M18M19
vo2
• The need for compensation of the common mode loop no longer exists since there isonly one dominant pole
• The dominant pole of the differential amplifier becomes the dominant pole of thecommon mode feedback
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-21
CMOS Analog Circuit Design © P.E. Allen - 2010
A Common Mode Feedback Correction Scheme for Discrete Time ApplicationsCorrection Scheme:
Ccm+
-+-+
-vid
vo1
vo2CMbias
φ1 φ2
Ccm Vocm
φ1 φ2
φ1
φ1
φ1 Fig. 7.3-14 Operation:1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias
= Vocm.
2.) During the 2 phase, the Ccm capacitors are connected between the differentialoutputs and the CMbias node. The average value applied to the CMbias node will beVocm.
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Example of a Common-Mode Output Voltage Stabilization Scheme for Discrete-Time ApplicationsCommon modeadjustment phase:Switches S1, S2 and S3are closed. C1 and C2are charged to the valuenecessary for I12 and I13to keep the commonmode output voltage atVCM.
Amplification phase:Switches S4 and S5 areclosed. If the commonmode output voltage isnot at VCM, the currentsI12 and I13 will changeto force the value of the common mode output voltage back to VCM.
070506-03
VPB1
M4 M5VPB2
VDD
M6 M7
VNB2M8
M10 M11
+−vIN
vOUT
VNB1
M1 M2
M3VCM
+−
M9
M12 M13 M14
M15
C1
C2
VNB1
S4
S5
S1
S2
S3
I12
I13
Discrete time common mode correction circuit
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Correction of Channel Charge and Clock FeedthroughIn the discrete-time common mode correction schemes, the switches can introduce
error due to channel charge and clock feedthrough.Through simulation, these errors can be predicted and corrected by applying a
correction signal superimposed upon the error signal to achieve the desired (target)common mode voltage.General principle:
CMFBAmplifier
CMFBSense
DifferentialOutputs
VBias
Vcm (Target voltage)
Unwanted ChargeInjection Error
ErrorSignal
CorrectionSignal
ΔV
Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-24
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Advantages of differential output op amps:
- 6 dB increase in signal amplitude- Cancellation of even harmonics- Cancellation of common mode signals including clock feedthrough
• Disadvantages of differential output op amps:- Need for common mode output voltage stabilization- Compensation of common mode feedback loop- Difficult to interface with single-ended circuits
• Most differential output op amps are truly balanced• For push-pull outputs, the quiescent current should be well defined• Common mode feedback schemes include,
- Continuous time- Discrete time