lect2 up260 (100328)

Lecture 260 – Buffered Op Amps (3/28/10) Page 260-1

CMOS Analog Circuit Design © P.E. Allen - 2010

LECTURE 260 – BUFFERED OP AMPSLECTURE ORGANIZATION

Outline• Introduction• Open Loop Buffered Op Amps• Closed Loop Buffered Op Amps• Use of the BJT in Buffered Op Amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 352-368



INTRODUCTIONBuffered Op AmpsWhat is a buffered op amp?

Buffered op amps are op amps with the ability to drive a low output resistance and/ora large output capacitance. This requires:

- An output resistance typically in the range of 10 Ro 1000

- Ability to sink and source sufficient current (CL·SR)

+

−

Op Amp Buffer

RoutLarge

RoutSmall

vIN vOUTvOUT’

070430-01

Types of buffered op amps:- Open loop using output amplifiers- Closed loop using negative shunt feedback to reduce the output resistance of the op

amp

Lecture 260 – Buffered Op Amps (3/28/10) 60-3


OPEN LOOP BUFFERED OP AMPSThe Class A Source Follower as a Buffer• Simple

• Small signal gain gm

gm + gmbs + GL < 1

• Low efficiency

• Rout = 1

gm + gmbs 500 to 1000

• Level shift from input to output• Maximum upper output voltage is limited• Broadbanded as the pole and zero due to the source follower are close so compensation

is typically not a problem

060118-10

VNBias1

VDD

M1

M2

vIN

vOUT



The Push-Pull Follower as a Buffer• Voltage loss from 2 cascaded followers

Av gm3

gm3 + gmbs3

gm1gm1 + gmbs1 + GL

< 1

• Higher efficiency

• Rout 0.5

gm + gmbs 250 to 500

• Current in M1 and M2 determined by:VGS4 + VSG3 = VGS1 + VSG2

2I6Kn'(W4/L4) +

2I5Kp'(W3/L3)

= 2I1

Kn'(W1/L1) + 2I2

Kp'(W2/L2)

Use the W/L ratios to define I1 and I2 from I5 and I6• Maximum positive and negative output voltages are limited

060706-02

VNBias1

VDD

M1

M2

vIN vOUT

VDD

VDD

M4VDD

VPBias1

VDD

M5

M3

M6

+−

VSG3

I5

I6

+−

VSG2+−

VGS4

+−

VGS1

I1

I2



Two-Stage Op Amp with Follower

-

+vin

M1 M2

M3 M4

M5

M6

M7VNBias

Cc

CLI5 I7

060706-03

VDD

M8

M9

vout

I9

Power dissipation now becomes (I5 + I7 + I9)VDD

Gain becomes,

Av = gm1

gds2+gds4 gm6

gds6+gds7 gm8

gm8+ gmbs8+gds8+gds9



Source-Follower, Push-Pull Output Op Amp

vout

VDD

VDD

Cc

-

+vin

M1 M2

M3

VSS

R1

M5

M6

R1

M7

M8

R1

M13

M14

VSS

VDDVSS

M22

M21

IBias

M9

M10

M11

M12

M4

M17

M18

M15

M16

M19

M20

Fig. 7.1-1

CL

Buffer

-+VSG18

-+VSG21

-

+VGS19

-

+VGS22

I17

I20

Rout 1

gm21+gm22 1000 , Av(0)=65dB (IBias=50μA), and GB = 60MHz for CL = 1pF

Note the bias currents through M18 and M19 vary with the signal.



Compensation of Op Amps with Output AmplifiersCompensation of a three-stage amplifier:This op amp introduces a third pole, p’3 (whatabout zeros?)With no compensation,

Vout(s)Vin(s) =

-Avo

sp’1 - 1

sp’2 - 1

sp’3 - 1

Illustration of compensation choices:

p1'p2'p3' p1

p2

p3

jω

σp1'p2'p3' p1

p2

p3=

jω

σ

Miller compensation applied around both the second and the third stage.

Miller compensation applied around the second stage only. Fig. 7.1-5

Compensated polesUncompensated poles

vin vout+-

x1v2

Unbufferedop amp

Outputstage

Polesp1' and p2'

Pole p3'

+

-

Fig. 7.1-4

CL RL



Crossover-Inverter, Buffer Stage Op AmpPrinciple: If the buffer has high output resistance and voltage gain (common source), thisis okay if when loaded by a small RL the gain of this stage is approximately unity.

060706-04

-

+vin

M1 M2

M3 M4

M5

M6M7

vout

VDD

VSS

C2

RL

+-

C1

Cross over stage Output StageInputstage

vin'

IBias

• This buffer trades gain for the ability to drive a low load resistance• The load resistance should be fixed in order to avoid changes in the buffer gain• The push-pull common source output will give good output voltage swing capability



Crossover-Inverter, Buffer Stage Op Amp - ContinuedHow does the output buffer work?The two inverters, M1-M3 and M2-M4 are designed to work over different regions of thebuffer input voltage, vin’.

Consider the idealized voltage transfer characteristic of the crossover inverters:

060706-05

VDDVA

M6 Active

M6 Satur-ated

M5 Active

M5 Saturated

VB

M1-M3Inverter

M2-M4Inverter

0 vin'

M1 M2

M3 M4M7

vout

VDD

VSS

C2C1

vin'

M6

M5 RL

voutVDD

VSS

IBias

Crossover voltage VC = VB-VA 0

VC is designed to be small and positive for worst case variations in processing.



Large Output Current BufferIn the case where the load consists of a large capacitor, the ability to sink and source alarge current is much more important than reducing the output resistance. Consequently,the common-source, push-pull is ideal if the quiescent current can be controlled.A possible implementation:

If W4/L4 = W9/L9 andW 3/L3 = W8/L8, then thequiescent currents in M1and M2 can be determinedby the followingrelationship:

I1 = I2 = Ib W 1/L1W 7/L7

= Ib W 2/L2

W 10/L10

When vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly,when vin is decreased, M5 turns off M1 and turns on M2 to sink current.

VDD

VSS

Ib

Ib

I=2Ib

M1

M2

M3 M4

M5

M6

M7

M8 M9

M10

vin

I=2Ib

vout

070430-07

vin

VDD

VSS

vout



CLOSED LOOP BUFFERED OP AMPSPrinciple

Use negative shunt feedback to reduce the output resistance of the buffer.

Av+−

vINvOUT

ROUTRo

070430-02

RL

• Output resistance

ROUT = Ro

1 + Av

• Watch out for the case when RL causes Av to decrease.

• The bandwidth will be limited by the feedback (i.e. at high frequencies, the gain of Avdecreases causing the output resistance to increase.



Two Stage Op Amp with a Gain Boosted, Source Follower Buffer

-

+vin

M1 M2

M3 M4

M5

M6

M7VNBias

Cc

I5 I7

070430-03

VDD

M11

vout

I11

1:K

M8

M9 M10

Rout

Rout 1

gm8K

Power dissipation now becomes (I5 + I7 + I11)VDD

Gain becomes,

Av = gm1

gds2+gds4 gm6

gds6+gds7 gm8K

gm8K+ gmbs8K +GL



Gain Boosted, Source-Follower, Push-Pull Output Op AmpVDD

Cc

-

+vin

M1 M2

M3

VSS

M5

M6

M7

M8

R1

M13

M14

VSS

VDD

M21

IBias

M9

M10

M11

M12

M4

M17

M18

M15

M16

M19

M20

Gain Enhanced Buffer

-+VSG18

-+VSG21

-

+VGS19

-

+VGS22

I17

I20M23

M24

+VT+2VON

-

vout

1:K

M22

M23 M24

Rout

M25 M261:K

070430-04

Rout 1

K(gm21+gm22) 1000

K 100

Av(0)=65dB (IBias=50μA)

Note the bias currents through M18 and M19 vary with the signal.



Common Source, Push Pull Buffer with Shunt FeedbackTo get low output resistance using MOSFETs, negative feedback must be used.Ideal implementation:

CL RL

viin vout

iout

VDD

M2

M1

Fig. 7.1-5A

+-

+-

ErrorAmplifier

ErrorAmplifier

VSS

+-

GainAmplifier

Comments:• The output resistance will be equal to rds1||rds2 divided by the loop gain

• If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is notdefined



Low Output Resistance Op Amp - ContinuedOffset correction circuitry:

-

+vin

A1

M16 M9

vout

VDD

VSS

VBias+

-

Cc

+-

+-

+-M8

M17

M8A

M13M6A

M6

M12 M11

M10

A2

VOS

Error Loop

Fig. 7.1-6

Unbufferedop amp

The feedback circuitry of the two error amplifiers tries to insure that the voltages inthe loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust theoutput for any error in the loop. The circuit works as follows:When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducingIM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreasesby an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.



Low Output Resistance Op Amp - ContinuedError amplifiers:

vinM1 M2

M3 M4

M5

M6

M6A

vout

VDD

VSS

VBias+

-

Cc1

A1 amplifier

MR1

070430-05

A2 amplifier

vin

VBias+

-

M2A M1A

M5A

M4A M3A

MR2

Cc2

Basically a two-stage op amp with the output push-pull transistors as the second-stage ofthe op amp.



Low Output Resistance Op Amp - Complete Schematic

Short circuit protection(max. output ±60mA):MP3-MN3-MN4-MP4-MP5MN3A-MP3A-MP4A-MN4A-MN5A

Rout rds6||rds6A

Loop Gain 50k5000 = 10

M2

M3 M4

M5

M1

vout

VDD

VSS

VBiasN+

-

Cc

+-

VBiasP+

-

Cc1

M16M3H M4H MP4

MP3

MP5

MR1

M8

M17 MN3 MN4

M6

M6A

M13 M12 M11

MR2Cc2

M8A

M9

MN5A

MN4A

MN3A

MP4A

MP3A

M4HA

M4A M3A

M3HA

M1AM2A

M5Avin+

-

Fig. 7.1-8

M10

RC

R1 RL CL

CC

C1

gm1 gm6



Simpler Implementation of Negative Feedback to Achieve Low Output Resistance

Output Resistance:

Rout = Ro

1+LG where

Ro = 1

gds6+gds7

and

|LG| = gm2

2gm4 (gm6+gm7)Ro

Therefore, the output resistance is:

Rout = 1

(gds6+gds7) 1 +gm2

2gm4 (gm6+gm7)Ro

-

+vin

M1 M2

M3 M4

M5

M6

M7

vout

VDD

VSS

CL

M8

M10

M9

Fig. 7.1-9

1/1 10/1200μA 10/1

10/1 10/1

1/1

1/1

1/1

10/1 10/1



Example 260-1 - Low Output Resistance Using Shunt Negative Feedback BufferFind the output resistance of above op amp using the model parameters of KN’ =

120μA/V2, KP’ = 25μA/V2, N = 0.06V-1 and P = 0.08V-1.

SolutionThe current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of

Ro = 1

( N+ P)1mA = 10000.14 = 7.143k

To calculate the loop gain, we find that gm2 = 2KN’·10·100μA = 490μS

gm4 = 2KP’·1·100μA = 70.7μSand

gm6 = 2KP’·10·1000μA = 707μS

Therefore, the loop gain is

|LG| = 490

2·70.7 (0.707+0.071)7.143 = 19.26

Solving for the output resistance, Rout, gives

Rout = 7.143k1 + 19.26 = 353 (Assumes that RL is large)



USE OF THE BJT IN BUFFERED OP AMPSSubstrate BJTsIllustration of an NPN substrate BJT available in a p-well CMOS technology:

��

��

n- substrate (Collector)

p- well (Base)

n+ (Emitter) p+

��n+

Emitter Base Collector(VDD)

Collector (VDD)

Emitter

Base

Fig. 7.1-10

Comments:• gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower

• Collector current will be flowing in the substrate• Current is required to drive the BJT• Only an NPN or a PNP bipolar transistor is available



A Lateral Bipolar Transistorn-well CMOS technology:• It is desirable to have the lateral

collector current much larger than thevertical collector current.

• Triple well technology allows thecurrent of the vertical collector to avoidflowing in the substrate.

• Lateral BJT generally has goodmatching.

060221-01

p+

n-well

n+

Substrate

E LCBVC

STI STI

LC

STI Lateral Collector

Emitter

Base

VerticalCollector

p+ p+



A Field-Aided Lateral BJTUse minimum channel length to

enhance beta:ßF 50 to 100 depending on the

process

060221-02

p+

n-well

n+

Substrate

BVC

STI STI

LC

STI Lateral Collector Emitter

Base

VerticalCollector

p+ p+p+

E LC

Keeps carriers fromflowing at the surfaceand reduces 1/f noise



Two-Stage Op Amp with a Class-A BJT Output Buffer StagePurpose of the M8-M9 sourcefollower:1.) Reduce the output resistance

(includes whatever is seen fromthe base to ground divided by1+ F)

2.) Reduces the output load at thedrains of M6 and M7

Small-signal output resistance :

Rout r 10 + (1/gm9)

1+ßF =

1gm10

+ 1

gm9(1+ßF)

= 51.6 +6.7 = 58.3 where I10=500μA, I8=100μA, W9/L9=100 and ßF is 100

vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD - 2KP’

I8(W8/L8) - Vt lnIc10Is10

Voltage gain:voutvin

gm1

gds2+gds4

gm6gds6+gds7

gm9gm9+gmbs9+gds8+g 10

gm10RL1+gm10RL

Compensation will be more complex because of the additional stages.

M1 M2

M3 M4

M5

M6

M7

vout

VDD

VSS

CcCL

IBias

Q10

M11

M12

M13

Fig. 7.1-11

M8

M9

Output Buffer

RL

vin

+

-



Example 260-2 - Designing the Class-A, Buffered Op AmpUse an n-well, 0.25μm CMOS technology to design an op amp using a class-A, BJT

output stage to give the following specifications. Assume the channel length is to be0.5μm. The FETs have the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, VTN =

|VTP| = 0.5V, N = 0.06V-1 and P = 0.08V-1 along with the BJT parameters of Is =10-14A and ßF = 50.VDD = 2.5V VSS = 0V GB = 5MHz Avd(0) 2500V/V Slew rate 10V/μsRL = 500 Rout 50 CL = 100pF ICMR = +1V to 2V

SolutionA quick comparison shows that the

specifications of this problem are similarto the folded cascode op amp that wasdesigned in Ex. 240-3. Borrowing thatdesign for this example results in thefollowing op amp.

Therefore, the goal of this examplewill be the design of M12 through Q15 tosatisfy the slew rate and output resistancerequirements.

070430

VPB1

M4 M5Rout

I6

VPB2

I4 I5

VDD

I7M6 M7

VNB2

M8 M9

M10M11

+−vIN

vO

VNB1

I1 I2

M1 M2

M3I3

C

VNB1

VPB1

M12

M13

M14

Q15

I12

I15



Example 260-2 – ContinuedBJT follower (Q15):

SR = 10V/μs and 100pF capacitor give I15 = 1mA.

Assuming the gate of M14 is connected to the gate of M5, the W /L ratio of M14becomes

W14/L14 = (1000μA/125μA)160 = 1280 W14 = 640μm

I15 = 1mA 1/gm15 = 0.0258V/1mA = 25.8

MOS follower:To source 1mA, the BJT requires 20μA (ß =50) from the MOS follower (M12-M13). Therefore, select a bias current of 100μA for M13. If the gates of M3 and M13 areconnected together, then

W13/L13 = (100μA/100μA)15 = 15 W13 = 7.5μm

To get Rout = 50 , if 1/gm15 is 25.8 , then design gm12 as1

gm15 =

1gm12(1+ßF) = 24.2 gm12 =

1(24.2 )(1+ßF) =

124.2·51 = 810μS

gm12 and I12 W/L = 27.3 30 W12 = 15μm



Example 260-2 - Continued

To calculate the voltage gain of the MOS follower we need to find gmbs9 ( N = 0.4 V).

gmbs12 = gm12 N

2 2 F + VBS12 =

810·0.42 0.5+0.55 = 158μS

where we have assumed that the value of VSB12 is approximately 1.25V – 0.7V = 0.55V.

AMOS = 810μS

810μS+158μS+6μS+8μS = 0.825

The voltage gain of the BJT follower is

ABJT = 500

25.8+500 = 0.951 V/V

Thus, the gain of the op amp isAvd(0) = (3,678)(0.825)(0.951) = 2,885 V/V

The power dissipation of this amplifier is, Pdiss. = 2.5V(125μA+125μA+100μA+1000μA) = 3.375mW

The signal swing across the 500 load resistor will be restricted to ±0.5V due to the1000μA output current limit.



SUMMARY• A buffered op amp requires an output resistance between 10 Ro 1000

• Output resistance using MOSFETs only can be reduced by,- Source follower output (1/gm)

- Negative shunt feedback (frequency is a problem in this approach)• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is

larger than the gm of a MOSFET

• Adding a buffer stage to lower the output resistance will most likely complicate thecompensation of the op amp

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compensation of op amps

types of buffered op

stage op amp

output amplifierscompensation

output amplifiers closed

source follower

negative output voltages

maximum upper output