8/13/2019 lec4_JWFILES

1/14

Placement

The process of arranging the circuit components on a layout surface.

Inputs: A set of fixed modules, a netlist.

Goal: Find the best position for each module on the chip according toappropriate cost functions.

Considerations: routability/channel density, wirelength, cut size,performance, thermal issues, I/O pads.

1

2

3

4

5

6

7 8

1

7

5

8

2

3

6

4

1 2

3

4

5

6

8 7

wirelength = 10 wirelength = 12

A

Density = 2 (2 tracks required)

D B C

E F G H

A

Shorter wirelength, 3 tracks required.

B C D

E F G H

1

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

2/14

Estimation of Wirelength

Semi-perimeter method: Half the perimeter of the bounding rectanglethat encloses all the pins of the net to be connected. Most widely usedapproximation!

Complete graph: Since #edges in a complete graph (n(n1)2

) is n2 #

of tree edges (n 1), wirelength 2n

(i,j)net dist(i, j).

Minimum chain: Start from one vertex and connect to the closest one,and then to the next closest, etc.

Source-to-sink connection: Connect one pin to all other pins of thenet. Not accurate for uncongested chips.

Steiner-tree approximation: Computationally expensive.

Minimum spanning tree

2

www.jntuworld.com

www.jntuworld.comj ld

8/13/2019 lec4_JWFILES

3/14

4

4

33

3

3

3

3

3

4

4

7

semiperimeter len = 11

10 78 8

complete graph len * 2/n = 17.5 chain len = 14

10

sourcetosink len = 17

8

Steiner tree len = 12

7

Spanning tree len = 13

www.jntuworld.com

www.jntuworld.com

j t ld

8/13/2019 lec4_JWFILES

4/14

Min-Cut Placement

Breuer, A class of min-cut placement algorithms, DAC-77.

Quadrature: suitable for circuits with high density in the center.

Bisection: good for standard-cell placement.

Slice/Bisection: good for cells with high interconnection on the periphery.

3a

1

3b

4a 2 4b

3a

2a

3b

1

3c

2b

3d

6a5a6b 4 6c 5b6d

n/2

n/2

1

2

3

4

5

6

7

10a9a10b8 10c9b10d

quadrature bisection slice/bisection

n/4

n/4n/2

n/2

n/2

n/4

n/4

C1

C2

C1

C2

n/k

n/k

(k2)n/k

C2

n/k

(k1)n/k

C1

3

www.jntuworld.com

www.jntuworld.com

www jntuworld com

8/13/2019 lec4_JWFILES

5/14

Algorithm for Min-Cut Placement

Algorithm: Min Cut Placement(N, n, C )/* N: the layout surface *//* n: # of cells to be placed *//* n0: # of cells in a slot *//* C: the connectivity matrix */

1 begin2 if (n n0) then PlaceCells(N, n, C );3 else4 (N1, N2) CutSurface(N);5 (n1, C1), (n2, C2) Partition(n, C);6 Call Min Cut Placement(N1, n1, C1);7 Call Min Cut Placement(N2, n2, C2);8 end

4

www.jntuworld.com

www.jntuworld.com

www jntuworld com

8/13/2019 lec4_JWFILES

6/14

Quadrature Placement Example

Apply K-L heuristic to partition + Quadrature Placement: CostC1 = 4, C2L= C2R = 2,etc.

P

Q

R

Q1

Q2

Q3

1

2

3

4

5

6

7

8

9

11

10

12

13

14

15

16

C1

C22,4,5,7 8,12,13,14

1,3,6,9 10,11,15,16 1

2

3

4

5

6

8

9

13

14

15

16

7 12

10

11

P

C4a

C2

Q

C4b

R

O1

C4a

C2

O2

C4b

O3

C1 C3bC3a

5

www.jntuworld.com

www.jntuworld.com

www jntuworld com

8/13/2019 lec4_JWFILES

7/14

Min-Cut Placement with Terminal Propagation

Dunlop & Kernighan, A procedure for placement of standard-cell VLSIcircuits, IEEE TCAD, Jan. 1985.

Drawback of the original min-cut placement: Does not consider thepositions of terminal pins that enter a region.

What happens if we swap {1, 3, 6, 9} and {2, 4, 5, 7} in the previousexample?

L1

L2

R

S

L1

L2

S

prefer to have them in R1

R1

R2

6

www.jntuworld.com

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

8/14

Terminal Propagation

We should use the fact that s is in L1!

L1

L2

R1

R2

L1

L2

R1

R2

center

pp

dummy cell

Lower cost higher cost

P will stay in R1 for the rest of partitioning!

s s

When not to use p to bias partitioning? Net s has cells in many groups?

h/3

p

h

Use p!

ph/3h

Dont use p to bias thesolution in either direction!

R

L

p1

p2

p3

G

minimum rectilinear Steiner tree

7

www.jntuworld.com

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

9/14

Terminal Propagation Example

Partitioning must be done breadth-first, not depth-first.

d

ba

c

S

a b

c d

S

RL

C1

a b

c d

C1

b

c d

ap1

L1

L2

R1

R2

c

a d

C1

L1

L2

R1

R2

b

RL

C1

a b

c d

without terminalpropagation

with terminalpropagation

unbiased partition of R

8

www.jntuwo ld.co

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

10/14

Placement by Simulated Annealing

Sechen and Sangiovanni-Vincentelli, The TimberWolf placement androuting package,IEEE J. Solid-State Circuits, Feb. 1985; TimberWolf3.2: A new standard cell placement and global routing package, DAC-86.

TimberWolf: Stage 1

Modules are moved between different rows as well as within the samerow.

Modules overlaps are allowed.

When the temperature is reached below a certain value, stage 2begins.

TimberWolf: Stage 2

Remove overlaps.

Annealing process continues, but only interchanges adjacent moduleswithin the same row.

9

j

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

11/14

Solution Space & Neighborhood Structure

Solution Space: All possible arrangements of the modules into rows,possibly with overlaps.

Neighborhood Structure: 3 types of moves

M1: Displace a module to a new location.

M2

: Interchange two modules.

M3: Change the orientation of a module.

overlap

3

4

1 2 12

3

4

M1 M2 M3

10

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

12/14

Neighborhood Structure TimberWolf first tries to select a move betweenM1and M2: Prob(M1) = 0.8, Prob(M2) =

0.2.

If a move of type M1 is chosen and it is rejected, then a move of type M3 for the samemodule will be chosen with probability 0.1.

Restrictions: (1) what row for a module can be displaced? (2) what pairs of modulescan be interchanged?

Key: Range Limiter

At the beginning, (WT, HT) is very large, big enough to contain the whole chip.

Window size shrinks slowly as the temperature decreases. Height and width log(T).

Stage 2 begins when window size is so small that no inter-row module interchangesare possible.

WT

HT

11

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

13/14

Cost Function

Cost function: C=C1+ C2+ C3.

C1: total estimated wirelength.

C1 =

iNets(iwi+ ihi)

i, i are horizontal and vertical weights, respectively. (i = 1, i= 1 1

2 perime-

ter of the bounding box of Net i.)

Critical nets: Increase both i and i. If vertical wirings are cheaper than horizontal wirings, use smaller vertical weights:

i < i.

C2: penalty function for module overlaps.

C2 =

i=jO2ij, : penalty weight.

Oij: amount of overlaps in the x-dimension between modules i and j.

C3: penalty function that controls the row length.

C2 =

rRows|Lr Dr|, : penalty weight.

Dr: desired row length.

Lr: sum of the widths of the modules in row r.

12

www.jntuworld.com

www.jntuworld.com

8/13/2019 lec4_JWFILES

14/14

Annealing Schedule

Tk =rkTk1, k= 1, 2, 3, . . .

rk increases from 0.8 to max value 0.94 and then decreases to 0.8.

At each temperature, a total # of nP attempts is made. n: # of modules; P: user specified constant.

Termination: T