larg2 user manual issue 1 - intel...1. 92 pairs of gpio (can be used as single-ended io) (see 2...

© Enterpoint Ltd. – Larg2 Manual – Issue 1.0 14/12/2015 1

Larg2 User Manual

Issue – 1.0


Foreword

PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN

OR POWERING UP YOUR LARG1 BOARD.

PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN

THIS MANUAL.

Trademarks

Cyclone-V, Altera, QuartusII, QSys are the registered trademarks of Altera Corporation, San Jose,

California, US.

Larg2 is a trademark of Enterpoint Ltd.


Contents

Foreword 2 Trademarks 2 Larg2 Board 4 Introduction 5 LARG2 FEATURES 6 FPGA 7 SPI FLASH 8 DDR3 MEMORY 9

DIMM INTERFACE 11 USB 14 ETHERNET 16 MAC ADDRESS DEVICE 17 LEDS 18 POWER MONITORS AND RESET 19 OSCILLATOR 20 IO EXPANDER 21 I2C DEVICES 22 UART AND SPI 23 MICRO SD CARD HOLDER 23 GPIO 24 POWER CONNECTIONS 25 POWER REGULATORS 26 PROGRAMMING LARG2 27 MECHANICAL 29 Medical and Safety Critical Use 30 Warranty 30 Support 30


LARG2

LARG BREAKOUT BOARD


INTRODUCTION

Welcome to your Larg2 board. Larg2 is a Cyclone-V based FPGA development board offering a

highly powerful, flexible and low cost approach to prototyping FPGA and System designs. It fits into a

standard DDR2 240 pin DIMM connector e.g FCI 10005639-11107LF.

The aim of this manual is to assist in using the main features of Larg2.There are features that are

beyond the scope of the manual. Should you need to use these features then please email

[email protected] for detailed instructions.

Larg2 currently comes with an 5CSEBA2U23C8SN UBGA672 Cyclone-V device fitted. Other

variants may be offered at a later date or as an OEM product. Please contact us on

[email protected] should you need further information. Custom Larg Modules with

additional functionality can also be provided to your specification.

Larg2 is supported by a breakout board which routes the IO on Larg2 to an FMC connector and a pair

of 0.1mm pitch DIL headers. These DIL headers support a wide range of Enterpoint add-on modules.

Some examples of these include:

ADC 7927 MODULE

LED DOT MATRIX MODULE

BUTTONS/SWITCHES/SATA/MEMORY MODULE

RS232 AND RS485 HEADER MODULES

DP83816 ETHERNET MODULE

SD CARD MODULE

IDE/5V TOLERANT CPLD MODULE

USB MODULE

D/A CONVERTER MODULE

ADV7202 MODULE

LTC2248 ADC MODULE

MICTOR CONNECTOR MODULE

IDT5V19EE901 CLOCK MODULE

OPTOISOLATOR MODULE

NAND FLASH MODULE

OVM 7690 CAMERA MODULE

KSZ9021RL GIGABIT PHY MODULE

We can also offer custom DIL Header modules should you require a function not covered by our

current range of modules. Typical turn around for this service is 6-8 weeks depending upon quantity

ordered and availability of components

mailto:[email protected]:[email protected]


LARG2 FEATURES

Fig1 Larg2 features

The Cyclone-V FPGA on board is supported by the free Quartus II Lite edition, version 13 or later,

available from Altera providing all the tools to enter and build a design. Using this tool in conjunction

with a programming cable you will also be able to program the Cyclone-V, and the supporting SPI

Flash, that are on Larg2.

Quartus II can be obtained directly from the Altera website. Registration may be necessary to complete

the download.

Once you have obtained your Quartus II tools:

(1) Connect your programming cable to the board and your PC hosting the Altera software.

(2) Power the board using the Enterpoint Larg Breakout board or your own hardware interface. 12v

and an FPGA IO voltage of 1.8V to 3.3V is required.


FPGA

Fig2 LARG2 Cyclone-V device

Larg2 supports Cyclone-V devices in the UBGA672 package. Larg2 is normally available with

commercial grade devices fitted. Should you have an application that needs industrial parts or faster

speed grades please contact sales for a quote at [email protected].

mailto:[email protected]


SPI FLASH MEMORY

Fig3 Larg2 SPI Flash

Larg2 has two MX25L25635EZNI-12G 256Mbit Quad SPI flash memory devices (U8 and U12), one

to configure the Cyclone-V HPS (U8) and the second to configure the Cyclone-V FPGA (U12). These

devices have a capacity of 256Mbits (32MB). A single configuration bitstream for the Larg2 FPGA is

approximately 34Mbits and the preloader file for the HPS is 60KB maximum. Any remaining space

can be used for alternative configurations or code and data storage. It would normally be expected that

the SPI flash for the HPS would contain boot code only and that the SDCard would be used to run

LINUX or some other operating system.

After configuration the SPI Flash can be accessed via the following pins of the FPGA:

SPI FLASH FUNCTION CYCLONE V PIN (U8) CYCLONE V PIN (U12)

CCLK C14 AA8

D/MISO0 A8 AD7

Q/MISO1 H16 AC6

WP#/MISO2 A7 AC5

HOLD/MISO3 J16 AB6

CS# A6 AA6

U8 can be programmed from the 7x2 programming connector J4, and U12 can be programmed from

the 7x2 programming connector J1.

Note: The FPGA cannot be programmed until a suitable boot file is loaded into the Cyclone-V

processor.Is this true?


DDR3 MEMORY

Fig4 Larg2 DDR3

Larg2 has a 4GBIT DDR3 Micron MT41K256M16HA-125E device as standard. This device is

organised as 32 Meg x 16 x 8 banks. This device is supported by the hard core memory controller in

the Cyclone-V FPGA. To add this core to your design the COREGEN tool, part of the ISE suite, will

generate implementation templates in VHDL or Verilog for the configuration that you want to use.

More details on the memory controller can be found in the user guide http://www.Altera.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_M

IS.pdf

The DDR3 has 12 address lines and 16 data lines to address all the available memory, which can be

accessed at speeds of 1.87ns. More details of the DDR3 can be found in

http://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125

The DDR3 site has the following connections to the FPGA:

DDR3 FUNCTION FPGA PIN DDR3 FUNCTION FPGA PIN

DDR_A0 M4 DDR_DQ3 D3

DDR_A1 M5 DDR_DQ4 E3

DDR_A2 K4 DDR_DQ5 E1

DDR_A3 L4 DDR_DQ6 F2

DDR_A4 K6 DDR_DQ7 F1

DDR_A5 K5 DDR_DQ8 G2

DDR_A6 J7 DDR_DQ9 G1

DDR_A7 J6 DDR_DQ10 L1

DDR_A8 J5 DDR_DQ11 L2

DDR_A9 H5 DDR_DQ12 L3

DDR_A10 J3 DDR_DQ13 K1

DDR_A11 G5 DDR_DQ14 J1

DDR_A12 H4 DDR_DQ15 K3

DDR_A13 F4 DDR_LDM B1

DDR_A14 G4 DDR_LDQS_P C2

DDR_A15 DDR_LDQS_N D2

DDR_BA0 L7 DDR_UDM H3

DDR_BA1 L6 DDR_UDQS_P H2

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdfhttp://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdfhttp://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125


DDR_BA2 M6 DDR_UDQS_N J2

DDR_CS_N P6 DDR_ODT P5

DDR_RAS_N R5 DDR_CAS_N P3

DDR_WE_N R4 DDR_RESET_N F3

DDR_DQ0 D1 DDR_CKE_P V3

DDR_DQ1 C3 DDR_CLK_N N5

DDR_DQ2 B2 DDR_CLK N4

The signals shown shaded in yellow are terminated using suitable arrangements of resistors.


DIMM INTERFACE

Fig5 DIMM connector

Larg2 fits into a standard DDR2 240 pin DIMM connector e.g FCI 10005639-11107LF (available

from Digikey, mouser etc.). This connector supports the following signals on the Cyclone-V: 1. 92 pairs of GPIO (can be used as single-ended IO) (see 2 below) 2. 8 single ended IO (The permissible VCCIO voltage is 1.8V to 3.3V)

3. Connections to the Ethernet device

4. Connections to the USB OTG device

5. SPI interface on Cyclone-V HPS.

6. I2C interface on Cyclone-V HPS.

7. UART signals on Cyclone-V HPS.

8. Cyclone-V HPS Reset signals.

9. Power supply connections (12V and the FPGA IO supply voltage VCCIO).

The pinout of the DIMM connector is shown below (C5 = Cyclone-V):

SIGNAL

NAME

DIMM

PIN

C5

PIN SIGNAL

NAME DIMM

PIN

C5

PIN SIGNAL

NAME

DIMM

PIN

C5

PIN

I2C1_SDA 1 C14 IO_P_36 81 M15 IO_P_68 161 W16 I2C1_SCL 2 D11 IO_N_36 82 M16 IO_N_68 162 Y16 UART1_TX 3 E5 IO_P_37 83 L17 IO_P_69 163 Y18 UART1_RX 4 C4 IO_N_37 84 M17 IO_N_69 164 AA18 IO_P_0 5 D12 IO_P_38 85 J18 IO_P_70 165 AA21 IO_N_0 6 C12 IO_N_38 86 K18 IO_N_70 166 AB21 IO_P_1 7 E8 IO_P_39 87 H22 IO_P_71 167 Y20 IO_N_1 8 D8 IO_N_39 88 G22 IO_N_71 168 Y21 IO_P_2 9 E11 IO_P_40 89 G15 IO_P_72 169 W20 IO_N_2 10 D11 IO_N_40 90 G16 IO_N_72 170 W21 IO_P_3 11 H6 IO_P_41 91 F21 IO_P_73 171 U20 IO_N_3 12 H5 IO_N_41 92 F22 IO_N_73 172 V20 IO_P_4 13 L8 IO_P_42 93 D22 IO_P_74 173 U15 IO_N_4 14 K8 IO_N_42 94 C22 IO_N_74 174 U16


SIGNAL

NAME

DIMM

PIN

C5

PIN SIGNAL

NAME DIMM

PIN

C5

PIN SIGNAL

NAME

DIMM

PIN

C5

PIN

IO_P_5 15 L10 IO_P_43 95 IO_P_75 175 AF17 IO_N_5 16 L9 IO_N_43 96 IO_N_75 176 AG16 IO_P_6 17 T13 IO_P_44 97 IO_P_76 177 AD17 IO_N_6 18 T12 IO_N_44 98 IO_N_76 178 AE17 IO_P_7 19 U9 IO_P_45 99 IO_P_77 179 Y17 IO_N_7 20 T8 IO_N_45 100 IO_N_77 180 Y18 IO_P_8 21 U14 IO_P_46 101 IO_P_78 181 AE19 IO_N_8 22 U13 IO_N_46 102 IO_N_78 182 AD19 IO_P_9 23 Y5 IO_P_47 103 IO_P_79 183 AF20 IO_N_9 24 Y4 IO_N_47 104 IO_N_79 184 AG20 IO_P_10 25 V12 IO_P_48 105 IO_P_80 185 AF22 IO_N_10 26 W12 IO_N_48 106 IO_N_80 186 AF21 IO_P_11 27 AC4 IO_P_49 107 IO_P_81 187 AD23 IO_N_11 28 AD4 IO_N_49 108 IO_N_81 188 AE22 IO_P_12 29 AE4 IO_P_50 109 IO_P_82 189 AC23 IO_N_12 30 AF4 IO_N_50 110 IO_N_82 190 AC22 IO_P_13 31 AF7 IO_P_51 111 IO_P_83 191 IO_N_13 32 AG6 IO_N_51 112 IO_N_83 192 IO_P_14 33 AD11 IO_P_52 113 IO_P_84 193 IO_N_14 34 AE11 IO_N_52 114 IO_N_84 194 IO_P_15 35 Y13 IO_P_53 115 IO_P_85 195 IO_N_15 36 AA13 IO_N_53 116 IO_N_85 196 IO_P_16 37 AH3 IO_P_54 117 IO_P_86 197 IO_N_16 38 AH2 IO_N_54 118 IO_N_86 198 IO_P_17 39 AG5 IO_P_55 119 IO_P_87 199 IO_N_17 40 AH4 IO_N_55 120 IO_N_87 200 IO_P_18 41 AH6 USB_FLG 121 IO_P_88 201 IO_N_18 42 AH5 I2C0_SDA 122 IO_N_88 202 IO_P_19 43 AG8 I2C0_SCL 123 IO_P_89 203 IO_N_19 44 AH7 I2C0_INT 124 IO_N_89 204 IO_P_20 45 AG9 RST_O_N 125 IO_P_90 205 IO_N_20 46 AH8 RST_N 126 IO_N_90 206 IO_P_21 47 AG10 GND 127 IO_P_91 207 IO_N_21 48 AH9 VCC_12V 128 IO_N_91 208 IO_P_22 49 AG11 VCC_12V 129 GPIO0 209 IO_N_22 50 AH11 GND 130 GPIO1 210 IO_P_23 51 AG14 VCC_12V 131 GPIO2 211 IO_N_23 52 AH13 VCC_12V 132 GPIO3 212 IO_P_24 53 AG15 GND 133 GPIO4 213 AH12 IO_N_24 54 AH14 VCCIO 134 GPIO5 214 V10 IO_P_25 55 AH17 VCCIO 135 GPIO6 215 AF18 IO_N_25 56 AH16 GND 136 GPIO7 216 AH21 IO_P_26 57 AG18 IO_P_56 137 GPIO8 217 AG21 IO_N_26 58 AH18 IO_N_56 138 GPIO9 218 AG26 IO_P_27 59 AG19 IO_P_57 139 T11 GPIO10 219 AH26 IO_N_27 60 AH19 IO_N_57 140 U11 GPIO11 220 AF26 CLK1_P 61 AE20 IO_P_58 141 V11 SPI_MISO 221 B18 CLK1_N 62 AD20 IO_N_58 142 W11 SPI_MOSI 222 C17 CLK2_P 63 AA18 IO_P_59 143 W8 SPI_CS_N 223 J17 CLK2_N 64 AA19 IO_N_59 144 Y8 SPI_CLK 224 A18 IO_P_28 65 AG23 IO_P_60 145 AA4 USB_DP 225 IO_N_28 66 AF23 IO_N_60 146 AB4 USB_DM 226 IO_P_29 67 AE24 IO_P_61 147 Y11 USB_ID 227 IO_N_29 68 AE23 IO_N_61 148 AA11 USB_VBUS 228 IO_P_30 69 AH23 IO_P_62 149 AD5 ETH_ALED 229 IO_N_30 70 AH22 IO_N_62 150 AE6 USB_CPEN 230 IO_P_31 71 AG24 IO_P_63 151 AF5 ETH_P4 231 IO_N_31 72 AH24 IO_N_63 152 AF6 ETH_N4 232 IO_P_31 71 IO_P_0 151 ETH_P4 231 IO_N_31 72 IO_N_0 152 ETH_N4 232


SIGNAL

NAME

DIMM

PIN

C5

PIN SIGNAL

NAME DIMM

PIN

C5

PIN SIGNAL

NAME

DIMM

PIN

C5

PIN

IO_P_32 73 AF25 IO_P_64 153 AE8 ETH_N3 233 IO_N_32 74 AG25 IO_N_64 154 AF9 ETH_P3 234 IO_P_33 75 AG28 IO_P_65 155 AE7 ETH_P2 235 IO_N_33 76 AH27 IO_N_65 156 AF8 ETH_N2 236 IO_P_34 77 AA24 IO_P_66 157 AD10 ETH_N1 237 IO_N_34 78 AA23 IO_N_66 158 AE9 ETH_P1 238 IO_P_35 79 AF27 IO_P_67 159 AF11 ETH_LLED 239 IO_N_35 80 AF28 IO_N_67 160 AF10 ETH_COM1 240


USB

There are two USB interfaces on Larg2:

Fig 6 Larg2 USB

The first USB interface on the Larg2 is achieved using an FT232RQ USB to serial UART

Device. The datasheet and drivers for this device are available from http://www.ftdichip.com.

When appropriate drivers are installed the Larg2 USB port should be detected as a serial port.

The FT232RQ is connected to the ‘outside world’ via the USB mini-B connector J4 and to the

Cyclone-V via the connections shown below:

The second USB device on Larg2 is a USB3300 Host/Device/OTG USB 2.0 PHY. The datasheet can

be found at http://www.microchip.com/, and LINUX drivers are available online.

There is no connector for the USB3300 on Larg2, it is anticipated that the host board will incorporate a

connector. The Larg breakout board has a USB hub which connects to a dual USB type A connector

specifically for this purpose. It also has a USB audio codec with 3.5mm headphone and microphone

jack sockets.

The connections between the USB3300 and the Cyclone-V are shown below:

SIGNAL FT232RQ PIN CYCLONE-V PIN

DATA_HPS_TO_FT232 2 H17

DATA_FT232_TO_HPS 30 A17

http://www.ftdichip.com/http://www.microchip.com/


*The USB_RESET signal is routed to pin 12 of the IO expander (U18), which is controlled by the

I2C1 bus. (See section ‘I2C devices’).

The connections between the USB3300 and the 240-pin DIMM connector are shown below:

SIGNAL USB3300 PIN CYCLONE V

PIN

USB_NXT 11 D5

USB_STP 13 C5

USB_DIR 12 E5

USB_CLK 14 G4

USB_D0 24 C10

USB_D1 23 F5

USB_D2 22 C9

USB_D3 21 C4

USB_D4 20 C8

USB_D5 19 D4

USB_D6 18 C7

USB_D7 17 F4

USB_RESET 9 *

SIGNAL USB3300 PIN DIMM PIN

USB_CPEN 3 230

USB_VBUS 4 228

USB_ID 5 227

USB_DM 8 226

USB_DP 7 225


ETHERNET

Fig7 Larg2 Ethernet device

The Larg2 Ethernet interface uses a Micrel KSZ9021RL device. The KSZ9021RL incorporates a

10/100/1000 Ethernet PHY with an RGMII interface. All datasheets and support documentation can be

found on Micrel’s website www.micrel.com.

The connections between the KSZ9021 and the FPGA are as shown below:

SIGNAL

NAME

KSZ9021

PIN

CYCLONE

V PIN

ETH1_RX0 42 A14

ETH1_RX1 41 A11

ETH1_RX2 38 C15

ETH1_RX3 36 A9

ETH1_TX0 24 A16

ETH1_TX1 25 J14

ETH1_TX2 26 A15

ETH1_TX3 27 D17

ETH1_TX_CLK 32 J15

ETH1_TX_CTL 33 A12

ETH1_RX_CLK 46 J12

ETH1_RX_CTL 43 J13

ETH1_MDC 48 A13

ETH1_MDIO 49 E16

ETH1_INT_N 51 *

ETH1_RESET_N 56 **

*The KSZ9021RL Interrupt signal is routed to pin 6 of the IO Expander.

** The KSZ9021 Reset signal is routed to pin 11 of the IO Expander.

There is no connector for the Ethernet on Larg2, it is anticipated that the host board will incorporate a

connector. The Larg breakout board has a combined Ethernet/dual USB connector for this purpose.

http://www.micrel.com/


The connections between the KSZ9021RL and the 240-pin DIMM connector are shown below:

SIGNAL

NAME

KSZ9021

PIN

DIMM PIN

ETH_TRD_P1 1 238

ETH_TRD_N1 2 237

ETH_TRD_P2 7 235

ETH_TRD_N2 8 236

ETH_TRD_P3 10 234

ETH_TRD_N3 11 233

ETH_TRD_P4 14 231

ETH_TRD_N4 15 232

ETH_COM1 DVDDH 240

ETH_LINKLED 19 239

ETH_ACTLED 21 229

MAC ADDRESS DEVICE

The Larg2 has an I2C MAC address device fitted which assigns the board a unique identity number.

The device used is a 24AA025E64T-I/OT of which further details can be found on

www.microchip.com. The I2C0 bus connects the Mac Address device to the Cyclone-V HPS via the

connections shown below:

SIGNAL MAC ADDRESS PIN CYCLONE V PIN

I2C0_SCL 1 C18

I2C0_SDA 3 A19

www.microchip.com.%20


LEDS

Larg2 has three LEDs. LED1 (blue) connects to the Cyclone-V HPS on pin B21, LED2 (YELLOW)

connects to the Cyclone-V HPS on pin A22, and LED3 (GREEN) connects to the Cyclone-V HPS on

pin C21. Each of these LEDs will be lit when the driving signal is asserted HIGH.

Fig 8 Larg2 LEDs


POWER MONITOR AND RESET SIGNALS

The Larg2 has two STM6719SFWB6F voltage monitors, U3 and U1, which monitor the supply rails

within the board and control the two reset signals. If 3V3 is low or missing the HPS_nPOR reset signal

(connected to Cyclone-V pin H19) is held active. If the 3V3 rail is low or missing the HPS_nRST

signal (connected to Cyclone-V pin A23) is held active. Once the power rails are present each reset

monitor produces a reset pulse of 140 ms to 280 ms, then releases the reset signal, which is then pulled

high by a resistor.

Connector J3 (found at the top right of the Cyclone-V) provides a manual reset facility for the

HPS_nPOR signal by means of adding a 2mm jumper between pins 1 and 2 two pins (the right and

centre pins). If the Larg Breakout board is used, push button PB1 and jumper J6 perform the same

function.

Push button switch SW1 (found above the Cyclone-V device) provides a manual reset facility for the

HPS_nRST signal.

Fig 9 Larg2 Reset devices


OSCILLATORS

There are four oscillators on Larg.

X1 is an ASEM 25MHz oscillator which is connected to pin E20 of the Cyclone-V HPS (HPS_CLK1).

X2 is an ASEM 25MHz oscillator which is connected to pin U10 of the Cyclone-V FPGA (CLKUSR).

X3 is an ASEM 24MHz oscillator which provides a clock signal to the USB OTG device.

X4 is an ASEM 25MHz oscillator which provides a clock signal to the Ethernet device.

The Cyclone-V has PLLs and DCMs to produce multiples, divisions and phases of the clock for

specific application requirements. Please consult the Cyclone-V datasheet available from the Altera

website at http://www.altera.com if multiple clock signals are required.

Fig10 Larg2 Oscillators

http://www.altera.com/


IO EXPANDER

Larg2 has a 16-bit I2C IO Expander (PCAL9555AHF). The control signals connect to the I2C1 signals

on the Cyclone-V HPS. The INT signal connects to a GPIO pin on the Cyclone-V HPS.

The signals connections are shown below:

*I2C control signals.

SIGNAL IO EXPANDER

PIN

CONNECTED TO

I2C1_SDA* 20 Cyclone-V PIN A21

I2C1_SCL* 19 Cyclone-V PIN K18

I2C_INT* 22 Cyclone-V PIN C6

GPIO0 1 DIMM PIN 209




I2C0_INT_N 5 DIMM PIN 124

ETH1_INT_N 6 ETHERNET PHY PIN 51

RESET_OUT_N 10 DIMM PIN 125

ETH1_RESET_N 11 ETHERNET PHY PIN 56

USB_RESET 12 USB 3300 PIN 9


I2C DEVICES

The Larg2 has two I2C busses, I2C0 and I2C, both of which are controlled from the ZYNQ HPS.

I2C0 connects to the MAC address device, I2C1 connects to the IO expander. Both busses are also

routed to the 240-pin DIMM connector as shown below:

SIGNAL Cyclone-V PIN DIMM PIN

I2C0_SDA A19 122

I2C0_SCL C18 123

I2C0_INT_N ** 124

I2C1_SDA A21 1

I2C1_SCL K18 2

EXP_INTERRUPT_N* C6

* This is the interrupt signal from the IO expander

** The I2C0_INT signal is routed to the Larg2 IO expander (pin 5)

The Enterpoint Larg Breakout board uses the I2C0 signals to control an IO Expander with 16 LEDs, 4

each of red, yellow, green and blue and all the I2C signals are also routed to a connector for user

applications.


UART1 AND SPI INTERFACES

The two UART1 signals and the four SPI signals on the Cyclone-V HPS are not used on Larg2,

however they are routed to the 240-pin DIMM connector so that the user can access these signals. The

signals are 3v3 voltage levels and are routed to the connector as shown below:

SIGNAL CYCLONE-V

PIN

DIMM PIN

UART1_RX C19 4

UART1_TX B16 3

SPI_SCLK A18 224

SPI_CS_N J17 223

SPI_MOSI C17 222

SPI MISO B18 221

Enterpoint’s Larg Breakout board uses the UART1 signals to connect to an FT232 serial/USB device,

with a mini B USB connector. The SPI signals are routed to an 8-pin header, with 0v and 3v3 power

pins, for user-defined applications.

SDCARD HOLDER

It is anticipated that an operating system such as LINUX will be resident on a micro SD card, and a

Micro SD Card socket has been provided for this purpose. To use this socket in a design you may need

to obtain a license from the SD Association at http://www.sdcard.org/home/.

The connections between the Micro SD Card Socket and the Cyclone-V HPS are shown below:

SDCARD SOCKET CYCLONE-V

PIN

SD_DATA0 C13

SD_DATA1 B6

SD_DATA2 B11

SD_DATA3 B9

SD_CMD D14

SD_CLK B8

SD_PWREN A5

SD_PRESENT E4

The SD_PWREN pin must be set LOW for power to be supplied to the SDCARD Reader.

http://www.sdcard.org/home/


GPIO

There are 92 P-N pairs of IO connected between the Cyclone-V FPGA and the DIMM connector. For

pin connection information see the section ‘DIMM Interface’.

There are also 12 single-ended IO connected to the DIMM connector. 8 of these (GPIO4 to GPIO11)

are routed to Cyclone-V FPGA IO, the other three (GPIO0 to GPIO3) are routed to the IO Expander.

The IO standard of these signals depends upon the IO voltage supplied to the VCCIO pins of the

DIMM connector by the user. The permissible VCCIO voltage is 1.8V to 3.3V. The Larg Breakout

board has VCCIO fixed at 3.3V.


POWER CONNECTIONS

Larg2 is powered from the DIMM connector. The power pins are shown below:

POWER SUPPLY DIMM PINS

12V 128,129,131,132

GND 127,130,133,136

VCCIO 134,135

The nominal 12V power supply has an allowable range of 4.5V to 28V. The current is limited by a

2.6A resettable fuse.

The allowable range for VCCIO is 1.8V to 3.3V. The current is limited by a 1.1A resettable fuse.

Enterpoint’s Larg Breakout Board has a power regulator to provide VCCIO, and accepts the nominal

12V power via a 2.5mm Jack Socket to allow an off-the-shelf power adapter to be used.


POWER REGULATORS

Fig11 Larg2 Power Regulators

Larg2 has six regulators supplying 3.3V, 2.5V, 1.35V, 1.2V, 1.1V and 0.675V power rails.

WARNING – REGULATORS CAN BECOME HOT IN NORMAL OPERATION ALONG

WITH THE BOARDS THERMAL RELIEF. PLEASE DO NOT TOUCH OR PLACE HIGHLY

FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE LARG2 BOARD IS IN

OPERATION.

A Micrel MIC26601 regulator (U13) supplies 3.3V with a maximum current available of 6A. This

powers the Cyclone-V HPS IO (via a power switch for correct power rail sequencing) and the other

regulators.

An Enpirion EP5322QI regulator (U16) supplies 2.5V with a maximum current of 2A for the Cyclone-

V HPS IO supply.

An Enpirion EP5322QI regulator (U2) supplies 1.35V with a maximum current of 2A for the DDR3

and related FPGA I/O.

An Enpirion EP5388QI regulator (U10) supplies 1.2V with a maximum current of 800mA for the

Ethernet PHY core.

An Enpirion EN6347QI regulator (U9) supplies 1.1V with a maximum current available of 4A. This is

used for the core voltage of the Cyclone-V.

An Altera EV1320QI push-pull regulator (U5) produces up to 2A at 0.675V. This supply is used as

reference and termination voltage for the DDR3 memory and related FPGA I/O.


PROGRAMMING LARG2

The programming of the Cyclone-V and SPI Flash parts on Larg2 is achieved using the JTAG

interface. The Cyclone-V series needs to be programmed using Quartus II version 13.1 or later. The

free Quartus II Lite supports the Cyclone-V device.

There are two JTAG chains on Larg2. J4 allows the programming of the Cyclone-V HPS and its SPI

Flash memory device and J1 supports the Cyclone-V FPGA and its SPI Flash device.

Fig12 Larg2 JTAG Connectors

The JTAG connectors have a layout as follows:

3V3 TMS TCK TDO TDI NC NC

GND GND GND GND GND GND GND

This pinout supports Enterpoint’s PROG4 cable. If you wish to use the Altera USB Blaster (or

equivalent) you will need an adapter. A suitable adapter is available from Enterpoint Ltd.

Fig13 Enterpoint’s Altera JTAG adapter

1. Configuring the HPS.

Larg2 will be shipped with a default configuration in the HPS which will enable the peripherals

connected to the HPS on Larg2 to be accessed, and an SD Card with an implementation of LINUX. It

is necessary to load a minimal configuration into the HPS before the FPGA can be configured. If you

wish to change the default configuration you will need use the Altera SoC EDS Command shell, found

in your Altera Directory:

TOP EDGE OF LARG2 BOARD


Figure 14 Locating the Altera SoC EDS Command Shell

Open the command shell and change directory to the location of your files.

The following files will be required (your file names may differ):

Preloader-mkpimage.bin, Uboot.bin

From the command prompt program the 2 files as follows: quartus_hps –c usb-blaster –o p –a0x00000 preloader-mkpimage.bin

You should verify the file as follows: quartus_hps –c usb-blaster –o v –a0x00000 preloader-mkpimage.bin

Program the second file as follows: quartus_hps –c usb-blaster –o p –a0x60000 uboot.bin

And verify it: quartus_hps –c usb-blaster –o v –a0x60000 uboot.bin

It should now be possible to boot the Larg2 from the image on the SDCard.

2. Configuring the FPGA and the SPI Flash memory

It is necessary to configure the FPGA before the SPI flash memory device can be detected. Plug your

programming cable into J1. Open the QuartusII programmer, check that your programming cable has

been detected correctly, then choose Autodetect. The screen below should appear:

Figure 15 Quartus II programmer screen showing CycloneV

Comment [c1]: Pic probably shows wrong cyclone5 device


Double click the FPGA File and select your .sof file. Tick the Program/Configure check box to enable

the Start Button and press Start to program the FPGA.

Once Complete (Should only take a few seconds) press the Auto Detect button.

The SPI flash device should now be shown attached to the FPGA:

Figure 16 Quartus II programmer screen showing CycloneV and flash memory.

Double click on the EPCQ256 File and select your programming file (.jic). Tick the box in the

'Program/Configure' column for the Flash memory. Select the icon representing the flash memory and

choose ‘Start’ to load your program into the device. A green bar in the top left of the programmer

screen shows the progress. The programming operation will take some time (at least 3 or 4 minutes).

Comment [c2]: Will just any .sof file do or do you need something special in it? –

applies to RS4 too.

Comment [c3]: Pic shows wrong devices

Comment [c4]: Not on Larg2


MECHANICAL ARRANGEMENT

The Dimensions on the drawing below are millimetres (mm). All sizes quoted are subject to

manufacturing tolerances and should only be used as a general guide.

Figure 17 Dimensions of Larg1

The tallest component is the push-button switch SW1:

Figure 18 Larg1 side view (3d model)

The height from the lower side of the PCB to the top of SW1 is approximately 8.5mm.


Medical and Safety Critical Use

Larg2 boards are not authorised for the use in, or use in the design of, medical or other safety critical

systems without the express written person of the Board of Enterpoint. If such use is allowed the said

use will be entirely the responsibility of the user. Enterpoint Ltd will accept no liability for any failure

or defect of the Larg2 board, or its design, when it is used in any medical or safety critical application.

Warranty

Larg2 comes with a 90 day return to base warranty. Do not attempt to solder connections to the Larg2.

Enterpoint reserves the right not honour a warranty if the failure is due to soldering or other

maltreatment of the Larg2 board.

Outside warranty Enterpoint offers a fixed price repair or replacement service. We reserve the right not

to offer this service where a Larg2 has been maltreated or otherwise deliberately damaged. Please

contact support if you need to use this service.

Other specialised warranty programs can be offered to users of multiple Enterpoint products. Please

contact sales on [email protected] if you are interested in these types of warranty,

Support

Please check our FAQ page for this product first before contacting support. FAQ is located at

http://www.enterpoint.co.uk/drigmorn/Larg2_faq.html. Telephone and email support is offered during

normal United Kingdom working hours (GMT or GMT + 1) 9.00am to 5.00pm.

Telephone - +44 (0) 121 288 3945

Email - [email protected]
mailto:[email protected]://www.enterpoint.co.uk/drigmorn/drigmorn3_faq.html

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