larc training ic compiler (icc)larc.web.nthu.edu.tw/ezfiles/674/1674/img/2486/20160726...nthu com/ee...
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
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LaRC Training – IC Compiler (ICC)
黃元豪
Department of Electrical Engineering and Institute of Communications Engineering,
National Tsing-Hua University,
Hsinchu, Taiwan, R.O.C.
2016 LaRC Training
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
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• The “IC design” here refers to “cell-based design” or
“digital IC design”.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• System spec determines how you would design your IC.
• Common specs are clock speed,
chip area, chip power, etc.
• You have to come back to check your
spec in each stage of IC design.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• Architectural design means drawing
the block diagram.
• A carry look ahead (CLA) adder:
• A correlation circuit:
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• Functional and logic design
– Verilog (HDL) code.
– HDL: Hardware Description Language
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• Circuit design here means using
design compiler (DC) to map
(or say synthesis) your Verilog code
into logic gates.
• Compared to functional design, now
the gate delay comes into play, and
you can roughly estimate you chip
speed (clock speed).
• Note that the net (connection) delay
is still not available
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• The main topic today, ICC (IC compiler),
does the physical design for us.
• In brief, physical design refers to (auto)
“place” and “route”.
• The net delay can be estimated now.
• Your chip roughly comes into reality
after the physical design.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• To make sure your chip can work,
it has to pass some tests (verifications).
• DRC: Design Rule Check
• LVS: Layout Versus Schematic
• ERC: Electrical Rule Chick
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
IC Design Flow
• Fabrication: 製造 (TSMC)
• Packaging:封裝 Testing: 測試
(日月光)
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow
• Details of physical design.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow – Design Setup
• In design setup, we load the
necessary files to prepare for
our physical design.
• top_syn.v: the gate level netlist,
which is generated (synthesized)
by the design compiler.
• top_syn.sdc: the Standard Delay
Constraint file. It tells ICC the
desired spec you want ICC to do.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow – Design Setup
• .tf file: this technology file contains
metal layer technology parameters
(Ex. design rules, 最小寬度等)
• Reference library: the standard
cell libraries (with characteristics)
which are unique to each
technology.
• .tluplus file: this specifies the RC
models so net delay can be
calculated.
• .map file: this file translates the
names in .tf file to ICC.12
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow – Design Planning
• Design planning defines the floorplan (格局, 藍圖).
• Ex.
– Tall cell or fat cell?
– How dense do you want the standard cells to be in the chip?
– How do you want to arrange the electrical pipes?
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow - Placement
• “Placement” performs iterative
placement and optimization for
the standard cells.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow - CTS
• CTS means Clock Tree Synthesis.
• CTS builds the clock trees.
• CTS can also fix hold time
violations and do some
placement optimization.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow - Route
• “Route” connects the placed
standard cells with metal
wires.
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NTHU COM/EE Communication VLSI Lab Y.H.Huang
Physical Design Flow - DFM
• DFM means Design For Manufacturing.
• For instance, DFM does filler
cell insertion to make the chip
density more uniform.
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