jntu anan ece 2 2 stld set 2

7/28/2019 Jntu Anan Ece 2 2 Stld Set 2

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S.13Switching Theory and Logic Design (April/May-2012, Set-2) JNTU-Anantapur

B.Tech. II-Year II-Sem. ( JNTU-Anantapur )

Code No: 9A04401/R09

II B.Tech. II Semester, Regular & Supplementary Examinations

April/May - 2012SWITCHING THEORY & LOGIC DESIGN

( Common to EEE, EIE, E.Con.E, ECE & ECC )

Time: 3 Hours Max. Marks: 70

Answer any FIVE Questions

All Questions carry equal marks

- - -

1. (a) List the decimal numbers 8 to + 7 in sign-magnitude, sign-1's complement and sign-2's complement represen-

tation and conclude the advantage of 2's complement representation in computers. (Unit-I, Topic No. 1.2)

(b) What is the advantage of 2's complement representation in computers? Perform the following operations using

2's complement method:

(i) (+ 55) (+ 15)

(ii) ( 55) ( 15). (Unit-I, Topic No. 1.2)

2. (a) State and prove De Morgans laws. Mention gate equivalents. (Unit-II, Topic No. 2.1)

(b) Determine the canonical sum of products form of the following function:

f(x, y, z) = z + (x' + y) (x + y'). (Unit-II, Topic No. 2.2)

(c) Realize XOR gate using minimum number of NAND gates. (Unit-II, Topic No. 2.3)

3. Simplify the following Boolean expressions using K-map and implement them using NOR gates:

(i) F(A, B, C, D) = AB'C' + AC + A'CD'(ii) F(W, X, Y, Z) = W'X'Y'Z' + WXY'Z' + W'X'YZ + WXYZ.(Unit-III, Topic No. 3.1)

4. A combinational circuit has four inputs and one output. The output is equal to 1 when,

(i) All the inputs are equal to 1 (or)

(ii) None of the inputs are equal to 1 (or)

(iii) When even number of inputs are equal to 1

Design the above circuit using logic gates. (Unit-IV, Topic No. 4.1)

5. Program a 3 input and 4 output PLA circuit to implement the sum and carry outputs of a full adder.

(Unit-V, Topic No. 5.1)

6. (a) Show how mod-12 JK counter could be built using mod-3 and mod-4 counters. (Unit-VI, Topic No. 6.3)

(b) Explain the steps in synchronous sequential circuit design. (Unit-VI, Topic No. 6.2)

7. Explain the following related to sequential circuits with suitable examples:

(a) State diagram

(b) State table

(c) State assignment. (Unit-VII, Topic No. 7.1)

8. (a) Explain the symbols used in an ASM chart with neat diagrams. (Unit-VIII, Topic No. 8.1)

(b) Explain the important features of the ASM chart. (Unit-VIII, Topic No. 8.1)

S e t - 2S o l u t i o n s


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S.14 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013


Q1. (a) List the decimal numbers 8 to + 7 in sign-magnitude, sign-1's complement and sign-2'scomplement representation and conclude the advantage of 2's complement representationin computers.

Answer : April/May-12, Set-2, Q1(a)

The given decimal numbers range is,

8 to + 7

Table shows the representation of the given numbers in sign-magnitude, 1's complement ad 2's complement form.

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

00000000

11111111

11111110

11111101

11111100

11111011

11111010

11111001

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

11111110

11111101

11111100

11111011

11111010

11111001

11111000

10001000

10000111

10000110

10000101

10000100

10000011

10000010

10000001

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

2s Complement

Form

1s Complement

Form

Sign-magnitude

Form

Decimal

Numbers

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

00000000

11111111

11111110

11111101

11111100

11111011

11111010

11111001

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

11111110

11111101

11111100

11111011

11111010

11111001

11111000

10001000

10000111

10000110

10000101

10000100

10000011

10000010

10000001

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

2s Complement

Form

1s Complement

Form

Sign-magnitude

Form

Decimal

Numbers

Table

Advantage of 2's Complement Representation in Computers

The use of 2's complement format to represent the binary numbers in computers is very simple. Also, the number of

steps required to obtain the result of addition/subtraction is less.

(b) What is the advantage of 2's complement representation in computers? Perform the follow-ing operations using 2's complement method:

(i) (+ 55) (+ 15)(ii) ( 55) ( 15).

Answer : April/May-12, Set-2, Q1(b)

Advantage of 2's Complement Representation in Computers

For answer refer April/May-12, Set-2, Q1(a), Topic: Advantage of 2's Complement Representation in Computers.

(i) Given that,

(+ 55) (+ 15)

Substraction using 2's complement method is the addition of minuend and 2's complement of subtrahend.

Step-1

Binary representation of + 55 is (+ 55) = (00110111)2

SOLUTIONS TO APRIL/MAY-2012, SET-2, QP


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Step-2

Binary representation of + 15 is, (+ 15) = (00001111)2

Step-3

2's complement representation of + 15 is = 11110001

Step-4

Then,

(+ 55) (+ 15) using 2's complement method is obtained as,

0011011111110001

001010001

+

Carrydiscarded

0011011111110001

001010001

+

Carrydiscarded

00101000)15()55( =++

(ii) Given that,

( 55) ( 15)

Step-1

2's complement representation of ( 55) is obtained as,

= Complement of (55) + 1


= 001000 + 1 = 001001

Step-2

2's complement representation of ( 15) is obtained as,



= 0000 + 1 = 0001

Step-3

2's complement representation of subtrahend is obtained as,

= Complement of ( 15) + 1


= 1110 + 1 = 1111

Step-4

( 55) ( 15) is obtained as,

001001

001111

011000

+

Since, the result obtained is a negative number, which will be in 2s complement form.

( 55) ( 15) = Complement (011000) + 1

= 100111 + 1

= 101000 = 40

( 55) ( 15) 40 =


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Q2. (a) State and prove DeMorgans laws. Mention gate equivalents.


DeMorgans Laws

The Demorgans laws for 4 variables are stated as,

1st Law

DCBA +++ = DCBA

2ndLaw

DCBA = DCBA +++

The above laws can be easily verified by means of truth table as shown below,

A B C D A B C D A + B + C + D DCBA +++ DCBA A B C D DCBA DCBA +++

0 0 0 0 1 1 1 1 0 1 1 0 1 1

0 0 0 1 1 1 1 0 1 0 0 0 1 1

0 0 1 0 1 1 0 1 1 0 0 0 1 1

0 0 1 1 1 1 0 0 1 0 0 0 1 1

0 1 0 0 1 0 1 1 1 0 0 0 1 1

0 1 0 1 1 0 1 0 1 0 0 0 1 1

0 1 1 0 1 0 0 1 1 0 0 0 1 1

0 1 1 1 1 0 0 0 1 0 0 0 1 1

A B C D A B C D A + B + C + D DCBA +++ DCBA A B C D DCBA DCBA +++

1 0 0 0 0 1 1 1 1 0 0 0 1 1

1 0 0 1 0 1 1 0 1 0 0 0 1 1

1 0 1 0 0 1 0 1 1 0 0 0 1 1

1 0 1 1 0 1 0 0 1 0 0 0 1 1

1 1 0 0 0 0 1 1 1 0 0 0 1 1

1 1 0 1 0 0 1 0 1 0 0 0 1 1

1 1 1 0 0 0 0 1 1 0 0 0 1 1

1 1 1 1 0 0 0 0 1 0 0 1 0 0


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The De Morgans 1st law is equivalent to NOR gate as shown in figure (1),

D.C.B.ADCBAF =+++=

A

BCD

D.C.B.ADCBAF =+++= D.C.B.ADCBAF =+++=

A

BCD

Figure (1): NOR Gate

And, the De Morgans 2nd law is equivalent to NAND gate as shown in figure (2),

D.C.B.ADCBAF =+++=

ABCD

D.C.B.ADCBAF =+++=

ABCD

Figure (2): NAND Gate

(b) Determine the canonical sum of products form of the following function:

f(x, y, z) = z + (x' + y) (x + y').


The given Boolean function is,

f(x,y,z) =z +(x' +y) (x +y')

=z +x'y' +xy

The above expression can be converted into canonical form as,

f(x,y,z) = (x +x') (y +y')z +x'y' (z +z') +xy(z +z')

= (x +x') (yz +y'z) +x'y'z +x'y'z' +xyz +xyz'

=xyz +xy'z +x'yz +x'y'z +x'y'z +x'y'z' +xyz +xyz'

=xyz +xy'z +x'yz +x'y'z +x'y'z' +xyz'

f(x,y,z) =xyz +xyz + xyz + xyz +xyz +xyz

(c) Realize XOR gate using minimum number of NAND gates.

Answer : April/May-12, Set-2, Q2(c)

For answer refer Unit-II, Q21.

Q3. Simplify the following Boolean expressions using K-map and implement them using NOR gates,

(i) F(A, B, C, D) = AB'C' + AC + A'CD'

(ii) F(W, X, Y, Z) = W'X'Y'Z' + WXY'Z' + W'X'YZ + WXYZ.

Answer : April/May-12, Set-2, Q3

For answer refer Unit-III, Q8.


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For the implementation of above expression, the combinational circuit using logic gates can be designed as shown

in figure,

A B C D

F

A B C D

F

Figure

Q5. Program a 3 input and 4 output PLA circuit to implement the sum and carry outputs of a full adder.


Full-adder Implementation using PLA Circuit

The logic diagram and truth table of full-adder circuit are as follows,

A

B

Cin

S = A B Cin

Cout

= (A+B) Cin

+ AB

+ +

A

B

Cin

S = A B Cin

Cout

= (A+B) Cin

+ AB

+ +

Figure (1)


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Inputs Outputs

A B Cin

S Co

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Truth Table

The minimal expressions for sum and carry outputs can be obtained using K-maps.

K-map for Sum S

0 1 3 2

4 5 7 6

1 1

11

00 01 11 10

inCBA

AB Cin

0

1

inCBA

A B Cin

inA BC

0 1 3 2

4 5 7 6

1 1

11

00 01 11 10

inCBA

AB Cin

0

1

inCBA

A B Cin

inA BC

S= inininin CBACBACBACBA +++

K-map for carry Output

1

1 1 1

0 1 3 2

4 5 7 6

00 01 11 10AB Cin

0

1 A B

BCin

ACin

1

1 1 1

0 1 3 2

4 5 7 6

00 01 11 10AB Cin

0

1 A B

BCin

ACin

Cout

=ACin

+BCin

+AB


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The implementation of above expressions using 3-input and 4-output PLA is shown in figure (2).

A B Cin

inCBA

inCBA

inCBA

A B Cin

A Cin

B Cin

A B

S Cout Unused

A B Cin

inCBA

inCBA

inCBA

A B Cin

A Cin

B Cin

A B

S Cout Unused

Figure (2): Implementation of Full-adder using PLA

Q6. (a) Show how mod-12 JK counter could be built using mod-3 and mod-4 counters.


The implementation of mod-12 counter using JK-flip flop can be built with the help of mod-3 and mod-4 counters as

mentioned below.

Initially, consider the implementation of mod-3 counter using JK-flipflop. This counter consists of three states,

which requires two JK-flip-flops. The excitation table of mod-3 counter using JK-flip-flop is shown in table (1).

Present State Next State Flipflop Inputs

QA

QB

*AQ

*BQ JA KA JB KB

0 0 0 1 0 1

0 1 1 0 1 1

1 0 0 0 1 0

1 1

Table (1)


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For JA

For KA

1

1

0

0 1

QB

QA

QB

JA = QB

1

1

0

0 1

QB

QA

QB

JA = QB

11

0

0 1

QB

QA

1

KA = 1

11

0

0 1

QB

QA

1

KA = 1

For JB

For KB

1

1

0

0 1QB

QA

B AJ Q

AQ

1

1

0

0 1QB

QA

B AJ Q

AQ 1

1

0

0 1QB

QA

1

B1K

1

1

0

0 1QB

QA

1

B1K

Then, the implementation of mod-3 counter using JK-flip-flop is shown in figure (1).

JA QA

KA

QA

JB QB

KB

QB

Logic 1

JA QA

KA

QA

JB QB

KB

QB

Logic 1

Figure (1)

Now, consider the implementation of mod-4 counter using JK-flip-flop. This counter consists of four states, which

requires two JK-flip-flops. The excitation table of mod-4 counter using JK-flip-flop is shown in figure (2).

Present State Next State Flipflop Inputs

QC

QD

*CQ

*DQ JC KC JD KD

0 0 0 1 0 1

0 1 1 0 1 1

1 0 1 1 0 1

1 1 0 0 1 1

Table (2)

For JC

For KC

1

1

0

0 1QD

QC

QD

JC = QD

1

1

0

0 1QD

QC

QD

JC = QD

11

0

0 1QD

QC

QD

KC = QD

11

0

0 1QD

QC

QD

KC = QD


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For JD

For KD

1

1

0

0 1Q

D

QC

11

JD = 1

1

1

0

0 1Q

D

QC

11

JD = 1

1

11

0

0 1Q

D

QC

1

KD = 1

1

11

0

0 1Q

D

QC

1

KD = 1

Then, the implementation of mod-4 counter using JK-flip flop is shown in figure (2).

JC

QC

KC QC

JD

QD

KD QD

Logic 1J

CQ

C

KC QC

JD

QD

KD QD

Logic 1

Figure (2)

Then, the implementation of mod-12 counter using mod-3 and mod-4 counters is shown in figure (3).

JA

QA

KA QA

JB

QB

KB QB

JC

QC

KC QC

JD

QD

KD QD

Logic 1

Modulo-3 counter Modulo-4 counter

JA

QA

KA QA

JA

QA

KA QA

JB

QB

KB QB

JC

QC

KC QC

JD

QD

KD QD

Logic 1

Modulo-3 counter Modulo-4 counter

Figure (3)In figure (3), the modification is done in mod-3 counter part to make a connection between two sections. The

modification is also a simple AND connection ofQC

and QD

, which is connected to all inputs of flip flops present in mod-3

counter section (i.e.,JA, K

A,J

Band K

B). The operation of circuit shown in figure (3) is shown in table (3).

Present State Next State

QA

QB

QC

QD

*AQ

*BQ

*CQ

*DQ

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 10 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 1 0 1 0

1 0 1 0 1 0 1 1

1 0 1 1 0 0 0 0

Table (3)

For table (3) it is clear that the implementaton shown in figure (3) will function as a mod-12 counter.


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(b) Explain the steps in synchronous sequential circuit design.


Step-1: State table must be obtained from the given information such as a state diagram, a timing diagram or any otherinformation.

Let us consider a state diagram shown below,

00

1001

11

0|0

0|0

1|0

1|1

1|0

0|0

1|0

0|0

00

1001

11

0|0

0|0

1|0

1|1

1|0

0|0

1|0

0|0

The state table can be obtained as,

Present StateNext State Output

x = 0 x = 1 x = 0 x = 1

00 00 10 0 0

10 11 10 0 1

11 01 11 0 0

01 01 00 0 0

Step-2: If possible, the total number of states must be reduced using state reduction technique.

Step-3: If the represented states are in alphabetical form then binary values must be assigned to each state in the state table.

Step-4: This step is used to determine the total number of flip-flops required to design the circuit.

Step-5: Based on the obtained data, the type of flip-flop should be chosen.

Step-6: From the obtained state table, the circuit excitation and output tables must be derived.

Step-7: Circuit output functions and flip-flop input functions must be derived using K-map or any other method.

Step-8: Finally, by using the circuit output functions and flip-flop input function obtained in step-7, sketch the logic diagram.

Q7. Explain the following related to sequential circuits with suitable examples:

(a) State diagram

(b) State table

(c) State assignment.


For answer refer Unit-VII, Q2.

Q8. (a) Explain the symbols used in an ASM chart with neat diagrams.


For answer refer Unit-VIII, Q1.

(b) Explain the important features of the ASM chart.


For answer refer April/May-11, Set-1, Q8(a).

jntu anan ece 2 2 stld set 2

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