jean-pierre colinge university of california davis, ca, usa jean-pierre colinge university of...
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![Page 1: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/1.jpg)
Jean-Pierre ColingeUniversity of California
Davis, CA, USA
Jean-Pierre ColingeUniversity of California
Davis, CA, USA
![Page 2: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/2.jpg)
◊ Introduction (Where SOI Technology stands today)
◊ SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond®)
◊ The “Classical” SOI MOSFET (Partially/Fully Depleted)
◊ Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates)
◊ SOI Circuits (Hi-T°, Low-Power, RAMs)
![Page 3: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/3.jpg)
◊ Introduction (Where SOI Technology stands today)
◊ SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond®)
◊ The “Classical” SOI MOSFET (Partially/Fully Depleted)
◊ Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates)
◊ SOI Circuits (Hi-T°, Low-Power, RAMs)
![Page 4: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/4.jpg)
MAINSTREAM
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IBM PD MicroprocessorMotorola PD/FD MicroprocessorAMD PD/FD MicroprocessorTI PD VariousHP PD MicroprocessorPeregrine FD (SOS) RF, logic, EEPROM
analog, Rad-hard
Synova PD Rad-HardHoneywell PD Hi-T°; Rad-hardLincoln Lab FD Low-power, Rad-hard
US Semiconductor Manufacturers Using SOIUS Semiconductor Manufacturers Using SOI
SOI news web site: http://www.soisolutions.com
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Advertisement page in USA Today, in Oct. 2000: IBM uses SOI and copper for its top-of-line servers
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G4
* 0.15 m copper process for initial G4 product (migrating to 1 GHz) * up to 1 GHz
G5
* 0.1 m process with initial G5 product* 2 GHz
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CLEARWATER, FLA. FEBRUARY 4, 1999 - Honeywell Space Systems and Motorola Semiconductor Products Sector today announced a joint licensing agreement for PowerPC* technology for use in Honeywell space processors. The result will be a next generation space microprocessor which will be radiation hardened to withstand the destructive effects of space, will operate with Power PC software and use less power.Internally, Honeywell is referring to this next generation microprocessor as the Space Processor Chip (SpacePC). It combines the capabilities of the advanced Motorola PowerPC 603e microprocessor with Honeywell’s radiation and performance enhancing Silicon On Insulator (SOI) technology.
CLEARWATER, FLA. FEBRUARY 4, 1999 - Honeywell Space Systems and Motorola Semiconductor Products Sector today announced a joint licensing agreement for PowerPC* technology for use in Honeywell space processors. The result will be a next generation space microprocessor which will be radiation hardened to withstand the destructive effects of space, will operate with Power PC software and use less power.Internally, Honeywell is referring to this next generation microprocessor as the Space Processor Chip (SpacePC). It combines the capabilities of the advanced Motorola PowerPC 603e microprocessor with Honeywell’s radiation and performance enhancing Silicon On Insulator (SOI) technology.
IBM
Motorola
Power PC
Honeywell
![Page 10: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/10.jpg)
◊ Introduction (Where SOI Technology stands today)
◊ SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond®)
◊ The “Classical” SOI MOSFET (Partially/Fully Depleted)
◊ Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates)
◊ SOI Circuits (Hi-T°, Low-Power, RAMs)
![Page 11: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/11.jpg)
Silicon on SapphireSilicon on Sapphire
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Silicon on SapphireSilicon on Sapphire
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SIMOXSIMOX
Silicon substrate
Oxygen ion implantation
Silicon substrateannealing
Buried oxide layer (BOX)
Silicon overlayer
[O] 66%
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SIMOX,
circa1985
SIMOX, 1998
3,000dislocations/cm2
1,000,000,000dislocations/cm2
SIMOXSIMOX
SiliconSilicon
BOX BOX
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Si-handle wafer
SiO2
Si wafer (future SOI layer)
Bonding
Polishing/etching
Etch-back
Wafer Bonding and Etch BackWafer Bonding and Etch Back
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Wafer BondingWafer Bonding
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H+ implant
Wafer A
Wafer A
Wafer B
Wafer A
Wafer B
Wafer A to be used next as Wafer B
Wafer B
A B
C D
Smart-Cut®
/ Unibond®Smart-Cut
® / Unibond
®
![Page 18: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/18.jpg)
◊ Introduction (Where SOI Technology stands today)
◊ SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond®)
◊ The “Classical” SOI MOSFET (Partially/Fully Depleted)
◊ Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates)
◊ SOI Circuits (Hi-T°, Low-Power, RAMs)
![Page 19: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/19.jpg)
P- type silicon
Depletion zoneN + Source N + Drain
GateGate Oxide
Buried oxide
0.1-
0.2
µm
P- type silicon
Depletion zoneN+ Source N+ Drain
GateGate Oxide
0.1
µm
1 m
m
P- type silicon
Depletion zoneN+ Source N+ Drain
GateGate Oxide
Buried oxide
< 0
.1 µ
m
MOSFETsMOSFETs
Bulk
Fully Depleted SOI
Partially Depleted SOI
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0 1 2 3 4 510 -9
10 -8
10 -7
Supply voltage (V)
Dra
in c
apac
itan
ce (
F/cm
2 ) Bulk, NB=1017 cm-3
SOI, P+ drain on P-substrate, tBOX=400 nm, NB=1015 cm-3
SOI, N+ drain on P-substrate, tBOX=400 nm, NB=1015 cm-3
Source and Drain CapacitanceSource and Drain Capacitance
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Gate
Source (N+) Drain (N+) tsi
Buried oxide tox2
Back gate (mechanical substrate)
tox1
Vg1
Vds
Vg2
P
SOI MOSFET: a few definitionsSOI MOSFET: a few definitions
FD: 30-80 nmPD:100-200 nm
60-400 nm
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Field IsolationField Isolation
LOCOS
Mesa
STI
PossibleEdgeLeakage
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Edge LeakageEdge Leakage
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Source Drain
Gate
Substrate contact
N+N+
P+
A
Source
Drain
Gate
Subst
rate
conta
ct
Subst
rate
conta
ct
B
N+
N+
P+ P+Source Drain
Gate
N+
N+
P+
P+
Edge Leakage Elimination
AndBody Ties
Edge Leakage Elimination
AndBody Ties
Source Drain
Gate
N+N+
A
Source
Drain
Gate
N+
N+ B
A: Regular SOI MOSFET; B: Edgeless device
A: Lateral body tie; B: H-gate body tieBody ties in source
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Source Drain
Gate
Silicon wafer (back gate)
E-fieldlines
SOI MOSFET: DIBLSOI MOSFET: DIBL
or: Drain-Induced Barrier Loweringor: Drain-Induced Barrier Lowering
Electric field lines from the drain encroach on the channel region. Any increase of drain voltage decreases the threshold voltage (the “NPN” potential barrier between source and drain is lowered).
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SOI MOSFETSOI MOSFET
PDSOI MOSFETPDSOI MOSFET FDSOI MOSFETFDSOI MOSFETPro: better VTH controlCon: floating substrate effectsRemedy: Body tie
Pro: better electrical propertiesCon: worse VTH control*Remedy: Uniform SOI material
OFFSPRING
Hybrid (DTMOS, MTCMOS)
OFFSPRING
Double gateMultiple gateBuried ground plane electrode
* VTH < 9 mV in literature
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Source Drain
Front Gate
Back Gate
PDSOI MOSFETPDSOI MOSFET
![Page 28: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/28.jpg)
PDSOI MOSFET: Kink Effect
PDSOI MOSFET: Kink Effect
Source Drain
Front Gate
Back Gate
1. Impact ionization
2. Hole injection in floating substrate
3. Forward bias diode
4. Increase of floating body potential
5. Reduces VTH
6. Increases current
12
43
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Drain Voltage
Dra
in C
urre
ntPDSOI MOSFET:
Kink Effect
PDSOI MOSFET: Kink Effect
Current is increased(GOOD!)
Output conductance(or Early voltage)
is very poor(BAD!)
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Incr
ease
d
dra
in v
olt
age
a
b
c
Gate Voltage
Log
(d
rain
cu
rren
t)c
ba
0 V
Illustration of the single-transistor latch. "Normal" subthreshold slope at low drain voltage (a), infinite subthreshold slope and hysteresis (b), and device "latch-up" (c).
SOI MOSFET: Single-Transistor Latchup
SOI MOSFET: Single-Transistor Latchup
Source Drain
Front Gate
Back Gate
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Source Drain
Front Gate
Back Gate
PDSOI MOSFET: floating-body effectsPDSOI MOSFET: floating-body effects
VG
ID
250 s
VG
ID
20 s
This is only one exampleamong MANY!
Floating body
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ID CoxW
LVG VTH VD
1
2n VD
2
IDsat 1
2n Cox
W
LVG VTH 2
S = nkT
qln(10)
gm
IDVA
q
n kTVA (VA Earlyvoltage)
gm
IDVA
2 Cox W L
n IDVA
Non saturation:
Saturation:
Subthreshold swing:
Gain (weak inversion):
Gain (strong inversion):
MOSFET Equations: Body FactorMOSFET Equations: Body Factor
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S
G
D S
G
D
s
Vg
s1
Vg
s2
Bulk SOI
Cox
Cdepl
CoxfCsi
Coxb
Oxide
Gate - Channel CouplingGate - Channel Coupling
Body factor: n = …1.5… in Bulk; n = …1.05... in FDSOI
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10-
10-
10-
10-
10-
10-
10-
10-
10-
10-
1.00.50.0-0.5-1.0
Gate voltage
Dra
in c
urre
nt [
A]
P-channel N-channel
Transistor characteristics
W = L = 3µm VDS = ±50mV
Vth = ±0.4V Ioff = 1pA/µm
-12
-11
-10
-9
-8
-7
-6
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BESOI 1 - - - 14 5 / 6.4 SIMOX 1 - - - 11 5 / 4.4 SOS 0.35 3 10 23 56 - / - SIMOX 0.32 3 33 14 21 3 / 13.4 SIMOX 0.25 3 41 23.6 32 1.5 / 17.5 SIMOX 0.75 0.9 3 10 11 1.5 / 9 SIMOX 0.75 0.9 10 12.9 30 - / 13.9 (10.4¥) SIMOX 0.3 2 - - 24.3 0.9 / 14 SOS* 0.5 2 2 26 60 1.7 / 16.3 SIMOX 0.2 2 125 28.4 46 1/15.3† SIMOX 0.07 1.5 5 150
(*) Metal-gate technology is used; (†) at 3 GHz and (¥) at 5 GHz.
SOI material
L (µm)
VD (V)
ID (mA)
fmax (GHz)
fT (GHz)
Noise figure / Associated gain (dB) at 2GHz
Microwave SOI MOSFETs
Unibond 0.25 1.5 50 75
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100101.1-10
0
10
20
30
H21 (dB)MAG (dB)ULG (dB)
Frequency (GHz)
Gai
n (d
B)
VDS=VGS=1 V L=0.75 µm NiSi (2.8 ohm/sq.)
Low-voltage Microwave MOSFET
Rather unsophisticated device: tox = 30 nm …
![Page 37: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/37.jpg)
◊ Introduction (Where SOI Technology stands today)
◊ SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond®)
◊ The “Classical” SOI MOSFET (Partially/Fully Depleted)
◊ Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates)
◊ SOI Circuits (Hi-T°, Low-Power, RAMs)
![Page 38: Jean-Pierre Colinge University of California Davis, CA, USA Jean-Pierre Colinge University of California Davis, CA, USA](https://reader035.vdocuments.site/reader035/viewer/2022062322/56649eb25503460f94bb84c4/html5/thumbnails/38.jpg)
Emitter (Source)
Collector (Drain)
Gate
Base
Buried Oxide
Emitter (Source)
Collector (Drain)
Gate
Base
Buried Oxide
Hybrid bipolar-MOS aka DTMOS (Dual-Threshold MOS)
aka MTCMOS (Multiple-Threshold CMOS)
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1001010.11
10
Power/stage (µW)
Del
ay/s
tage
(ns
))
Vdd=0.7 V
0.8 V1.0 V0.9 V
1 fJ
10 fJ
100 fJ
2.52.01.51.00.50
100
200
300
400
500
600
700
Vdd (V)D
elay
/gat
e (p
s)
Hybrid device
CMOS/SOI
Leff,N = 0.45 m, Leff,P = 0.58 m(1987)
Leff,N = Leff,P = 0.3 m(1994)
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(Double-Gate MOSFET)
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Increasing gate voltageDepth in silicon film
(0 to 40 nm)
Electron concentration (cm-3)
1016
VT
tsi=40 nm
Double-Gate SOI MOSFET:Volume Inversion
Double-Gate SOI MOSFET:Volume Inversion
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543210-1-2-3-4-510 -12
10 -11
10 -10
10 -9
10 -8
10 -7
10 -6
10 -5
Gate voltage [V]
Dra
in c
urre
nt [
A]
300°C300°C
200°C 200°C
20°C
P-channel N-channel
W = L = 3µm
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Ground Plane SOI MOSFETGround Plane SOI MOSFET
"The ground-plane concept for the reduction of short-channel effects in fully depleted SOI devices", Ernst, T., and Cristoloveanu, S., Electrochemical Society Proceedings 99-3, p. 329, 1999
Source Drain
Gate
Silicon wafer (back gate)
E-fieldlines
Source Drain
Gate
Silicon wafer (back gate)E-fieldlines
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Boron doping concentration
1019 cm-3
1015 cm-3
Source Drain
buried oxide
Gate
Doping concentration
contour plot
L = 0.1 µm
Distance (micrometres)
Dis
tanc
e (m
icro
met
res)
Ground-Plane SOI MOSFETGround-Plane SOI MOSFETP+ implanted ground plane (in Si wafer)
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Potential
0 V
1.5 V
Source Drain
buried oxide
Gate
Potential contour plot
L = 0.1 µm VG = 0 V
VDS = 1.5 V
Distance (micrometres)
Dis
tanc
e (m
icro
met
res)
Potential
0 V
1.5 V
Source DrainGate
Potential contour plot
L = 0.1 µm VG = 0 V
VDS = 1.5 V
Distance (micrometres)
Dis
tanc
e (m
icro
met
res)
buried oxide
Ground-Plane SOI MOSFETGround-Plane SOI MOSFETEquipotentials (Regular SOI MOSFET)
Equipotentials (Ground-Plane SOI MOSFET)
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L (nm) S (mV/dec) SGP (mV/dec) DIBL (mV) DILBGP (mV)
50 99 89 350 260
70 91 84 272 190
100 83 77 190 120
200 74 71 80 70
500 71 69 45 40
Regular FD SOI vs. Ground-Plane FD SOIRegular FD SOI vs. Ground-Plane FD SOI
RegularSOI MOSFET
RegularSOI MOSFET
Ground-PlaneSOI MOSFET
Ground-PlaneSOI MOSFET
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Double-Gate SOI MOSFETDouble-Gate SOI MOSFET
J.P. Colinge, M.H. Gao, A. Romano, H. Maes and C. Claeys, Technical Digest of IEDM, p. 595, 1990
Source Drain
Gate
Silicon wafer (back gate)
E-fieldlines
Source Drain
Gate
Silicon wafer (back gate)
GateE-fieldlines
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S
D
G
S
DG
S
DG
S
DG
S
DG
1 2 3 4 5Buried Oxide
Different gate configurations for SOI devices: 1) single gate; 2) double gate; 3) triple gate; 4) quadruple gate (or: gate-all-around structure); 5) ∏-gate MOSFET.
Multiple-Gate SOI MOSFETscMultiple-Gate SOI MOSFETsc
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DIBL in fully depleted SOI MOSFETs with different gate structures and different effective gate lengths. VDS = 100 mV.
Gate length (nm)
Multiple-Gate SOI MOSFETscMultiple-Gate SOI MOSFETsc
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◊ Introduction (Where SOI Technology stands today)
◊ SOI Materials (SOS, SIMOX, Wafer Bonding, Unibond®)
◊ The “Classical” SOI MOSFET (Partially/Fully Depleted)
◊ Other SOI MOSFETs (Hybrid, Double Gate, Ground Plane, multiple gates)
◊ SOI Circuits (Hi-T°, Low-Power, RAMs)
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N-well
0V
Vin1=5V
Vin2=0V
Vin
1=5V
Vin
2=0V
5V
5V
0V
5V
Leakage currents
0V
Vin1=5V
Vin2=0V
Vin
1=5V
Vin
2=0V
5V
5V
0V
5V
Leakage current
Leakage currents: example of NAND gate
Bulk SOI
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109
108
107
106
105
104
103
102
101
100
0
20
40
60
80
100
120
Frequency (Hz)
Ope
n-lo
op g
ain
(dB
)
Phase margin (degrees)
Room temp. CL =10 pF
CL=250 pF
400°C
300°C
200°C
50°C
SOI CMOS operational amplifier: High-temperature operation
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Circuit Vdd Speed Company µcontroller CPU 0.9V 5.7 MHz Motorola 8k-gate 16b ALU 0.5V 40 MHz NTT 300k gate array 1.2V 38 MHz NTT 16x16b multiplier 0.5V 18 ns Toshiba PLL 1.5V 1.1 GHz Sharp 32-bit ALU 0.5V 260 MHz Toshiba 8x8 ATM switch 2V 40 Gb/s NTT 560k master array 1V 50 MHz Mitsubishi 0.2 µm 64b PPC 1.8V 550 MHz IBM 0.25 µm 64b ALPHA 1.5V 600 MHz Samsung
Low-Voltage Circuits Low-Voltage Circuits
10
PD
FD
PD
FD
FD
FD
FD
hybrid
hybrid
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101.11
10
100
Bit rate per link (Gbps)
Num
ber
of l
inks
CMOS
CMOS
BiCMOSHEMT
SIMOX
ATM Switch
5 Gbps
10 Gbps
40 Gbps
Y. Ohtomo, S. Yasuda, M. Nogawa, J. Inoue, K. Yamakoshi, H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe, and K. Takeya, Digest of Technical papers, International Solid-State Circuits Conference, p. 154, 1997
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* Much lower rate of soft errors * Less junction leakage * Reduced bit line capacitance * Higher pass-transistor transfer efficiency
Storage capacitance can be reduced 2-3 Supply voltage can be reduced below 1 V
DRAMsDRAMs
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Year Company Memory chip Vdd
1993 IBM 512 kb SRAM 1V 1993 Mitsubishi 64 kb DRAM 1.5V 1995 Samsung 16 Mb DRAM 1996 Mitsubishi 16Mb DRAM 0.9 V 1997 Hyundai 1 Gb DRAM 2 V
Low-Voltage Memories
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1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000
16k
64k
256k
1M
16M
1G
1 Gb
1 Mb
1 kb1k 4k
SOI RAMs
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SOI now used in commercial products
PD and FD SOI MOSFET physics
Advanced SOI MOSFET structures