colinge cork

EUROSOI 2008 – Short Course January 23, 2008, Cork, Ireland

1EUROSOI TutorialCork, 23 January 2008

The SOI MOSFET:

from Single Gate

to Multigate

Jean-Pierre Colinge

Silicon Research Group

Tyndall National Institute, Cork, Ireland


1995 2000 2005 2010 2015 2020

108

1010

1012

Year

Tra

nsis

tors

per

chip

DRAM

Microprocessor

Moore’s law

64Gb Flash

Number of stars in our galaxy

9



bi

ox

Sibi

el

dep

el

ox

el

j

ox

Si VEIVL

t

L

t

L

xSCE

64.0164.02

2

!"#

$%&

'()

Electrostatic Integrity in A: bulk, B: fully depleted SOI, and C: double-gate MOSFETs

DS

ox

SiDS

el

dep

el

ox

el

j

ox

Si VEIVL

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xDIBL

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'()

DIBLSCEVV THTH **) +

xj t

dep

tBOX

tSi

tSi

BulkFD

SOI DG

el

dep

el

ox

el

j

L

t

L

t

L

xEI "

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2

2

1el

BOXSi

el

ox

el

Si

L

tt

L

t

L

tEI

,("#

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'()

2

2

1el

Si

el

ox

el

Si

L

t

L

t

L

tEI

2/4/1

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"#

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A B C

Voltage-Doping Transformation

Electrostatic Integrity (EI)


Gate length (nm)

100 3003010 1000

100

30

10

300

DIB

L (

mV

)

DG

Bulk

FDSOI

Typical drain-induced barrier lowering in bulk, fully depleted SOI (FDSOI) and

double-gate (DG) MOSFETs calculated by MASTAR


10



2008 2010 2012 2014 2016 2018 20205

10

15

20

25

30

35

40BulkFDSOIDG

Bul

kM

OSFET

limit

FDSOI MOSFET limit

HP

LSTP

LOP

Year

Ga

le le

ng

th (

nm

)x

Evolution of gate length predicted by the 2005 ITRS for high-performance (HP),

low operating power (LOP), and low standby power (LSTP) digital circuits



1. T. Skotnicki, G. Merckel, T. Pedron: The voltage-doping transformation: a new approach to the modeling of

MOSFET short-channel effects. IEEE Electron Device Letters 9, 109 (1988)

2. T. Skotnicki : Heading for decananometer CMOS - is navigation among icebergs still a viable strategy?

Proceedings of the 30th European Solid-State Device Research Conference. Frontier Group, Gif-sur-Yvette,

France, 19 (2000)

3. T. Skotnicki: Ultimate scaling of SOI MOSFETs. MIGAS Short Course, Villard de Lans, France (2004)

4. T. Skotnicki, C. Denat, P. Senn, G. Merckel, B. Hennion: A new analog/digital CAD model for sub-

halfmicron MOSFETs. Technical Digest of the International Electron Devices Meeting (IEDM), 165 (1994)

5. T. Skotnicki, F. Boeuf, R. Cerutti, S. Monfray, C. Fenouillet-Beranger, M. Muller, A. Pouydebasque: New

materials and device architectures for the end-of-roadmap CMOS nodes. Materials Science & Engineering B

(Solid-State Materials for Advanced Technology) 124-125, 3 (2005)

6. T. Skotnicki, J.A. Hutchby, Tsu-Jae King, H.-S.P. Wong, F. Boeuf: The end of CMOS scaling: toward the

introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and

Devices Magazine 21-1, 16 (2005)

7. T. Skotnicki and F. Boeuf: CMOS Technology Roadmap – Approaching Up-hill Specials, Proceedings of the

9th Intl. Symp. On Silicon Materials Science and Technology, ECS Volume 2002-2, 720, 2002

Electrostatic Integrity: references

11



1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004

Partially Depleted SOI MOSFET

SOS MOSFET

Fully Depleted SOI MOSFET

XMOS

DELTA

MFXMOS

Double-gate GAA MOSFET

FinFETQuantum-wire MOSFET

Trigate MOSFET

Triple

gate

Triple+

gate

Year: 2006

Surround

gate

MIGFET

VCBM, DTMOS, MTCMOSSingle

gate

Double

gate

--Gate MOSFET

.-Gate MOSFET

CYNTHIA Surround-gate transistor

Nano-Beam Stacked Channels MOSFET

SON MOSFET

MBCFET/TSNWFET

2008

/-Gate

Multi-Gate MOSFET “Family Tree”

Commercial production

Commercial production

AMD, IBM, Freescale, Sony/Toshiba

OKI, EM Microelectronic …


Gate

Source Drain

Buried oxide

Back gate (substrate)

Source

Drain

Gate

ID

Buried oxide

20 nm

Polysilicon Gate

Silicon

Fin

Buried Oxide

Gate

Source Drain

BOX

Gat

e

Gat

e

“1 Gate”“1 Gate”

“2 Gates”“2 Gates”

“3 Gates”“3 Gates”

Evolution of Transistors

“Gate-all-Around”“Gate-all-Around”

Source DrainGate

12



DELTA

Double-gate GAA MOSFET

FinFET

MIGFET

SON MOSFET

1990 1992 1994 1996 1998 2000 2002 2004 2006

a o ea Stac ed C a e s OS

Drain

Gate

Source

IMEC, 1990

Hitachi, 1990

Hitachi, UC Berkeley,

Nippon Steel, NKK,

1998

Double-Gate Transistors


Quantum-wire MOSFET

Trigate MOSFET

--Gate MOSFET

.-Gate MOSFET

Univ. Louvain, 1995

1994 1996 1998 2000 2002 2004 2006

Drain

Source

Pitch

W

Intel, 2002

TSMC, 2002

Triple-Gate Transistors

/-gate MOSFET

13



50 nm

0.2 µm

20 nm

56.5 nm

11.1 nm

1.7 nm

5.7 nm

4.2 nm

Photo: Courtesy Infineon and Texas Instruments, Inc.

Device Research Conference, 2006

Triple+-Gate Transistor: - gate


Nanowire MOSFET

"High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices",

Singh, N.; Agarwal, A.; Bera, L.K.; Liow, T.Y.; Yang, R.; Rustagi, S.C.; Tung, C.H.; Kumar, R.; Lo, G.Q.;

Balasubramanian, N.; Kwong, D.-L., IEEE Electron Device Letters, Vol. 27, no. 5, pp. 383- 386, 2006

14



GAA, SON FinFETM IGFET

Trigate FET - -gate FET . -gate FET

Quadruple

gate FET

Cylindrical

FETM ulti-bridge/stacked

nanowire FET

Do

ub

le g

ate

Tri

ple

g

ate

Su

rro

un

din

g g

ate

Multi-Gate MOSFET Structures

tsi

WIMEC

INTEL

TI

Freescale

LETIU. Singapore

Gat

e

Gat

e


Si

BOX Si

FOX

GateGate

Hard

Mask

A B

FOX

Si

FOX

C

FOX

Gate

Si

A: Inverted T channel FET;

B: Bulk FinFET;

C: Multi-channel Field Effect Transistor

Multi-Gate MOSFET Structures

15



si

zyx

dz

zyxd

dy

zyxd

dx

zyxd

0 ),,(),,(),,(),,(

2

2

2

2

2

2

*)/

(/

(/

Cdz

zyxdE

dy

zyxdE

dx

zyxdE zyx )((),,(),,(),,(

Source

Drain

x

yz

Ey

EyE

z

Ez

Ex

Ex

tsi

wsi

L

Electrostatic Control of Channel

Poisson:

Or, in other words:


,1 ) si

oxtsi tox

,2 ) si

2 oxtsi tox

oxsi

ox

si tt

,4

4 1

ox

siox

si

ox

sisi tt

tt

,216

21ln2 22 (33

4

5667

8(

)

Surrounding gate

(circular channel cross

section)

Quadruple gate

(square channel cross

section)

Double gate

Single gate

Source

Drain

x

yz

Ey

EyE

z

Ez

Ex

Ex

tsi

wsi

L

Natural Length, ,

The concept of Natural Length is very similar to that of Electrostatic Integrity

16



oxsisi

ox

tt

nControlticElectrosta

1

9

n = number of gates; tsi is assumed equal to Wsi

n = 3 for trigate and n : for -gate (!!!)

Electrostatic Control of Channel

A decrease of tsi can be substituted for a

decrease of tox or an increase of !ox

Source

Drain

x

yz

Ey

EyE

z

Ez

Ex

Ex

tsi

wsi

L


1. K.K. Young: Analysis of conduction in fully depleted SOI MOSFETs. IEEE Transactions on

Electron Devices 36-3, 504 (1989)

2. R.H. Yan, A. Ourmazd, and K.F. Lee: Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE

Transactions on Electron Devices 39-7, 1704 (1992)

3. C.P. Auth, J.D. Plummer: Scaling theory for cylindrical, fully-depleted, surrounding-gate

MOSFET's. IEEE Electron Device Letters 18-2, 74 (1997)

4. Chi-Woo Lee, Se-Re-Na Yun, Chong-Gun Yu, Jong-Tae Park, J.P. Colinge: Device design

guidelines for nano-scale MuGFETs. Solid-State Electronics 51-3, 505 (2007)

5. Q. Chen, E.M. Harrell II, J.D. Meindl: A physical short-channel threshold voltage model for

undoped symmetric double-gate MOSFETs. IEEE Transactions on Electron Devices 50-7, 1631

(2003)

Natural Length: references

17



Nanowires Hold Promise for Future CMOS

David Lammers, News Editor -- Semiconductor International, 10/8/2007

A roadmap from Japan's technical community sees silicon

nanowires extending the reach of multi-gate devices.

Multiple nanowires in multi-gate devices could increase the

drive current of future CMOS devices.


A BW

si

Pitch

GateGate

W

L L

A: Single-gate, planar MOSFET layout; B: Multi-fin multigate FET layout

Current Drive

18



PitchWsi

Gate

Fin tsi

Fin Fin Fin

BOXA

5 0 1 0 0 1 5 0 2 0 00

0 .5

1

1 .5

2

2 .5

3

P itch (n m )

Cu

rre

nt I D

/ID

o

ts i

= 50 n m

T riga te , (10 0 ) s id ew a lls

T riga te , (1 10 ) s ide w a lls

F in F E T , (11 0 ) s idew a lls

F inF E T , (1 00 ) s id ew a lls

5 0 1 0 0 1 5 0 2 0 00

0 .5

1

1 .5

2

2 .5

3

P itch (nm )

ts i

= 1 00 n m

T rig a te , (1 00 ) s ide w a lls

T rig a te

(1 10 ) s ide w a lls

F in F E T , (11 0 ) s idew a lls

F in F E T

(10 0 ) s ide w a llsCu

rre

nt I D

/ID

o

Current Drive

P

tWII

top

sisidesitop

DoD "

""# 2$%

Normalized current drive of a 50nm-thick FinFET and triple-gate MOSFET vs. pitch. Wsi=pitch/2; The (100)-interface electron

mobility is 300 cm2/Vs and the (110)-interface mobility is 150 cm2/Vs. Left: tsi=50nm; Right: tsi=100nm


Wsi=5nm

tsi=15nm

tox

=2nm

Na=5x1015cm -3

VG

=VTH

+0.7V

BOX

Wsi=t

si=5nm

tox

=2nm

Na=5x1015cm -3

VG

=VTH

+0.7V

BOX

Hard

Mask

Ele

ctr

on c

once

ntr

ation

Ele

ctr

on c

on

cen

tration

Wsi=t

si=5nm

tox

=2nm

Na=5x1015cm -3

VG

=VTH

+0.7V

Ele

ctr

on

co

ncentr

ation

BOX

Ele

ctr

on c

on

ce

ntr

ation

Hard

Mask

Ele

ctr

on c

oncentr

atio

n

Ele

ctr

on c

oncentr

ation

Wsi=t

si=5nm

tox

=2nm

Na=5x1015cm -3

VG

=VTH

Wsi=t

si=5nm

tox

=2nm

Na=5x1015cm -3

VG

=VTH

Wsi=5nm

tsi=15nm

tox

=2nm

Na=5x1015cm -3

VG

=VTH

BOXA B

C D

E F

Electron concentration profile

in a FinFET (A,B), a trigate

FET (C,D) and a gate-all-

around device (E,F) at

threshold (A,C,E) and above

threshold (B,D,F). The

vertical scale (electron

concentration) is different for

each plot.

Volume Inversion

19



0

tsi = 5nm

Depth in silicon

Ele

ctr

on c

oncen

tration

5 10 15 20

10nm15nm

20nm

Electron concentration profile in double-gate

MOSFETs with different silicon film thickness.

Volume Inversion

Silicon film thickness (nm)

0 10 20 30 40 50

Mob

ility

Mobility vs. silicon film thickness in

a double-gate transistor.


0 2 4 6 8 10 12 14 16 18 200.44

0.46

0.48

0.5

0.52

0.54

0.56

2*

22

2 2

2ln

sisii

ox

tmqtnq

TkC

q

kT &$''(

)**+

,

''(

)**+

,

sii

ox

tnq

TkC

q

kT2

2ln

Thre

sh

old

vo

lta

ge

(V

)

Silicon film thickness (nm)

0%-MS

nmtox 2.1%

Threshold Voltage

T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, S. Deleonibus: Multiple gate

devices: advantages and challenges. Microelectronic Engineering 80, 378 (2005)

20



-0.1 0 0.1 0.2 0.3 0.4 0.5 0.610

-12

10-11

10-10

10-9

10-8

10-7

10-6

SchrodingerPoisson

Dra

in c

urr

ent

(A)

Gate voltage (V)

W = tsi = 20 nm

10 nm

5 nm

3 nm

2 nm

.. P

P+S

Drain current vs. gate voltage in trigate MOSFETs with different cross sections. Devices are simulated using either

Poisson's equation only (P) or a Poisson+Schrödinger solver (P+S). VDS = 50 mV, tox = 2 nm, Na = 5x1017 cm-3.


Electron concentration (Poisson) Electron concentration (Poisson+Schrödinger )

Wsi

tsi

Wsi=tsi=20 nm / -MS=0V / VG= 0.0V / VG2=0V / Na=5x1017 cm-3

21



Wsi=tsi=20 nm / -MS=0V / VG= 1.5V / VG2=0V / Na=5x1017 cm-3


Wsi

tsi



Wsi=tsi= 5 nm / -MS=0V / VG=0.0V / VG2=0V / Na=5x1017 cm-3

Wsi

tsi

22




Wsi=tsi= 5 nm / -MS=0V / VG=1.5V / VG2=0V / Na=5x1017 cm-3

Wsi

tsi


3D Simulation: Quantum

Section: 5 nm x 5 nm, VG>VTH

23



0 1 2 3 4 5 6

x 1021

-0.76

-0.74

-0.72

-0.7

-0.68

-0.66

-0.64

-0.62

-0.6

1D3D

0 0.5 1 1.5 2 2.5 3 3.5 4

x 1021

-0.76

-0.74

-0.72

-0.7

-0.68

-0.66

-0.64

-0.62

-0.6

1D3D

c

Density of sates vs. energy above Eco for a 1D system (A) and a 2D system (B)

1D/2D Density of States


0 1 2 3 4 5

x 1020

-0.56

-0.5598

-0.5596

-0.5594

-0.5592

-0.559

-0.5588

-0.5586

-0.5584

-0.5582

-0.558

En

erg

y a

bove E

co (e

V)

Density of states (cm-3 eV-1)

150 "eV

Silicon

Fin

Polysilicon Gate

Buried Oxide

20 nm

tsi

W

0 0.1 0.2 0.30

0.5

1

1.5

2

2.5

3

3.5

4x 10

-7

Curr

ent

(A

)

Gate Voltage (V)

DT=5K, V

S=50mV

DT=150K, V

S=0.2mV

T=28K, VDS

=0.2mV

T=8K, VDS

=0.2mV

T=4.4K, VDS

=0.2mV

(x 0.004)

Quantum effect: Inter-subband scattering

At low temperature

24



56.5 nm

11.1 nm

1.7 nm

5.7 nm

4.2 nm

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8-5

0

5

10

15

20x 10

-8

VDS

=0.1mV

VDS

=0.2mV

VDS

=0.4mV

VDS

=0.5mV

VDS

=1.0mV

VDS

=5.0mV

Gate voltage (V)

Dra

in c

ondu

cta

nce

(S

)

0 2 4 6 8 10

x 1020

-0.775

-0.77

-0.765

-0.76

-0.755

-0.75

1 meV

5 meV

Density of states (cm-3 eV-1)

Energ

y a

bove

EC

o (e

V)

At room temperature !

Quantum effect: Inter-subband scattering


CONTENT:

•The SOI MOSFET: From Single Gate to

Multigate

•Multigate MOSFET Technology

•BSIM-CMG: A Compact Model for Multi-

Gate Transistors

•Physics of the Multigate MOS System

•Mobility in Multigate MOSFETs

•Radiation Effects in Advanced Single- and

Multi-Gate SOI MOSFETs

•Multi-Gate MOSFET Circuit Design.

25

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