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Jay Kim nepes Corporation, System Packaging Division October 13-15, 2015 Slide 2 1. Introduction 2. Fan-out technology 3. System In Packaging Solution 4. Scaled UP Fan Out Packaging 5. Summary Slide 3 Past Features and functionality Power/ Performance Cost Present Time to Market Time to Revenue Higher levels of component integration Smaller form factor Energy efficiency and performance System level cost Security Efficient hardware design Software/firmware enabled Slide 4 Does not have to be universal solution for the ALL requiring ultra small & extremely low cost Solution to relax the limitation of WLP, FC PKG or W/B PKG in some aspects Simpler supply chain at single manufacturing location Integration capability of heterogeneous devices & components Possible eco-system with device owner & end user working for entire system solution Slide 5 Eliminating package substrate, Au wire & C4 bumps Reduced electrical parasitic Higher frequency response Small & thin Single chip, Multi chip & embedding component capability (w/4RDL) Proprietary feature of Embedded Ground Plane (Cu) JEDEC, Commercial & Industrial. Automotive level reliability Slide 6 Excellent RF isolation, controlled impedance, low insertion loss, low attenuation, good thermal dissipation and automotive reliability Small (6x6mm, 1 metal layer), Short transmission lines Can expose back of die for heatsink Embedded Ground Plane for ground and shielding Can embed an antenna structure Slide 7 Slide 8 0.8 ~ 1.0 x 1.0 mm 2 sized with < 300 um thick Optimized process & a feature for thin panel manufacturing Replaceable BGA or QFN but thinner & better Slide 9 Enabling die-face up for sensor application Stacking & device pre-mounting possible Slide 10 Slide 11 14mm x 17mm x 1.7mm (after PoP) 3~4 active devices (AP, PMIC, Flash, Wi-Fi) 90~110 discrete components 4 Metal layers PoP supportive enabling DDR as option Slide 12 RDL design rule in tied up with function, reliability Antenna & Inductor embedding possible with multi RDL Slide 13 FeaturesBenefits Majority of the components integrated inside Get to market ~25% faster development time and reduce design time Ultra-small form factor Gives >50% reduction over current discrete solutions Embedded software and firmware is available and fully optimized for the SCM Provides a reduction in validation effort Memory enabled and power management integrated Reduces design complexity of integrating and certifying DDR memory and power management into customer design Challenge In Eco system from product design, testing, MP solution, Soft/firm ware, supply chain Reduces customers supply chain complexity and Improves time to market Slide 14 Single IoT board with 8bit - processor + BLE + Wi-Fi Fan out SiP basis - Integrated all function into 1 chip (DotDuino - 100 % compatible SiP module with Arduino) Slide 15 New material development for large panel processing Very high through put & material utilization in build up process (Dielectric ~ RDL) A flexibility in panel size (die placement ~ mold) Slide 16 Fan Out WLP as high performance & small form factor solution in place Face up & stackable Fan Out Package (VF-FOP) introduced for sensor & memory application High Integrated SiP is ready for true production for customers looking for faster market in & development TAT Scaled up Fan Out Packaging is to implemented with extra effort in material & process development Slide 17 Thank you for attention ! nepes Corporation www.nepes.co.kr Jay Kim (jhkim@nepes.co.kr, +82-10-4056-9339)jhkim@nepes.co.kr