FOUR WEEKS SUMMER TRAINING REPORT

ON

VLSI ANALOG AND DIGITAL IMPLEMENTATION

Submitted by

JAIDEEP SINGH

Registration number:11310164

programme:BTECH ECE

section:1309

Under the guidance of

Rajkumar sir and ravishankar sir

(vlsi faculty members in department of ece lpu)

School of Electronics and Electrical Engineering

Lovely professional university,phagwara,Punjab

(17th june-14th july,2016)

Organisational overview:lovely professional university;phagwaraTraining was completed under the guidance of Ravishankar sir and Rajkumar sir in vlsi domain .

Technology Learnt

TYPES OF DOMAIN IN VLSI * Analog:Analog circuits deal with continuous time signals. You design analog circuit to generate, detect, measure, amplify, attenuate or filter a signal that resembles signals exist naturally (hence the name analog), such as a sound wave or a temperature curve.

• Analog circuit designer knows about semiconductor technology, semiconductor physics, semiconductor device physics, electrical circuit theory, control and feedback.

*digital:Digital circuits deal with discrete time quantities with only two values: 0 and 1. You design digital circuits to do mathematical analysis and logic processing based on Boolean Algebra.

Digital circuit designer knows about Boolean algebra, linear algebra, digital signal processing, synchronous and asynchronous system

Continued…

• For Analog design we use following tools-• (1) Virtuoso• (2) Assura

• For digital design we use following tools-• (1) Ncsim • (2) Encounter• (3) Vivado

VIRTUOSO

• Designed to help users create manufacturing-robust designs, the Cadence® Virtuoso® Analog Design Environment is the advanced design and simulation environment for the Virtuoso platform. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center designs better for yield improvement and advanced matching and sensitivity analyses.

Example (Invertor in 180nm tech.)

SYMBOL

Simulation…

Ckt design using cadence virtuoso

Parametric Analysis

ASSURA

Cadence Assura Physical Verification supports both interactive and batch operation modes with a single set of design rules. The tool is used to identify and correct the design rule errors. We can perform three types of analysis-(1)DRC(2)LVS(3)RCX

DRC RULES

• LAMDA RULE(λ) • MICRON RULE(μ)

Layout using assura (invertor)…

NCSim (Incisive)

• Incisive is a suite of tools from Cadence Design Systems related to the design and verification of ASICs, SoCs, and FPGAs. Incisive is commonly referred to by the name NCSim in reference to the core simulation engine. In the late 1990s, the tool suite was known as ldv (logic design and verification)

ENCOUNTER

• Use to perform RTL analysis.• RTL Checks for High Speed Designs.• Identifies Design Issues Quickly.• Generates three reports-(1)Area analysis report(2)Timing analysis report(3)Power analysis report

VIVADO

• It is is a software suite produced by Xilinx for synthesis and analysis of HDL designs, superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.

• As of 2015, Xilinx recommends Vivado Design Suite for new designs with Ultrascale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000.

Vedic multiplier• With the up-to-the-minute encroachment of VLSI technology the insist for

portable and embedded digital signal processing (DSP) systems has increased efficiently.

• Multipliers are key components of many high performance systems such are FIR filters, Microprocessors, Digital Signal Processors etc

• In order to perform multiplications,a large number of adders or components are used.The ancient system of mathematics named as Vedic mathematics was rediscovered from the Vedas.In contrast to conventional mathematics,Vedic mathematics is simpler and easy to understand.In 1884 Swami BharatiKrishna TirthajiMaharaj re-introduced the concept of ancient system of Vedic mathematics.The utterance 'Vedic' is consequential from the word 'Veda „which earnings the store-house of all knowledge.The Vedic mathematics includes sixteen-sutras or formulae and thirteen sub-sutras.

Urdhva Tiryagbhyam Sutra

Ex.1: Find the product 14 X 12The symbols are operated from right to left .Step i) :

             

Step ii) :

             

Step iii) :

               

Let us work another problem by placing the carried over digits under the first row and proceed.

Steps:

i) 4 X 6 = 24 : 2, the carried over digit is placed below the second digit.ii) (3 X 6) + (4 x 1) = 18 + 4 = 22 ; 2, the carried over digit is placed below third digit.iii) (2 X 6) + (3 X 1) + (4 X 3) = 12 + 3 + 12 = 27 ; 2, the carried over digit is placed below fourth digit.iv) (2 X 1) + ( 3 X 3) = 2 + 9 = 11; 1, the carried over digit is placed below fifth digit.v) ( 2 X 3 ) = 6.vi) Respective digits are added

Program(Verilog code)

RESULT:

Interface of vivado for fpga:

FPGA RESULT

Block R

AM

s

Block R

AM

s

ConfigurableLogicBlocks

I/OBlocks

What is an FPGA?

BlockRAMs

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VEDIC MULTIPLIER ADVANTAGES

• They are area efficient and are high speed multiplier

DISADVANTAGES OF VEDIC MULTIPLIER:-with the increase in complexity system complexity also increases.

Reference

• http://verilog-code.blogspot.in/2014/01/design-and-implementation-of-16-bit.html

• http://www.123mylist.com/2014/06/vlsi-implementation-of-vedic.html?m=1#!

THANK YOU