ISTFAM 2010

Conference Proceedings from the

36th International Symposiumfor Testing and Failure Analysis

November 14-18, 2010

Intercontinental Hotel Dallas

Dallas, Texas, USA

Sponsored by

Electronic Duvlca Failure Analysts SocietyAll AIMUi Socwity o!ASM ImerwIM*

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Published byASM International®

Materials Park, Ohio 44073-0002

Contents

IPFA 2010 Best Paper

Combining High-Resolution Pulsed TIVA and Nanoprobing Techniques to

Identify Drive Strength Issues in Mixed-Signal Circuits 1

V.K. Ravikumar1, M.Y. Ho1, R.R. Goruganthu2, S.L Phoa1, V. Narang1, and J.M. Chin1

(1) Advanced Micro Devices Singapore Pte Ltd., Singapore;

(2) Advanced Micro Devices, Inc., Austin IX, USA

Session 1: Emerging FA Techniques and Concepts

Laser Voltage Imaging: A New Perspective of Laser Voltage Probing 5

Yin S. Ng1, Ted Lundquist1, Dmitry Skvortsov1,

Joy Liao2, Steven Kasapi2, and Howard Marks2

(1) DCG Systems, Inc., Fremont, CA, USA;

(2) NVIDIA Corporation, Santa Clara, CA, USA

Two-Photon X-Variation Mapping Based on a

Diode-Pumped Femtosecond Laser 14

K.A. Serrels1, D.T. Reid1, T.R. Lundquist2, and P. Vedagarbha2(1) Heriot-Watt University, Edinburgh, UK;

(2) DCG Systems Inc, Fremont, CA, USA

Quantitative, Nanoscale Free-Carrier Concentration Mapping

Using Terahertz Nearfield Nanoscopy 20

J. Wittborn1, R. Weiland1, A.J. Huber2, F. Keilmann3, and R. Hillenbrand4

(1) Infineon Technologies AG, Munich, Germany;(2) Neaspec GmbH, Martinsried, Germany;

(3 )Max Planck Institut of Quantum Optics and Center for NanoScience, Garching, Germany;(4) CIC nanoGUNE Consolider, Donostia ~ San Sebastian, Spain

Laser-Thermal Imaging 27

R. Aaron Falk and Tram Pham

QFI, Tukwila, WA, USA

Mobile Diffractive Solid Immersion Lens Design for

Backside Laser Based Fault Localization 32

S.H. Goh1, J.Y. Cho1, Jeffrey Lam1, J.C.H. Phang2(1) Global Foundries Singapore, Singapore;

(2) National University of Singapore, Singapore

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Session 2: FA Process/Case Studies

Volume Electrical Failure Analysis for Product-Specific Yield Enhancement 38

Steven Kasapi1, Joy Liao1, Bruce Cory1, Izak Kapilevich2, Richard Fortune2,Yin Shyang Ng2, Cathy Kardach2, and Elaine Cheng2(1) NVIDIA, Santa Clara, CA, USA;

(2) DCG Systems, Fremont, CA, USA

Case Study in Fault Isolation of a Metal Short for Yield Enhancement 49

Sarven Ipek and David Grosjean

Analog Devices Inc., Wilmington MA, USA

Inter Layer Dielectric Defect Induced High Contact Resistance 54

Re-Long Chiu, Jason Higgins, Toby Kinder, Juha Tyni, Sharon Ying, and Jones ChungWaferTech LLC CAMAS, Washington, USA

Failure Analysis Methodology on Systematic Defect in

ADC_PLL Ring Pattern Due to Plasma De-Chuck Process 58

Ang Ghim Boon, Chen Changqing, Alfred Quah, Magdeliza, Indahwan Jony,Lee Mern Tat, David Zhu, and Neo Soh PingFailure Analysis Group, QRA, Global Foundries

Fault Isolation of Sub-Surface Leakage Defects UsingElectron Beam Induced Current Characterization in

Next-Generation Flash Memory Technology Development 62

Go Nagatani1, Kenneth Yu\ Amelia Del Rosario1, Max Sidorov1,Richard E. Stallcup II2, and Joel-Anthony Gray2(1) Spansion Inc., Sunnyvale, CA, USA;

(2) DCG Systems Inc., Dallas, TX, USA

A Case Study: Observation of Counter Doping of Gate Poly andIts Validation in High Density 90nm CMOS SRAM Bitcell 66

Yuk Tsang, Xiang-Dong Wang, Michael Mendicino, and Andrew BlankenshipFreescale Semiconductor Inc., Austin, TX, USA

Session 3: Packaging and Assembly Level FA I

Magnetic Microscopy for 3D Structures: Use of the Simulation Approachfor the Precise Localization of Deep Buried Weak Currents 71

Fulvio Infante 1,2, Rodolphe Gomes2, Philippe Perdu2, Fabien Battistella3,Sebastien Annereau3, and Dean Lewis4

(1) FAST, Toulouse, France;

(2) CNES, Toulouse, France;

(3) Thales IT, Toulouse, France;

(4) Universite Bordeaux, Talence, France

X

Advanced Sample Preparation Method for Lead Free Bump IMC and

Solder Grain Image Enhancement 79

Ming-Song Sheu, Yian-Liang Kuo, Jeng-Hun Lee, Yu-Ting Lin,Hui-Chen Chu, Tsung-Fu Tsai, and Chih-Horng ChangTaiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan

Extending Acoustic Microscopy for

Comprehensive Failure Analysis Applications 84

Sebastian Brand1, Matthias Petzold1, Peter Czurratis2, and Peter Hoffrogge2(1) Fraunhofer Institute for Mechanics of Materials, Halle, Germany;(2) PVA TePla Analytical Systems GmbH, Aalen, Germany

Session 4: Sample Preparation for Technological Analysis

Process Induced Defects in the Silicon Substrate:

Approaches for Successful Failure Analysis 92

J. G. van Hassel and Xiao-Mei ZhangNXP Semiconductors, Nijmegen, The Netherlands

X-Sectional Scanning Capacitance Microscopy (SCM) Applications on

Deep Submicron Devices at Specific Sites 98

Xiang-Dong Wang, Yuk Tsang, and Clifford Howard

Freescale Semiconductor Inc. Tempe, AZ, USA

High Volume and Fast Turnaround Automated Inline TEM

Sample Preparation for Manufacturing Process Monitoring 102

Hyoung H. Kang1, John F. King1, Oliver D. Patterson1, Steven B. Herschbein1,James P. Nadeau2, and Scott E. Fuller2

(1) IBM Microelectronics, Hopewell Junction, NY, USA;

(2) FEI Company, Hillsboro, OR, USA

Session 5: Defect Characterization and Metrology I

Backscattered Electron Imaging for Embedded Subtle Defects in

32nm Processes 108

Z.G. Song1, H.S. Song2, J. Yu3,and T. Su1

(1) IBM, Samsung Electronics Co., Singapore;

(2) IBM STG-MD, Hopewell Junction, NY, USA;

(3) Global Foundries, Singapore

Semi-Automated Full Wafer In-Line SRAM Failure Analysis byDual Beam Focused Ion Beam (FIB) 113

Steven B. Herschbein1, Hyoung H. Kang1, Harvey E. Berman1,Carmelo F. Scrudato1, Aaron D. Shore1, and Bing Dai2

(1) IBM Systems & Technology, Hopewell Junction, NY, USA;

(2) Stanford University, Stanford, CA, USA

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Simulation Studies of Fluorine-Induced Corrosion and Defects on

Microchip Al Bondpads in Wafer Fabrication 117

Hua Younan and Nistala Ramesh Rao

Globalfoundries Singapore Pte. Ltd., Singapore

Session 6: Sample Prep for Chip Access and Device Deprocessing

A Novel Wet Etch In-situ Decapsulation of Devices on Boards 122

Michael A. Gonzales and Joanna Kiljan

Qualcomm, Inc., San Diego, CA, USA

Low Temperature Plasma Decapsulation of Copper-Wire-Bonded and

Exposed Copper Metallization Devices 127

Kristopher D. Staller

Texas Instruments, Tucson, AZ, USA

Decapsulation of Copper Bonded Plastic Encapsulated Integrated Circuits

Utilizing Laser Ablation and Mixed Acid Chemistry 133

Jake E. Klein and Lucas CopelandTexas Instruments Inc., Tucson, AZ, USA

Session 7: Alternative Energy (Photovoltaics, Solid State Lighting, etc.)

Photoluminescence and EBIC for Process Control and

Failure Analysis in Si-Based Photovoltaics

Martin Kittler1, Tzanimir Arguirov1, Reiner Schmid1,Winfried Seifert1, and Teimuraz Mchedlidze2

(1) IHP, Frankfurt (Oder), Germany;

(2) Joint Lab IHP/BTU Cottbus, Cottbus, Germany

Quality Evaluation Techniques of Solar Cell Module

Daisuke Murahara, Wataru Shimizu, Hidehisa Kubota,Tamiko Oda, and Kazuhiro Yabe

Oki Engineering Co., Ltd., Tokyo, Japan

Combined Electron Beam Induced Current Imaging (EBIC) and

Focused Ion Beam (FIB) Techniques for

Thin Film Solar Cell Characterization 151

Frank Altmann1, Jan Schischka1, Vinh Van A/go2, Stacey Stone2,Laurens F. Tz. Kwakman3, and Ralf Lehmann4

(1) Fraunhofer Institute for Mechanics of Materials, Halle, Germany;

(2) FEI Company, Hillsboro, OR, USA;

(3) FEI France, SAS., Lyon, France;

(4) FEI Deutschland GmbH, Frankfurt Main, Germany

Activation Energy Analysis of Dark and Laser Illuminated l-V Characteristics of

Thin-Film Poly Silicon Solar Cells 158

M. Boostandoost, U. Kerst, and C. Boit

Berlin University of Technology, Berlin, Germany

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137

143

Session 8: Sample Prep for Chip Access and Device Deprocessing II

Characterization and Failure Analysis of 3D IntegratedSemiconductor Devices Novel Tools for Fault Isolation,

Target Preparation and High Resolution Material Analysis 163

Frank Altmann1, Matthias Petzold1, Christian Schmidt1, Roland Salzer1,Cathal Cassid/, Paul Tesch3, and Noel Smith3

(1) Fraunhofer Institute for Mechanics of Materials, Halle, Germany;

(2) austriamicrosystems AG, Unterpremstaetten, Austria;

(3) Oregon Physics, Hillsboro, OR, USA

A Novel Junction Profiling Methodology 171

Tomokazu Nakai

Micron Japan, Ltd., Hyogo, Japan

Improvement of Optical Resolution through

Chip Backside Using FIB Trenches 176

Arkadiusz Glowacki1, Clemens Helfmeier1, Uwe Kerst1,Christian Boit1, and Philippe Perdu2

(1) Berlin University of Technology, Berlin, Germany;(2) CNES, Toulouse, France

Copper to Aluminum Bonding: IMC Characterization throughNew Mechanical Sectioning Methods 181

Lucas Copeland1 and Mukul Saran2

(1) Texas Instruments, Tucson, AZ, USA;

(2) Texas Instruments, Dallas, TX, USA

Sample Preparation and Analysis on Full-Thickness Silicon Wafers for

Wafer-to-Wafer Bonding Process Development 186

Richard J. Young1, Alex Buxbaum1, Corey Senowitz1, C. Deeb2, and W.H. Teh3

(1) FEl Company, Hillsboro, OR, USA;

(2) International SEMATECH Manufacturing Initiative, Albany, NY, USA;

(3) SEMATECH, Albany, NY, USA

Session 9: Board and System Level FA

Application of Lock-in Thermography on PCB for

Fault Localization and Validation of Failure Mechanism Due to

External Discrete Component Variation 191

William Ng1, Kevin Weaver1, Zachary Gemmill1,Herve Deslandes2, and Rudolf Schlangen2(1) National Semiconductor, Santa Clara, CA, USA;

(2) DCG Systems, Fremont, CA, USA

System Level FA on Transmission Line Issues 196

Nicholas Konkol

Intel Corporation, Hillsboro, OR, USA

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Fault Localization of Power-Ground Short via Signal Injection and

Oscilloscope Technique 202

Binh NguyenIntel Corporation, Hillsboro, OR, USA

Session 10: Photon Based Techniques I

Product Debug: Speed Problem Related to Unexpected RC Delay 206

J.G. van Hassel and F. Zachariasse

NXP Semiconductors, Nijmegen, The Netherlands

Timing Characterization of a Tester Operated Integrated Circuit byContinuous and Pulsed Laser Stimulation 211

Tuba Kiyan1, Christof Brillert2, and Christian Boil3

(1) Yildiz Technical University, Istanbul, Turkey;

(2) Infineon Technologies AG, Munich, Germany;(3) Berlin University of Technology, Berlin, Germany

Dynamic Power Analysis under Laser Stimulation:

A New Dynamic Laser Simulation Approach 217

A. Deyine1, P. Perdu1, K. Sanchez1, J.C. Courrege1, and Dean Lewis2

(1) THALES & CNES, Toulouse, France

(2) University Bordeaux, Talence, France

Two-Photon Absorption Laser Assisted Device Alteration Using1340nm CW Laser: Critical Timing Fault Isolation & Localization for

32nm MPU and Beyond 224

Baohua Niu, Pat Pardy, Joe Davis, Mel Ortega, and Travis Eiles

Intel Corporation, Hillsboro, OR, USA

Session 11: Posters

Failure Analysis Power Cycling Tool - FAPCT 231

Yi Yun Chua

Intel Production, Malaysia

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis 233

Kuo Hsiung Chen, Wen Sheng Wu, Yu Hsiang Shu, and Jian Chan Lin

United Microelectronics Corporation, Tainan, Taiwan, ROC

Using Nano-Probing Technique to Clarify Nickel Silicide beyondProcess Window Causing Device Failure 236

Jian-Chang Lin and Wen-Sheng WuUnited Microelectronics Corporation, Tainan, Taiwan, ROC

Fault Isolation on High Resistance Failure of 45nm ET Via

Chains Using Combined Technique of SEM PVC and Nanoprobing 239

P.K. Tan, Z.H. Mai, Y.W. Goh, L. Zhu, S.L Toh, Q. Deng, R. He, H. Tan,H.L Li, Q.F. Wang, Y.Z. Ma, W.Y. Lee, G.R. Low, and Jeffrey Lam

Detecting Internal "ESD-Like" Damage on CMOS Gates 243

M. Gores1 and H. Dicken2

(1) Hi-Rel Laboratories, Inc, Spokane, WA, USA;

(2) DM Data, Inc, Scottsdale, AZ, USA

Design Rule of Microchip Al Bond Pad and Optimization of

Bonding Process in Wafer Fabrication 249

Hua Younan, Nistala Ramesh Rao, Ang Ghim Boon, and Chen ShutingGlobalFoundries Singapore Pte Ltd., Singapore

Backside Infrared Imaging Using Improved Refraction-Assisted

Illumination Methods 254

Terence Yeoh, Stephen LaLumondiere, Neil Ives, and Martin LeungThe Aerospace Corporation, El Segundo, CA, USA

The Novel Dopant Profile Inspection Methodology by FIB 257

Po Fu Chou and Li Ming Lu

United Microelectronics Corporation, Ltd., Taiwan, R.O.C.

Design Diagnosis with E-Beam Probing to Improve Reliability Issue

Due to Competitive Signal Error 261

T.C. Chuang, CM. Shen, L.F. Wen, S.C. Lin, CM. Huang, and Jon C. Lee

Taiwan Semiconductor Manufacture Company, Ltd., Tainan, Taiwan, R.O.C.

Application to Non Destructive Physical Analysis Method UsingX-ray CT Imaging 265

Akira Mizoguchi, Minoru Sugawara, Masahide Nakamura, and Koichiro Takeuchi

Mitsubishi Electric Corporation, Kamakura City, Kanagawa pref., Japan

Fundamental Study of Al Pad Grain Size Measurement and Its Effectiveness 271

Yaobin Zhao, Haibo Dai, Baolin Gao, Linfeng Wu, Sanan Liang,

Chorng Niou, and Qiang Guo

Semiconductor Manufacturing International (Beijing) Corp, Beijing, P.R. China

Session 12: MEMs, Discretes and Optoelectronic Device FA

Characterization of Green and Ultraviolet LEDs byLaser-Based FA Techniques 275

M.A. Miller, E.I. Cole Jr., and P. TangyunyongSandia National Laboratories, Albuquerque, NM, USA

Advanced Laser Preparation of Microsystems for Further FIB Processing 281

Juergen Walter, Stefan Martens, and Walter Mack

Infineon Technologies AG, Regensburg, Germany

Fast Turn-around Failure Analysis of Metal Interconnection UsingFIB and LA ICP-MS 285

Zixiao Pan1, Wei Wei1, and Fuhe Li2

(1) Exponent Failure Analysis Associates, Menlo Park, CA, USA;

(2) Air Liquide - Balazs NanoAnalysis, Fremont, CA, USA

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A Novel Non-Destructive Approach to Deprocess the Sealing Cap from

MEMS Device for Failure AnalysisHsien-Wen Liu, King-Ting Chiang, Tao-Chi Liu, Ming-Lun Chang, and Jandel Lin

Integrated Service Technology Inc., Hsin-chu, Taiwan, R.O.C.

290

A Novel Technique for Localization of Low Level Leakage in

Integrated Circuits

A. Chiang, H. Wu, H. Nguyen, W. Pratchayakun, and P. Le

Vishay Siliconix, Santa Clara, CA, USA

297

Session 13: Defect Characterization and Metrology - II

Energy-Dispersive X-ray Spectrometry Performance on

Multiple Transmission Electron Microscope Platforms 301

James Demarest1, Chris Deeb2, Thomas Murray3, and Hong-Ying Zhaf

(1) IBM, Albany, NY, USA;

(2) SEMATECH, Albany, NY, USA;

(3) CNSE SUNY Albany, Albany, NY, USA;

(4) Corner, Albany, NY, USA

Highly Resistive AIN Formation in TiN / AlCu / TiN Stack Evidenced byEELS TEM and XPS 304

B. Delahaye1, H. Fray1, J.P. Brun1, N. Guilbaud1, P. Tabary1, S. Lariviere1,D. Basso1, M. Modi2, and M. Idir2

(1) Altis Semiconductor, Corbeil-Essonnes, France;

(2) Synchrotron Soleil, Gif-Sur-Yvette, France

Scanning Capacitance Microscopy for Failure Analysis of SOI- Based

Advanced Microprocessors 309

Lim Soon Huat, Lwin Hnin-Ei, Vinod Narang, and J.M. Chin

Device Analysis Lab, Singapore

Wafer Level Atomic Force Probing 317

Terence Kane, Sweta Pendyala, and Michael P. TenneyIBM Systems and Technology Group, Hopewell Junction, NY, USA

Session 14: Test and Diagnostic, Test and Debug

Systematic Defect Identification through Layout Snippet ClusteringWing Chiu Tarn, Osei Poku and R.D. (Shawn) Blanton

Carnegie Mellon University, Pittsburgh, PA, USA

320

High Volume Scan FA for Yield Enhancement at the 90nm Node

Ryan Ross and Gil Garteiz

Freescale Semiconductor, Tempe AZ, USA

330

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Tester-Driven Dynamic Laser Stimulation for Hard Functional Failure 332

S.H. Goh1, Y.H. Chan1, F. Zheng1, H. Tan1, J.W. Ting1, Robin Chen1, Z.H. Mai1,

Jeffrey Lam1, LC. Hsia1, CM. Chua2, andJ.C.H. Phang2(1) Global Foundries Singapore, Singapore;(2) SEMICAPS Pte Ltd, Singapore

Leveraging the Power Grid for Localizing Trojans and Defects 338

Jim Plusquellic1 and Dhruva Acharyya2(1) University of New Mexico, NM, USA;

(2) Verigy Inc., Santa Clara, CA, USA

Session 15: Circuit Edit I

Success! > 90% Yield for 65nm/40nm Full-Thickness Backside Circuit Edit 348

David W. Niles and Ronald W. Kee

Avago Technologies, Fort Collins, CO, USA

Innovative Methodologies of Circuit Edit on

Wafer-Level Chip Scale Package (WLCSP) Devices 359

Shih-Ting Liu, Tao-Chi Liu, Ming-Lun Chang, and Jandel Lin

Integrated Service Technology Inc., Hsin-chu, Taiwan, R.O.C.

Session 16: Counterfeit Electronics—Risks and Mitigation

Counterfeit Parts Recognition and Detection for Failure Analysts 364

Katherine V. WhittingtonCalifornia Institute of Technology, Pasadena, CA, USA

Case Studies of Counterfeit Part Detection in Assembled Products 369

Daniel P. HartgerinkNational Aeronautics and Space Administration, Houston TX, USA

Session 17: Photon Based Techniques II

Differential and Lockin Imaging of Dynamic Photon Emission and

Applications in Failure Analysis 373

Zhongling Qian1, Christof Brillert1, Christian Burmer1, and Yoshiyuki Yokoyama2(1) Infineon Technologies AG, Munich, Germany;

(2) Hamamatsu Photonics Deutschland GmbH, Herrsching, Germany

Application of Lock-in Thermography for Backside Failure Localization

Using Solid Immersion Lenses 378

Christian Schmidt1, Christian Grode1, Frank Altmann1,Jurgen Schulz2, and Alexander Seibt2

(1) Fraunhofer Institute for Mechanics of Materials, Halle, Germany;

(2) Melexis GmbH, Erfurt, Germany

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Combining Time Resolved Emission and Analog Simulation for

Fault Localization 384

Christian Burner1, Fabian Hopsch2, and Wolfgang Vermeiren2

(1) Infineon Technologies, Munich, Germany;(2) Fraunhofer IIS/EAS Dresden, Germany

Developing a Chemistry-Assisted Focused Ion Beam Process for

'On-Demand' Solid Immersion Lenses in Silicon 389

P. Scholz1, U. Kerst1, C. Boit1, T. Kujawa2, and T. Lundquist2(1) Berlin University of Technology, Berlin, Germany;(2) DCG Systems, Fremont, CA, USA

Infrared and Visible—Near Infrared Electroluminescence Developments for

FA in AIGaN/GaN HEMTS on SiC 393

M. Bouya1'2, D. Carisetti1, J.C. Clement1, N. Malberf, N. Labaf, and P. Perdu3

(1) THALES Research and Technology, Palaiseau, France;

(2) University Bordeaux, Talence, France;

(3) CNES Laboratory, Toulouse, France

Session 18: Nanoprobing and Nano Scale Electronic Characterization

Characterizing Gate Disturb Embedded Flash Memory Cells byAtomic Force Probing 398

M. Hoffmann, C. Nowak, A. Haase, and S. Eckl

Infineon Technologies Dresden GmbH, Dresden, Germany

Identification of a Non-LDD Induced Vt Shift Failure Mechanism via

Nano-Probe Characterization 403

Randal Mulder1 and Yuk Tsang2(1) Silicon Laboratories, lnc.;Austin, TX, USA;

(2) Freescale Semiconductor, lnc.;Austin, TX, USA

Characterization of a Resistive Path to a Gate Node

Using Tunneling Current Measurements 409

Clifford Howard, Sam Subramanian, Kent Erington,Randall Mulder, Yuk Tsang, and John Bartlett

Freescale Semiconductor, Inc., Austin, TX, USA

Electron Beam Absorbed Current as a Means of LocatingMetal Defectivity on 45nm SOI Technology 413

K. Dickson, G. Lange, K. Erington and J. Ybarra

Freescale Semiconductor, Inc. Austin, TX, USA

Frequency Sensitive Soft Fails in SRAM Arrays 423Sweta Pendyala, Terence Kane, Michael Tenney, Richard Oldrey,Manuel Villalobos, and John SylvestriIBM Systems and Technology Group, Hopewell Junction, NY, USA

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Session 19: Circuit Edit II (Laser, FIB, etc.)

Pulsed Spot Milling and Deposition to Enable Next Generation

Circuit Edit Via Development 426

Dane Scott1, Ted Lundquist2, and Tahir Malik2

(1) Intel Corporation, Folsom, CA, USA;

(2) DCG Systems, Inc., Fremont, CA, USA

Novel Circuit Edit Solution for Bulk Copper Milling 431

Tahir Malik1, Rajesh Jain1, Ferdi Meijer2, and Tim Velthof

(1) DCG Systems, Fremont, CA, USA;

(2) MASER Engineering, Enschede, The Netherlands

Fast Mixed Field Material Removal Using New Dielectric Etch Solution 440

Vladimir V. Makarov1, Leo Krasnobayev1, and James Hahn2

(1) Tiza Lab, LLC, Milpitas, CA, USA;

(2) Altera Corp., San Jose, CA, USA

Session 20: Packaging and Assembly Level FA II

Root-Cause Investigations of Stitch Bond - Shearing by Means of

3D-X-ray Computer Tomography (XCT),Metallographic Polishing and FIB 444

Peter Jacob, Iwan Jerjen, and Giovanni Nicoletti

EMPA Swiss Federal Labs for Materials Testing and Research, Duebendorf, Switzerland

Methodology for Analysis of Schottky Diode Failures 449

Bhanu P. Sood1, Michael Pecht1, John Miker2, and Tom Wanek2

(1) University of Maryland, College Park, MD, USA;

(2) Emerson Network Power, Lorain, OH, USA

Resolving the Failure Analysis Challenges on Stacked Die Structure in

Lead Frame Chip Scale Package 457

Raymond G. Mendaros and Jon Carlo P. Salimbangon

Analog Devices Inc., Cavite, Philippines

Author Index 465

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