islamic azaduniversity of qazvin vlsi design automation
TRANSCRIPT
Islamic Azad University of Qazvin
VLSI Design Automation VLSI Design Automation AlgorithmsAlgorithms
Ali Jahanian
January, 2009
CAD_VLSI - Introduction Page 2 OF 28
Course Descriptionq VLSI-CAD
– Automating the layout generation of digital circuits.q Course will covers
– Basic algorithms and complexity theory– Integrated circuit (IC) Design flow– Computer Aided Design (CAD) tool development for Very Large Scale
Integration (VLSI)– Lots of programming! (Tutorials will be provided by me)
q Perquisites:– Basics of VLSI Design– Programming
q Course webpage:– http://www.qazviniu.ac.ir (Grades, news, slides, and …)– [email protected]
CAD_VLSI - Introduction Page 3 OF 28
References
q N. Sherwani, “Algorithms For VLSI Physical Design Automation”, Kluwer Academic Publishers, 3rd edition, 2002.
q Research papers (the required papers will be introduced during the course)
q Sung Kyu Lim, Practical problems in VLSI Physical Design Automation, Springer, 2008.
q M. Sarrafzadeh and C.K. Wong, “An Introduction to VLSI Physical Design”, McGraw Hill, 1996.
CAD_VLSI - Introduction Page 4 OF 28
Course Outline
q Lectures 1-4: Introduction and design cyclesq Lectures 5-8: Basic algorithmsq Lectures 9-13: Clustering / partitioningq Lectures 14-17: Placementq Lectures 18-25: Routingq Lectures 26-27: CAD for FPGAq Lectures 28-32: Emerging topics in physical design
CAD_VLSI - Introduction Page 5 OF 28
Course Evaluationq Homework: 30%
q Research and presentations: 20%– Research topic is selected by students and approved by me. – Subject is studied and reported clearly in a research technical report. – Research is concluded by presenting it in a formal presentation session. – Novelty, practicality, and well-defined documentation are the main metrics for
evaluation.
q Projects: 25%– Projects are performed by Atlas Evaluation Toolkit which is a simple Linux-based
environment for developing and testing the physical design CAD algorithms.
q Final exam: 40%
CAD_VLSI - Introduction Page 6 OF 28
My References for the Slidesq Kia Bazargan’s slides
– Dept. of ECE, Minnesota.
q Morteza Saheb Zamani’s slides– Dept. of Computer and IT, Amirkabir Univ.
q Kurt Keutzer’s slides– Dept. of EECS, UC-Berekeley.
q Majid Sarrafzadeh’s slides– Dept. of ECE, UCLA.
CAD_VLSI - Introduction Page 7 OF 28
VLSI CAD Societiesq ACM SIGDA
– Special Interest Group in Design Automation
q DATC of IEEE Computer Society– Design Automation Technical Committee
CAD_VLSI - Introduction Page 8 OF 28
VLSI CAD Conferencesq DAC
– Design Automation Conferenceq ICCAD
– Int’l Conference on Computer-Aided Design
q ISPD– Int’l Symposium of Physical Design
q ASP-DAC– Asia and South Pacific DAC
q DATE (EDAC)– Design Automation and Test in Europe
q ISCAS– Int’l Symposium on Circuits and
Systems
q ISVLSI– International Symposium on VLSI
q GLSVLSI– Great Lakes Symposium on VLSI
q DSD– Euro-Micro Conference on Digital
System Design
q ICCD– Int’l Conference on Computer Design
q APC-CAS– Asia-Pacific Conference on Circuits
and Systems
CAD_VLSI - Introduction Page 9 OF 28
VLSI CAD Journals
q IEEE TCAD– IEEE Transactions on CAD
q ACM TODAES– ACM Transactions on Design Automation of Electronic
Systemsq Integration, the VLSI Journalq IEEE Transactions on Circuits and Systemsq IEEE Transactions on VLSI Systemsq IEEE Transactions on Computersq Elsevier Micro-electronics Journal
CAD_VLSI - Introduction Page 10 OF 28
Web Sitesq Computer Science Papers
– http://citeseer.ist.psu.edu/– http://portal.acm.org/– http://ieeexplore.ieee.org/Xplore/
q GSRC Bookshelf– http://www.gigascale.org/bookshelf/
q DACCafe– http://www.dacafe.com/DACafe/homepage.html
q News group– http://www.google.com à groups à comp.lsi.cad
Shahid Beheshti UniversityDepartment of Electrical and Computer Engineering
Lecture 1: Introduction
Ali Jahanian
CAD_VLSI - Introduction Page 12 OF 28
IC Productsq Processors
– CPU, DSP, Controllersq Memory chips
– RAM, ROM, EEPROMq Analog
– Mobile communication,audio/video processing
q Programmable– PLA, FPGA
q Embedded systems– Used in cars, factories– Network cards
q System-on-chip (SoC)
CAD_VLSI - Introduction Page 13 OF 28
Semiconductor Industry Growth Rates
CAD_VLSI - Introduction Page 14 OF 28
IC Product Market Shares
Source: Electronic Business
CAD_VLSI - Introduction Page 15 OF 28
Growth in System SizeC
AG
R = C
ompound A
nnual Grow
th Rate
CAD_VLSI - Introduction Page 16 OF 28
Example: Intel Processor Sizes
Intel386TM DXProcessor
Intel486TM DXProcessor
Pentium® Processor
Pentium® Pro &Pentium® II Processors
1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µSilicon ProcessTechnology
CAD_VLSI - Introduction Page 17 OF 28
Moore’s Law
1
10
100
1K
10K
100K
1M
10M
Transistors
10x/6 years10x/6 years
8086
6800068020
8038680486
68040
80804004
Pentium ProPentium
PPC601
PPC603
MIPS R4000
Microprocessors
CAD_VLSI - Introduction Page 18 OF 28Fall 2006 EE 5301 - VLSI Design I-18
NRTS: Chip Frequencies
[©Keutzer]
Clock speed GHz
0
1
3
5
7
9
11
1997 1999 2001 2003 2006 2009 2012
On-chip, local clock, high performance
On-chip, global clock, high performance
CAD_VLSI - Introduction Page 19 OF 28
More Demand for EDAC
AE = C
omputer A
ided Engineering
CAD_VLSI - Introduction Page 20 OF 28
The Inverted Pyramid
Electronic Systems > $1.5 Trillion
Semiconductor > $400 B
CAD $6 B
CAD_VLSI - Introduction Page 21 OF 28
Increasing Device and Context Complexity
q Exponential increase in device complexity– Increasing with Moore's law (or faster)!
q More complex system contexts– System contexts in which devices are deployed
(e.g. cellular radio) are increasing in complexityq Require exponential increases in design
productivity
We have exponentially more transistors!We have exponentially more transistors!
Com
plexity
CAD_VLSI - Introduction Page 22 OF 28
VLSI Technology Generationsq Submicron ( FS < 1 µm) [After 1990]
q Deep submicron ( FS < 0.18 µm or 180nm) [After 1999]
q Nano-scale (FS < 100 nm) [After 2005]
q Feature size (FS) = Technology node = channel length of minimum transistor.– Mainly λ = FS/2
CAD_VLSI - Introduction Page 23 OF 28
Deep Submicron and Nano-scale Effects
q Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: – Cross-coupled capacitances– Signal integrity – Resistance – Inductance– Leakage power
Design of each transistor is getting more difficult! Design of each transistor is getting more difficult!
DSM
Effects
CAD_VLSI - Introduction Page 24 OF 28
Heterogeneity on Chip q Greater diversity of
on-chip elements– Processors – Software – Memory – Analog
More transistors doing different things!More transistors doing different things!
Heterogeneity
CAD_VLSI - Introduction Page 25 OF 28
Stronger Market Pressures
q Decreasing design windowq Less tolerance for design
revisions Time-to-market
Exponentially more complex, greater design risk, greater variety, and a smaller design window!
Exponentially more complex, greater design risk, greater variety, and a smaller design window!
CAD_VLSI - Introduction Page 26 OF 28
A Quadruple-Whammy
Time-to-market
Com
plexityD
SM Effects
Heterogeneity
CAD_VLSI - Introduction Page 27 OF 28
Productivitygap
How Are We Doing?
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr/Chip
Log
ic tr
ansi
stor
s per
chi
p(K
)
10
100
1,000
10,000
100,000
1,000,000
10,000,000
Logic Tr./Chip
1981
1985
1989
1993
1997
2001
2005
2009
58% / Yr. compoundcomplexity growth rate
21% / Yr. compoundproductivity growth rate
Just EDA can decrease the gap
between Productivity and
Complexity
CAD_VLSI - Introduction Page 28 OF 28
Hot Topics in VLSI-CADq EDA for 3-d architectures
– 3-D ASIC placement and routing– 3-D FPGA placement and routing– Thermally robust interconnects– 3-D std cell design
q CNT interconnects– CNT interconnects modeling– CNT-based routing– Using CNT in 3d
q Physical design of Multi-cores, NOCs, MPSOCsq Physical design of aerospace systems
– SEU tolerant design
q Leakage-aware placement and routingq Application-driven voltage island designq Parallel CAD algorithms for multi-core systems