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IPC-7091 Draft document for industry consensus only October 2016

IPC-7091 Design and Assembly Process Implementation of 3D Components Final Draft for Industry Review October 2016 Comment deadline: November 21, 2016 To send comments or request a comment form, contact [email protected]. To join the IPC-7091 ballot group, visit https://www.surveymonkey.com/r/6VSLZFW.

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IPC-7091 Table of Contents

1 SCOPE ........................................................................................................................ 9

1.1 Purpose ............................................................................................................. 9 1.2 Target Audience ................................................................................................ 9 1.3 Intent .................................................................................................................. 9

2 APPLICABLE DOCUMENTS .................................................................................... 11 2.1 IPC ................................................................................................................... 11 2.2 Joint Industry Standards .................................................................................. 11 2.3 JEDEC ............................................................................................................. 11 2.4 Government Electronics and Information Technology Association (GEIA) ....... 11

3 GENERAL DESCRIPTION ......................................................................................... 12 3.1 Terms and Definitions ...................................................................................... 12

3.1.2 Electronic Element .............................................................................. 12 3.1.3 Interposer ............................................................................................ 12 3.1.4 Substrate ............................................................................................ 12 3.1.5 Electronic Package ............................................................................. 12 3.1.6 Electronic Module ............................................................................... 12 3.1.7 Three-Dimensional (3D) Packaging .................................................... 12

3.2 Technology Overview ...................................................................................... 12 3.2.1 Die Stack Package .............................................................................. 13 3.2.2 Package Stack .................................................................................... 13 3.2.4 Interposer ............................................................................................ 14 3.2.5 Through-Silicon Via (TSV) .................................................................. 14 3.2.6 Through-Glass Via (TGV) ................................................................... 14 3.2.7 System on Chip (SoC) ........................................................................ 14 3.2.8 System in Package (SiP) .................................................................... 15 3.2.9 Wafer Level Packaging (WLP) ............................................................ 15 3.2.10 Fan-Out WLP .................................................................................... 16 3.2.11 Substrate .......................................................................................... 16 3.3.1 Two-Dimensional (2D) Package .......................................................... 17 3.3.2 Two-and-a-Half-Dimensional (2.5D) Package ..................................... 17 3.3.3 Three-Dimensional (3D) Package ....................................................... 18

3.4 Embedded (Placed) Technology ...................................................................... 18 4 DEVICE CONSIDERATIONS .................................................................................. 19

4.1 General Requirements ..................................................................................... 19 4.2 Device Preparation .......................................................................................... 19 4.2.1 Cleaning ....................................................................................................... 19

4.2.2 Baking ................................................................................................. 20 4.2.3 Changing termination material ............................................................ 20

4.3 Passive Component integration (organic base material) .................................. 23 4.3.1 Formed resistors ................................................................................. 23 4.3.2 Formed Capacitors .............................................................................. 23


4.3.3 Formed Inductors ................................................................................ 24 4.3.4 Discrete Inductors ............................................................................... 24

4.4 Passive Component Integration (Nonorganic Base Material) ........................... 24 4.4.1 Formed Resistors ................................................................................ 24 4.4.2 Formed Capacitors .............................................................................. 25 4.4.3 Formed Inductors ................................................................................ 26

4.5 Semiconductor Die Issues ............................................................................... 26 4.5.1 Surface Redistribution ......................................................................... 26

4.6 Post-Process Validations ................................................................................. 27 4.6.1 Solder on Pad (Flip-Chip) .................................................................... 27 4.6.1 Known Good Die (KGD) ...................................................................... 28

4.7 Package Assembly Variations .......................................................................... 28 4.7.1 Die Stack (Wire-Bond) ........................................................................ 28 4.7.2 PoP Technologies ............................................................................... 29 4.7.3 Through Mold Via (TMV) ..................................................................... 30 4.7.4 Through-Mold Interconnect (TMI) ........................................................ 30 4.7.5 High-Density PoP ................................................................................ 31 4.7.5.4 Direct-Bond Interconnect (DBI) ........................................................ 32 Figure 4-16 Direct Bond Interface ................................................................ 33 4.7.6 Folded Stack Packaging ..................................................................... 33 4.7.7 PoP Interposer (PoPi) ......................................................................... 33 4.7.8 Thin Small Outline Package (TSOP) Stacking .................................... 34 4.7.9 Die Stack (Cu-to-Cu TSV) ................................................................... 34 4.7.9.1 Cu/Sn/Cu Fusion Bond .................................................................... 35 4.7.10 3D Interposer/Substrate Packaging .................................................. 36

4.8 Cost Consideration .......................................................................................... 36 4.9 Component Handling ....................................................................................... 37

4.9.2 Component Storage ............................................................................ 38 4.10 Thermal Management of 3D Components ..................................................... 38

4.10.1 Thermal Conduction/Convection ....................................................... 38 4.10.2 Thermal Transfer Mechanisms .......................................................... 39 4.10.4 High-Conductivity Mold Compounds ................................................. 41 4.10.5 Liquid Cooling ................................................................................... 42 4.10.6 Microfluidic Cooling ........................................................................... 43 4.10.7 Single-Phase Intertier Cooling .......................................................... 43 4.10.8 Two-Phase Intertier Cooling .............................................................. 43 4.10.9 Heat Pipes ........................................................................................ 44 4.10.10 Microchannel and Minichannel Cooling ........................................... 44 4.10.11 Thermal Modeling ........................................................................... 44

5 INTERPOSER/SUBSTRATE MATERIALS ................................................................ 45 5.1 Organic Interposer ........................................................................................... 45 5.2 Glass Interposer .............................................................................................. 45 5.3 Silicon Interposers ........................................................................................... 46 5.4 Ceramic Substrate/Interposer .......................................................................... 47


5.5 Conductor Characteristics (Copper Foil/Film) .................................................. 47 5.6 Conductor Characteristics (Metallization on Silicon) ........................................ 48 5.7 Conductor Characteristics (Metallization on Glass).......................................... 48 5.8 Conductor Characteristics (Metallization on Ceramic) ..................................... 48

6 PROCESS MATERIALS ............................................................................................ 49 6.1 Adhesives (Conductive and Nonconductive) .................................................... 49

6.1.1 Polymer Adhesives ............................................................................. 49 6.1.2 Dry Film Adhesive ............................................................................... 50 6.1.2.1 Die Attach Film Application .............................................................. 50

6.2 Solder Materials ............................................................................................... 51 7 PACKAGE-LEVEL STANDARDIZATION (JESD30) .................................................. 52

7.1 Package Outline Standards ............................................................................. 52 7.1.1 BGA .................................................................................................... 53 7.1.2 Fine-Pitch BGA (FBGA/FIBGA) ........................................................... 53 7.1.3 Package-on-Package (PoP) ................................................................ 55 7.1.4 TMV PoP ............................................................................................. 56 7.1.5 Wafer-Level BGA (WLBGA) ................................................................ 56 7.1.6 Stacked-Die Packaging Standards ...................................................... 57

8 PRINTED BOARD AND OTHER MOUNTING BASE OR BOARD STACKUP CONSIDERATIONS ............................................................................................... 58 8.1 Printed Board Technology ............................................................................... 58

8.1.1 Multilevel PCB Substrate .................................................................... 58 8.2 Mounting Base ................................................................................................. 59 8.3 Surface Finish for Placed Components ............................................................ 59

8.3.1 Electroless Nickel/Immersion Gold (ENIG) .......................................... 59 8.3.2 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) .. 60 8.3.3 Organic Solderability Preservative (OSP) ........................................... 60 8.3.4 Electrolytic Nickel/Electrolytic Gold (ENEG) ........................................ 60 8.3.5 Direct Immersion Gold (DIG) ............................................................... 60 8.3.6 Immersion Silver (IS)........................................................................... 60 8.3.7 Immersion Tin (IT) ............................................................................... 60 8.3.8 Copper (Chemical Deposition and Electroplate).................................. 60

8.4 Embedded-Component Technology ................................................................. 61 8.4.1 Formed Resistor Process .................................................................... 61 8.4.2 Capacitor Formation Process .............................................................. 62 8.4.3 Planar Capacitance ............................................................................. 63 8.4.3.1 Plane Layer Separation .................................................................... 63 8.4.4 Discrete Formed Capacitor Element ................................................... 63 8.4.5 Discrete Inductor Forming ................................................................ 64 8.4.6 Discrete Component Placement ....................................................... 64

8.5 Substrate and Interposer Materials (Package Level) ....................................... 67 8.5.1 Organic Circuit Structure ............................................................................... 67

8.5.2 Ceramic Circuit Structure .................................................................... 68 8.5.2.1 Metallization on Ceramic .................................................................. 68


8.5.3 Silicon Circuit Structure ....................................................................... 69 8.5.4 Glass Circuit Structure ........................................................................ 69

8.6 Dielectric Encapsulation ................................................................................... 69 8.6.1 Reinforced Prepreg ....................................................................................... 69 8.6.2 Unreinforced Resin ....................................................................................... 69 8.6.3 Resin-Coated Copper (RCC) ........................................................................ 69 8.7 Via Hole Preparation and Interconnectivity ...................................................... 69 8.7.1 TGV Connection to Board Copper ................................................................ 69 8.7.2 TGV Connection to Component Terminations ............................................... 70

8.7.3 Through Glass Via (TGV) Formation ................................................................... 70 8.7.4 Through-Silicon Via (TSV) Formation.................................................. 71 8.7.5 Via Filling ............................................................................................ 72 8.7.6 Alternative Via Plating on Silicon-Based Interposers .......................... 72 8.7.7 Conductor Forming on Silicon Interposers .......................................... 72 8.8 Buildup Layers and Via Hole Preparation (Redistribution Layer (RDL) on

Silicon and Glass) ........................................................................... 73 8.8.1 Silicon Interposer Metallization ........................................................... 73 8.8.2 Glass Interposer Metallization ............................................................. 73

9 DESIGN METHODOLOGY ........................................................................................ 73 9.1 Design Challenges ........................................................................................... 73 9.1 Total Circuit Consideration ............................................................................... 74

9.1.1 Internal (Embedded) Component Mounting ........................................ 74 9.1.1.1 Organic-Based Interposers .............................................................. 74 9.1.2.1 Solder Attachment............................................................................ 75 9.1.2.2 Conductive Polymer Attachment ...................................................... 75 9.1.3 Internal (Embedded) Component Mounting ........................................ 75 9.1.4 Circuit Interface Techniques ............................................................... 75 9.1.4.1 Organic-Based Interposer Design .................................................... 75 9.1.5 Internal Discrete Heat Sink ................................................................. 77 9.1.5.1 Organic-Based Interposer Design .................................................... 77

9.2 Layout Strategy ................................................................................................ 77 9.2.1 Product Functional Description ........................................................... 77 9.2.2 Engineering Actions ............................................................................ 77 9.2.3 Design Density Analysis ...................................................................... 78 9.2.4 Embedded Component Selection ........................................................ 78 9.2.4.1 Embedding Passive Components .................................................... 78 9.2.4.2 Embedding Active Components ....................................................... 79 9.2.5 Embedded-Component Circuit Interface ............................................. 79 9.3 Multilayer Substrate Construction and Geometries ................................ 80 9.3.2 Build-Up Circuit Layers on Silicon Base Structures ............................. 80

9.4 Component Attachment on Multilevel Assembly .............................................. 81 9.5 Circuit Routing Strategy (Organic and Nonorganic) ......................................... 81

9.5.1 Organic-Based Substrates .................................................................. 81 9.5.2 Silicon and Glass Interposers ............................................................. 82


9.5.3 Ceramic-Based Substrates and Interposers ........................................ 82 9.6 Documentation ................................................................................................. 82

9.6.1 Documentation Package ..................................................................... 82 9.6.2 Bill of Material (BOM) .......................................................................... 83 9.6.3 Software Tools and Data Transfer ...................................................... 83 9.6.4 General Rules for 3D Design .............................................................. 83

10 ASSEMBLY OF 3D PACKAGES ON PCBs ............................................................. 83 10.1 PoP Assembly Process .................................................................................. 83

10.1.1 PoP Fluxing Options ......................................................................... 84 10.1.2 PoP Fluxing Process ......................................................................... 84 10.1.2.1 Flux Coverage ................................................................................ 85 10.1.3 Flux Height Statistical Process Control (SPC) ................................... 85 10.1.4 Paste Dip .......................................................................................... 86 10.1.5 Prestacking Process ......................................................................... 87 10.1.6 TMV/TMI Assembly Considerations .................................................. 87 10.1.7 PoP Package Standoff Height (SOH) ................................................ 88 10.1.8 PoP Die Gap ..................................................................................... 90

10.2 3D Printing ..................................................................................................... 90 10.2.1 Jet Printing (see manufacturer) ......................................................... 90 10.2.2 Cavity Printing ................................................................................... 90 10.2.3 Cavity Keep-Out Zone ....................................................................... 91 10.3 Multilevel Placement ............................................................................ 92 10.4 Die Attachment .................................................................................... 92 10.4.1 Direct Chip Attachment (DCA) .......................................................... 92 10.4.2 Die-to-Substrate Reinforcement ........................................................ 93

10.5 Reflow Soldering Considerations for 3D Components ................................... 93 Figure 10-20 Soldering Material in PoP assembly ....................................... 93

10.6 3D Component Inspection Techniques .......................................................... 94 10.7 Board-Level Rework ...................................................................................... 95

10.7.1 Rework with Convection Reflow Soldering ........................................ 96 10.7.2 Rework With Infrared (IR) Reflow Soldering ...................................... 96 10.7.3 Rework With Laser Soldering ............................................................ 96 10.8 Underfill ................................................................................................ 97 10.8.1 Package-to-Board Reinforcement ..................................................... 97

10.9 Material Selection and Application ................................................................. 97 10.9.1 Capillary Flow Underfill (CUF) ........................................................... 98 10.9.2 No-Flow/Fluxing Underfill .................................................................. 98 10.9.3 Removable/Reworkable Underfill ...................................................... 98 10.9.4 Corner Bonding/Glue Bonding .......................................................... 98 10.9.5 Molded Underfill (MUF) ..................................................................... 99 10.9.6 Vacuum Underfill (VUF) .................................................................... 99 10.9.7 Wafer-Applied Underfill ..................................................................... 99 10.9.8 Underfill Inspection ......................................................................... 100 10.9.8.1 Causes of Voids ........................................................................... 100


10.9.8.2 Void Characteristics ..................................................................... 101 10.9.8.3 Test Strategies ............................................................................. 101 10.9.8.4 Flow-Pattern Voids ....................................................................... 101 10.9.8.5 Moisture Voids ............................................................................. 101 10.9.8.6 Effect of Contamination ................................................................ 102

11 TESTING AND PRODUCT VERIFICATION .......................................................... 102 11.1 Establishing Test Requirements .................................................................. 102 11.2 Assembly Process Qualification ................................................................... 102

11.2.1 Package-Level Stress Test ............................................................. 103 11.3 Substrate Test Coupons .............................................................................. 104

12 RELIABILITY ......................................................................................................... 105 12.1 Reliability Considerations ............................................................................. 105 12.2 Design for Reliability (DfR) Principles .......................................................... 106 12.3 End-Use Relationship .................................................................................. 106 12.4 Effects of Lead-Free Materials and Pure Tin Finishes on Reliability ............ 107 12.5 Validation, Qualification and Accelerated Aging Test for Reliability ............. 108 12.6 Environmental Testing ................................................................................. 109

13 DEFECT AND FAILURE ANALYSIS ...................................................................... 110 13.1 Nondestructive Failure Analysis (NFA) ........................................................ 110

13.1.1 Electrical Testing ............................................................................. 111 13.1.1.1 Functional Testing (FT) ................................................................ 111 13.1.1.2 Modeled Fault Testing (MFT) ....................................................... 111 13.1.1.3 IDDQ ............................................................................................ 111 13.1.1.4 Time-Domain Reflectometer (TDR) .............................................. 111

13.2 Internal Nondestructive Inspection ............................................................... 111 13.2.1 Acoustic Microscopy (AM) ............................................................... 111 Figure 13-1 Acoustical Microscopy (AM) Can Identify Voids, Delamination

and Cracks .................................................................................... 112 13.3.2 X-Ray Imaging ................................................................................ 112 13.3.2.1 Example X-Ray Image ................................................................. 112 13.3.3 Infrared (IR) .................................................................................... 113 13.3.3.1 IR Thermography (IRT)/Thermal Imaging..................................... 113 13.3.3.2 Infrared (IR) Microscopy ............................................................... 113 13.3.4 Magnetic Current Imaging (MCI) ..................................................... 114 13.3.5 Internal Optical Inspection ............................................................... 114 13.3.6 Electrical Probing- Nanoprobing ...................................................... 114 13.3.7 Chemical Analysis ........................................................................... 114 13.4 Destructive Failure Analysis (DFA) .................................................... 115 13.4.1 Cross-Sectioning (X-Sec) ................................................................ 115 13.4.2 Parallel Lapping (P-lap) ................................................................... 116 13.4.3 Decapsulation ................................................................................. 116

13.5 Optical Inspection ........................................................................................ 117 13.5.1 Optical Inspection (Postassembly) .................................................. 117 13.5.2 Confocal Laser Scanning Microscopy (CLSM/LSCM) ..................... 117


13.5.3 Examples of Observed External Inspection Defects ........................ 117 13.5.3.1 Head-on-Pillow Defect ................................................................. 117 13.5.3.2 Package-on-Package (PoP) Joining Defects ................................ 118 13.5.3.3 Nonwet Open Joint ....................................................................... 118 13.5.3.4 Bridging on PoP ........................................................................... 119 13.5.3.5 Solder Ball Oxidation .................................................................... 119 13.5.3.6 Insufficient Solder/Flux ................................................................. 120 13.5.3.7 Incomplete Solder Reflow ............................................................ 120 13.5.3.8 Missing Solder Ball ....................................................................... 121 13.5.3.9 Nonuniform or Missing Solder Deposition .................................... 121 13.5.3.10 Voids and Uneven Solder ........................................................... 121

14 Supplier selection and Qualification ....................................................................... 121 14.1 Factory and Process Audits ......................................................................... 121 14.2 Site Visit Procedure ..................................................................................... 122 14.3 Design and Process Evaluation ................................................................... 122 14.4 Observations and Recommendations .......................................................... 122

15 GLOSSARY OF ACRONYMS ................................................................................ 123


IPC-7091, Design and Assembly Process Implementation of 3D Components

1 SCOPE This document describes the design and assembly challenges, and ways to address them, for implementing 3D component technology. Recognizing the effects of combining multiple uncased semiconductor die elements in a single package format can impact individual component characteristics and can dictate suitable assembly methodology. The information contained herein focuses on achieving optimum functionality, process assessment, end-product reliability and repair issues associated with 3D semiconductor package assembly and processing.

1.1 Purpose Performance-driven electronic systems continue to challenge companies in search of more innovative semiconductor package methodologies. The key market driver for semiconductor package technology is to provide greater functionality and improved performance without increasing package size. The package interposer is the key enabler. Although glass-reinforced epoxy-based materials and high-density copper interconnect capability will continue to have a primary role for array-configured packaging, there is a trend toward alternative dielectric platforms as well as toward combining multiple functions within the same die element. To address this movement, an increasing number of semiconductor die developed for advanced applications now require higher I/O with contact pitch variations that are significantly smaller than the mainstream semiconductor products previously in the market. For these applications companies are developing interposer technologies that can provide interconnect densities far superior to organic-based counterparts.

1.2 Target Audience The target audiences for this document are managers, design and process engineers, and operators and technicians who deal with:

• Implementing 3D semiconductor packaging • Interposer, substrate and printed board design • Board-level assembly, inspection and repair processes

1.3 Intent This document intends to provide useful and practical information to those who are designing, developing or using 3D-packaged semiconductor components or those who are considering 3D package implementation. The 3D semiconductor package may include multiple die elements, some homogeneous and some heterogeneous. The package may also include several discrete passive SMT devices, some of which are surface mounted and some which are integrated (embedded) within the components substrate structure.

1.4 Implementation Challenges The next generation of 3D assembly has many implementation challenges, since the technology is complex and requires process expertise that may require foundries, outsourced semiconductor assembly and test (OSAT) providers and original design manufacturers (ODM). There is no clear direction where 3D packages will be built, tested and assembled. The type of process to be used and the order of assembly and stacking is not defined and depends on the assembler’s expertise. Figure 1-1 illustrates the technological complexity of 3D assembly.


Figure 1-1 3D Technology Complexity

As the mobile electronics markets continue to see significant growth, there will be an increasing demand for product miniaturization and higher product performance expectation. Developers of personal communication and computing products, for example, have already adopted multi-core processors. Furthermore, these high-performance processors will require greater memory bandwidth. To meet these market trends, manufacturers are predicting faster process capability and anticipate reduced power requirements to extend battery life. Next-generation semiconductor package solutions also are projected to be physically robust. While materials for organic substrate-based applications will meet the majority of commercial applications, more severe operating environments may require a more robust (non-organic) base substrate material.

Industry may continue to rely on organic-based platforms for a majority of semiconductor packaging applications. When addressing miniaturization of excessively high I/O and through-silicon via (TSV) die stacking applications, 2.5D silicon and glass-based platforms will likely prevail. In addition, technology developers with proven intellectual property (IP) may choose to license core IP as a shared resource across multiple users, amortizing development costs.

The ability to extend core IP through reuse, or by leveraging IP across multiple platforms, offsets the full nonrecurring engineering (NRE) costs that companies would normally incur when introducing a new IP usage model. Amkor Technologies, for example, has indicated advanced 2.5D SiP architectures can support leading-edge system performance requirements while reducing time-to-market and lowering total cost-of-ownership (when compared to packaged system-on-chip (SoC) platforms). The company’s position is that the 2.5D TSV architecture represents a viable approach to single-package system design and allows benefits such as:

• Power and performance improvements enabling new applications • Smaller form factor • Silicon layer count reduction for reduced cost and cycle time • Employment of die utilizing the best technology node at the best price and

performance (keeping foundry capital expenditures down) • Die partitioning and optimization for memory, analog, performance, power

management, etc. • Higher effective die yields obtained through die recovery • Integration of memory technologies with clear downstream benefits for bandwidth

and power (serving as replacements to eDRAM/eFlash) • Accelerated time to market • Risk reduction in the manufacturing schedule

OSAT ODMFoundry

Wafer process

Package Assy

Board Assy

TSV

Wafer bumping

Package Bumping

Micro bumping

Interposer PoP Assy

Pre stacked

2.5D Assy

Pkg mold

Wire bond

Underfill

Corner GlueRework

System Test

Wafer test KGD WL PKG

Die attach


2 APPLICABLE DOCUMENTS 2.1 IPC IPC-T-50 Terms and Definitions for Printed Boards and Printed Board Assemblies

IPC-SM-817 General Requirements for Dielectric Surface Mounting Adhesives

IPC-SM-785 Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments IPC-3406 Guidelines for Electrically Conductive Surface Mount Adhesives IPC-3408 General Requirements for Anistropically Conductive Adhesive Films IPC-7092 Design and Assembly Process Implementation for Embedding Passive and Active Components IPC-7351 Generic Requirements for Surface Mount Design and Land Pattern Standard

IPC-9701 Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments

2.2 Joint Industry Standards J-STD-001 Requirements for Soldered Electrical and Electronic Assemblies

J-STD-030 Selection and Application of Board Level Underfill Materials

J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices

2.3 JEDEC JEDECPublication 95 Mechanical Outlines of Solid State and Related Products

JESD22-A102 Accelerated Moisture Resistance – Unbiased Autoclave

JESD22aA108 Temperature, Bias and Operating Life

JEP158 3D Chip Stack With Through-Silicon Vias (TASVs): Identifying, Evaluating and Understanding Reliability Interactions

2.4 Government Electronics and Information Technology Association (GEIA) GEIA-STD-0005-1, Performance Standard for Aerospace and High Performance Electronic Systems Containing Lead Free Solder GEIA-STD-0005-2, Standard for Mitigating the Effects of Tin Whiskers in Aerospace and Electronic Systems 2.4 IEC IEC/TS 62647-4 Process Management for Avionic Aerospace and Defense Electronic Systems Containing Lead-Free Solder – Part 4


3 GENERAL DESCRIPTION 3.1 Terms and Definitions In addition to the terms listed here, the reader is referred to IPC-T-50 for additional terms and definitions for printed boards and printed board assemblies.

3.1.1 Die* Separated piece(s) of a semiconductor wafer that constitutes a discrete semiconductor or integrated circuit (IC). They are normally uncased and leadless forms of an electronic component and may be active or passive.

*singular or plural

3.1.2 Electronic Element A bare die/wafer or discrete component (resistor, capacitor, inductor, transistor, diode, fuse, etc.) with metallized terminals or terminations ready for mounting. The element can be an IC or a discrete electrical, optical or microelectronic mechanical system (MEMS) element. Individual elements cannot be further reduced without destroying their stated function.

3.1.3 Interposer A material placed between two surfaces to provide electrical insulation, redistribution of electrical connections, mechanical strength and/or controlled mechanical and thermal separation between the two surfaces.

3.1.4 Substrate The insulating material upon which a conductive pattern may be formed. (The base material may be rigid or flexible. It may be a dielectric or insulated metal sheet.) For this document, the term substrate refers to an interconnect platform fabricated from organic dielectric materials (rigid, flexible or a combination of rigid and flexible materials). Sometimes referred to as package substrate.

3.1.5 Electronic Package An individual electronic element or elements in a container that protect the contents to ensure reliability and provide terminals to interconnect the container to an outer circuit. Package outline is generally standardized or meets guideline documents. A package may function as electronic, optoelectronic or MEMS, and it may include bioelectronic elements (e.g., sensors).

3.1.6 Electronic Module A functional block that contains individual electronic elements and/or electronic packages to be used in a next-level assembly. An individual module may include an application-specific function or multiple electronic functions (e.g., optoelectronic, mechanical or other elements). The module typically provides protection of its elements and packages to assure the required level of reliability.

3.1.7 Three-Dimensional (3D) Packaging Three-dimensional (3D) integration of heterogeneous elements, using traditional interconnection processes, to achieve vertically configured interconnections.

3.2 Technology Overview The electronics industry has experienced a semiconductor package technology renaissance. This


is due to the growing number of innovative 3D package assembly methodologies which enable continually maximizing product functionality without increasing product size.

Multiple-die packaging commonly utilizes a substrate and/or interposer as a base. By integrating multiple-die elements within a single-package outline, overall product functionality can be increased while the package size becomes smaller than its predecessors, improving performance and capability.

Assembly of semiconductor die onto an organic substrate or glass/silicon interposer is essentially the same as assembly for standard IC packaging formerly using lead frames, but substrate- or interposer-based IC packaging for 3D applications can adopt a wider range of materials and alternative assembly processes. 3.2.1 Die Stack Package When vertically stacking two or more semiconductors for wire-bond assembly, the die elements will ideally have a progressively smaller outline. This tiered configuration allows all die to be sequentially attached on top of one another in a single operation, leaving the edge of the die elements accessible for the subsequent wire-bond operation, typical of that shown in Figure 3-1.

This tiered die format will generally furnish the lowest overall multiple-die package profile.

There is also a potential for improving package performance due in part to the very short coupling between vertically configured semiconductor die. Because they generally utilize a common substrate or interposer the package typically exhibits lower resistance, lower inductance and lower overall power consumption.

Figure 3-1 Die Stack Package Assembly (Figure source: STATS ChipPACK)

3.2.2 Package Stack A package stack refers to vertically mounting one or more prepackaged and tested die elements. Memory semiconductor companies adopted this process to provide a simple solution for furnishing significantly higher-density configurations to keep pace with more advanced processors.

3.2.3 Package on Package (PoP) Package on package (PoP) technology consists of at least two microelectronic packages which are assembled in a vertical stack and also utilizes a fine-pitch ball grid array (BGA) to join the package sections. The lower package of the stack includes a pattern of metallized lands on its top surface, through which mechanical and electrical attachments are made with the upper package (illustrated in Figure 3-2). The ball pattern of the upper package is designed to facilitate the connection between the packages.


Figure 3-2 Mixed-Function PoP Example

3.2.4 Interposer Silicon and glass are the ideal interposer materials for flip-chip and system-in-package (SiP) applications in terms of coefficient of thermal expansion (CTE) to match the physical properties of the silicon-based semiconductors mounted on the interposer surface.

3.2.5 Through-Silicon Via (TSV) TSV technology is the key to successful implementation of silicon as an interposer base. The processes developed for drilling and plating very small vias in this extremely brittle medium have enabled the dramatic expansion of I/O density and increased product performance.

3.2.6 Through-Glass Via (TGV) TGV technology has enabled developers to take advantage of significantly lower base material cost (compared to silicon). TGV drilling and plating processes are very different from the TSV process; however, glass interposers are said to furnish far lower transmission loss than silicon-based interposers.

3.2.7 System on Chip (SoC) SoC technology is a package in which there are multiple functions implemented into one silicon die. It may include one or more processors, memory and related peripheral functions on a single silicon platform. The heterogeneous SoC may include logic, analog and passive elements mounted onto a ceramic, silicon or glass material as a base platform in a planar (two dimensional, 2D) format.

Figure 3-3 is an example of SoC consisting of a single large die containing multiple functions.


Figure 3-3 System on Chip (SoC) Example

One advantage of SoC is high electrical performance with low power consumption, since all functions are on one silicon die. The disadvantage is that it creates multiple functions on one die which is very complicated, costly and time consuming.

3.2.8 System in Package (SiP) SiP, also known as multichip module (MCM), is multiple die or chip scale packages (CSPs) mounted on a single package substrate. Developing a SiP with related but dissimilar functions within a single package outline enables greater PCB surface utilization and potentially can provide enhanced electrical performance.

A typical system application would combine logic, memory and analog functions in a vertically configured 3D package utilizing an organic base substrate for interconnection. One advantage of SiP is each die could use a different process technology, as appropriate, for the functionality needed. One package can also consist of old and new technologies.

Figure 3-4 shows a SiP package with four unique die connected together in one package substrate.

Figure 3-4 SiP Example 3.2.9 Wafer Level Packaging (WLP) Wafer level packaging (WLP) has evolved to further reduce the packaged die footprint. In this approach, the wafer coming out of the semiconductor fab is the starting point for package processing. Multiple methods have been developed to package the die by performing much of the processing on the wafer before it is singulated.

A common method begins by adding a redistribution layer to the active side of the wafer to bring the I/O pads to a uniform array format. Next, a dielectric layer is deposited and pads are opened

Memory portion

Logic portion(Low performance)

Logic portion(High performance)

Analog/RFPortion

Memory die

Logic die(Low performance)

Logic die(High performance)

Analog/RFdie


at the desired contact points. Solder paste or preformed solder balls are then deposited on the pads and then the wafer is reflowed. The back of the wafer can then be marked with a part number and/or logo. Finally, the wafer is singulated by sawing.

The resulting package is not only small, but it has minimal electrical parasitics and, potentially, low cost in high volume, especially after the nonrecurring expenditure (NRE) specific to each wafer has been absorbed (Figure 3-5).

Figure 3-5 WLP for High-Performance Memory Figure provided by Tessera.

3.2.10 Fan-Out WLP Fan-out WLP technology is used to redistribute the very fine-pitch I/O of a die element to a more process compatible contact pitch. The basic die element is prepared with contact features suitable for flip-chip attachment to an interposer base. The interposer performs the function of “fanning out” the I/O of the die element to a uniform array format more efficient for board or substrate mounting.

3.2.11 Substrate The material selected for component substrates can be either of the following:

• Ceramic • Organic, glass-reinforced resin system • Non-reinforced film

Bismaleimide-triazine (BT) laminate is one of the preferred substrate materials for array-configured semiconductor package applications. Polyimide is also used for component substrates. The material is composed of high-strength and high-temperature polymers, which are suitable for any electronic package application requiring high performance or when operating in hazardous environments.

3.3 Package Geometric Space As semiconductor die elements shrink in size companies work to increase package density and enhance functional performance. To support this effort a number of semiconductor package


assembly providers are expanding the role of the interposer to interconnect both heterogeneous logic functions and homogeneous memory within a single package outline.

3.3.1 Two-Dimensional (2D) Package A 2D package consists of one or more die mounted in a single plane. A 2D package could be any of the following:

• Standard BGA package with one die • SoC with one die and multiple-function silicon • SiP with a lot of silicon die

The die could use flip-chip, wire-bonded or any other die-attached technology. Figure 3-6 shows an example of a 2-D SiP with two flip-chip die.

Figure 3-6 Example of a 2D SiP

3.3.2 Two-and-a-Half-Dimensional (2.5D) Package A two-and-a-half-dimensional (2.5D) package consists of one or more die mounted on an intermediate interposer and then mounted onto the package substrate. The interposer could be silicon, glass, ceramic or organic furnished with through vias for connecting the die metallization layer to the package substrate metallization layer. Figure 3-7 shows a 2.5D SiP package in which an interposer with TSVs is placed between the SiP substrate and the two flip-chip die elements.

Figure 3-7 Example of a 2.5D SiP A 2.5D interposer serves as a high-density interconnect platform to accommodate multiple heterogeneous and/or homogeneous semiconductor packaging applications. The base material for the interposer is a silicon wafer commonly used in manufacturing semiconductor elements. Prior to metallization for circuit interconnect, small via holes are ablated through the silicon material. The advantage of using 2.5D technology is the ability to stack different silicon technologies on a single substrate. This simplifies the assembly process until 3D challenges can

PCB

Die #1Die #2

Package Substrate

PCB

Die #1Die #2

Package Substrate

Interposer


be resolved. Two-and-a-half-dimensional packaging also has time-to-market advantages since it requires less integration design time and less manufacturing time. 3.3.3 Three-Dimensional (3D) Package There are many approaches for 3D packaging, such as:

• Package-on-package • Stacked die with wire bond • Stacked die with wire bond and flip chip • Stacked die with TSV • Stacked die utilizing intermediate interposers

There are many challenges involved in 3D packaging that relate to manufacturing process complexities and high cost. The PCB example shown in Figure 3-8 has a PoP device on the left and a distinct 3D multiple-die package assembly on the right. The 3D package assembly represents a SiP having two intermediate interposer structures. The larger interposer accommodates four vertically stacked through-mold-via (TMV) packaged die as well as an assembly with two flip-chip die mounted onto a smaller intermediate interposer.

Figure 3-8 3D PoP and SiP Assemblies on a PCB 3.4 Embedded (Placed) Technology Embedding components within the organic substrate structure is not a new concept. Until recently, however, most embedded component applications adapted only passive elements. The early component-forming processes relied on resistive inks and films to enable embedding of resistor and capacitor elements. Although the forming methods remain viable, many companies choose to place new generations of very thin, small outline discrete passive components and semiconductor die elements within the layering structure.

Implementing embedded component technology will continue to be a viable solution for a broad segment of the electronics packaging industry, especially handheld and consumer sectors where very small size and low power consumption are key marketing factors.

Figure 3-9 shows an example of embedded uncased active and passive component elements.


Figure 3-9 BGA Package Substrate with Embedded Active and Passive Elements

High-performance applications can benefit also when related components are positioned in close proximity to one another. Close coupling of related components contributes to minimizing signal delay and cross-talk problems. Selection of components to be embedded within the package substrate, however, must be made early in the design process (see 8.4).

4 DEVICE CONSIDERATIONS Both passive and active components maybe incorporated into a package substrate. Most commercial passive elements are furnished with a terminal compatible for solder processing, while semiconductors require further preparation. Semiconductor elements have traditionally been configured for gold wire-bond termination. Copper wire-bond termination, however, has evolved into the mainstream for both single- and stacked-die package applications (see 4.7). Converting to copper wire requires additional plating operations (explained further in 5.7). Flip-chip mounting will require similar plating processes as well as surface redistribution of the wire-bond terminal sites to a more uniform array contact pattern (see 4.6.1). Many have found that by reducing the component population on the substrate surface, package-level assembly is less complex and smaller, often resulting in lower fabrication cost. Although size and cost reductions are significant attributes, the close coupling of key elements can also contribute to improving functional performance. Refer to 4.3 for more detail on passive component variations for embedding. 4.1 General Requirements Multiple-die package planning must establish interconnection priorities that include the number of data lines, estimated data speed and power dissipation method. The substrate or interposer developed will require optimization to ensure interconnect lengths are minimized. This optimized design will generally improve overall signal speed and enable significant reduction in power dissipation.

4.2 Device Preparation Before opening containers, place the containers on an ESD-protected workstation. The work surface of the table and the floor area are covered by a static dissipative work surface. Moreover, all the static dissipative surfaces and the workstation must be connected to a common ground point. In addition, an employee's connection must be added and connected to the common ground point. This connection must be used to connect a wrist strap. Handling individual components should be avoided. However, when necessary for test and/or product verification, direct physical contact must be avoided. Human hands contain oil, which can contaminate the contacts and can impact the integrity of the solder interface. Refer to J-STD-033 for detail regarding the handling, packing, shipping and use of moisture/reflow-sensitive surface mount devices 4.2.1 Cleaning When devices furnished to the production floor are in the sealed tray carriers from the supplier, there is generally no need to clean parts before use. When kitting personnel or operators in the assembly environment inadvertently handle semiconductor packages without gloves, they may contaminate parts with various elements that can affect the solder process. When physical contact with these devices occurs, a cleaning procedure should be implemented. There is a broad range of chemistries and bench-top cleaning systems designed for small-lot cleaning. The process may be as simple as a soak-and-rinse procedure or more aggressive using sonic technology. Ultrasonic units typical of that shown in Figure 4-1 are small enough to sit on a


table, shelf or workbench and be moved easily. They are simple in design, with single tanks ranging in size from half-gallon to 8 gallons and moderate frequency levels that are safe for even very delicate array configured components.

Figure 4-1 Benchtop Small-Batch Ultrasonic Cleaner 4.2.2 Baking Plastic-packaged semiconductor devices should be placed and soldered onto the board assembly within 48 hours at general factory conditions of 30 ºC/60 % RH. If these conditions can’t be met, baking of the device(s) is required before board mounting. When baking is required, devices should be baked for a minimum of 8 hours at 125 ºC. To avoid damage during handling, the components should be retained or returned to the partitioned carrier tray for baking. All JEDEC standard trays (see Figure 4-2) are made from ESD-safe materials and can be furnished with a temperature rating up to 180 °C.

Figure 4-2 JEDEC-Compliant Carrier Tray Source: R. H. Murphy 4.2.3 Changing termination material A majority of commercial array-configured components are furnished with a tin-rich, lead-free alloy ball contact in order to be compliant with Restriction of Hazardous Substances (RoHS) regulations. A number of electronic market segments remain exempt from lead-free restrictions, especially products that operate in harsh environments and/or have life-critical functionality. While these market segments are allowed to use solder containing lead alloy, it is increasingly difficult to procure commercial BGA components in non-ROHS compliant configurations. When the specific alloy furnished on the BGA component is not compatible with a particular application, it will require removal of the existing contact (deballing) and replacement (reballing) with the preferred alloy.


4.2.3.1 Deballing For low-volume applications, the original solder ball can be removed using solder wicking or a hot-air desoldering tool. The solder wick method can work well, but the technician performing the task must avoid scratching or lifting the pads on the component. As an alternative, hot-air desoldering systems specifically developed for BGA rework can be used. When a greater number of components require reballing; however, automated wave solder deballing system or a solder-dip process may prove more efficient. No matter the method used, the cleaner the pads, the better the result obtained with the reballing process. 4.2.3.2 Reballing The reballing process is significantly more complex. The components must first be prebaked to ensure that any moisture that may have been absorbed from the ambient atmosphere is eliminated. Any moisture retained within the BGA package can become gaseous during the reballing process, causing severe structural failure. BGA reballing equipment suppliers recommend a component bake-out for eight hours at 51 °C (~ 125 °F). At least two sources for preformed are available to provide the preferred alloy spheres that are already configured in their proper array. The preform arrays use either water-soluble paper or temporary polymer carrier to retain the tiny spheres in position during reflow soldering onto the BGA. A large number of arrays are available, and the cost is low for small quantities since there is minimal tooling cost. Both methods require additional component cleaning with water and baking to dry the BGA again before use. There are also a number of suppliers for bench-top rework and repair systems that enable efficient deballing and reballing processes, but operator skill will be critical. Fully automated BGA reballing systems are available as well, however, due to the cost of these systems, they will likely be justified only for very high volume or sustained use applications. 4.2.3.3 Outsourcing Solutions Because the process for efficiently changing a solder ball alloy may be beyond the capability for many companies, a broad range of solutions have emerged from the service sector:

1. The reballing process has been shown to be reliable, provided that strict process procedures are followed. The advantage of using a reballed BGA component is that the component is transparent to a tin-lead soldering process. The disadvantages, however, are the cost and time required to reball the component and the potential for package warpage when the component is exposed to excessive temperature. Additionally, package warping increases the potential for head-on-pillow solder process defects.

2. Reball processing for aeronautic applications should be managed using IEC/TS 62647-4. On the negative side, this process effectively eliminates component traceability and revokes any regular or extended warranty that is normally provided by the original manufacturer regarding component use and storage.

3. Use of a standard tin-lead reflow process for assembly of all components on the board except the lead-free BGA will require a two-stage process: • Solder paste is printed onto the PCB land patterns followed by placement of all

components except the lead-free BGAs. The assembly is then processed using a conventional tin-lead reflow solder process (210 °C to 220 °C peak temperature).

• Flux—not solder paste—is selectively applied at BGA sites, and lead-free BGAs are then placed and selectively soldered using standard lead-free process profile (240 °C to 245 °C peak). Selective soldering is completed using either hot air or a laser assisted process that selectively heats only the lead-free BGAs.


The key advantage of the two-stage assembly process is that the Integrity and reliability of both tin-lead and lead-free components remain intact since they experience only the profiles for which they are designed. The disadvantage of this method is processing will require additional resources, overall process lead-time may increase and the assembler will need a selective soldering capability (hot-air repair tool or selective laser soldering system) in house. 4.2.3.4 Mixed/Backward Compatibility Solder Processing Backward compatibility scenarios arise when component suppliers introduce lead-free components, but not all board assemblers that use these components have converted their board assembly lines to lead-free technology. Hence, the assembly will have a mix of tin-lead and lead-free components. Tin-lead solder paste materials are typically eutectic requiring a maximum profile temperature of ~ 220 °C to coalesce and complete the joining process. On the other hand, typical lead-free solder reflow requires a temperature range of 235 °C to 245 °C to ensure uniform alloy fusion, well above the 220 °C tin-lead solder process reflow profile limit. Some high-performance product design teams have conducted testing and worked with their component fabricators to develop acceptable “hot” reflow profiles that do not introduce component integrity concerns. Although component materials are generally robust enough to withstand the extended temperature spike, some component fabricators may void their component warranties if the assembly process temperature exceeds 220 °C. The advantage of using a “hot” profile is minimal process parameters changes and low cycle time impact. The disadvantages of using a “hot” profile is the time and costs associated with the additional due diligence reliability testing and laborious reflow profile generation necessary to demonstrate component/solder joint integrity acceptability. IPC recommendation is to use 228 °C to 232 °C as the “hot” profile. Figure 4-3 example ‘a’ illustrates a typical tin-lead eutectic solder joint with uniform microstructure, while Figure 4-3 example ‘b’ shows a lead-free solder joint with a mixed metallurgy microstructure exhibiting segregated regions of lead-free and tin-lead solder.

Figure 4-3 BGA Solder Joints: a) Tin-Lead; b) Mixed Metallurgy (Lead-Free Alloy in a Tin/Lead Process) The real disadvantage of the segregated “mixed alloy” microstructure is that the solder joint will be compromised and may require the use of an underfill material to physically reinforce the package-to-board solder joint interface. Utilize a “hot” reflow profile during tin-lead soldering process to harmonize the BGA solder joint microstructure and minimize solder joint microstructure segregation. 4.2.3.5 Underfill for Mixed-Alloy Soldering A methodology for reinforcing lead-free BGA components assembled using a tin-lead solder-based process is applying underfill. The application of an underfill material also reduces the impact of mismatch stresses (CTE) on the solder joints by directly coupling the BGA component


to the PCB. The advantages of using an underfill approach are the reduced costs and greater availability of standard lead-free configured BGA components. The disadvantages of using an underfill are the materials cost and time associated with dispensing and curing the material. Furthermore, if the underfill formulation is not reworkable, the PCBA becomes nonrepairable (refer to IPC-SM-817 and J-STD-030 for guidance). 4.3 Passive Component integration (organic base material) Organic substrate structures- The use of embedded passives can reduce assembly costs, enable a reduction in board area, and minimizes the cost of purchasing and handling significant numbers of discrete components. Users, however, must also address the potential for increased unit cost as well as decreases in throughput and process yield. The first decision to be made is whether or not to adopt an embedded component solution. Depending on the application, cost, performance, or some other metric may influence the decision.

Several factors must be considered:

• Value range of passive components selected for embedding (formed or placed) • Availability of discrete passive components suitable for embedding

4.3.1 Formed resistors Polymer thick-film (PTF) resistors can be printed directly onto the laminate surface requiring only conventional screen print processing to provide the resistor pattern. The paste-like PTF material developed for this process is available in resistance values that range between 1 ohm and 1 meg ohm per square. Etch formed resistors- Resistor elements can also be formed using copper foils coated with a thin film resistor material (Figure 4-4). The basic foils are sputter coated with a thin Nickel-Chromium (NiCr) or Nickel-Chromium-Aluminum-Silicon (NiCrAlSi) with a predetermined resistance value. The resistor elements are formed during a two-step chemical etch process and provide resistor elements with a tolerance range between +/- 8% and +/- 10%.

Figure 4-4 Formed Resistor Elements Further laser trimming can be used to modify the value and /or improve resistor tolerance (the process variations and methodologies for forming resistor elements are further defined in IPC-7092).

Discrete resistors- As an alternative to forming component parts, many companies are placing very thin discrete passive components within the multilayer circuit. A popular discrete resistor is furnished in a standard 01005 device outline (0.40mm x 0.20mm x 0.15mm actual size) is available in all standard values in tolerances as low as +/-1%.

4.3.2 Formed Capacitors Two techniques commonly adopted for embedded capacitor applications are forming and laminating.

• Forming is where a thick-film dielectric material is deposited or printed directly onto copper.

o Process variations


Deposited: stencil or screen-printed dielectric pattern Polymer thick film Ceramic thick film Ceramic filled polymer

• Lamination is where a film-like dielectric layer is placed between opposing copper circuit

layers. Capacitance value is achieved using materials of different dielectric constants and different dielectric thicknesses.

The planar capacitor simply sandwiches a dielectric material between two layers of copper foil. The most common commercially available capacitor technology is an organic laminate structure that relies on a thin glass reinforced epoxy composite with copper foil on both sides. Companies are also supplying a barium-titanate-filled polyimide as well as epoxy material that can provide a much higher capacitance density

Discrete (placed) capacitors- A growing number of companies are supplying small outline capacitors with a thickness of 0.15mm to 0.20mm for the 01005 size component and 0.20mm to 0.30mm for the 0201. The 01005 and 0201 type capacitors with a C0G dielectric, for example, are available in a value range between 5.0pf and 100pf. The X7R dielectric capacitors, on the other hand have a value range 68 pF to 470 pF for the 01005 type and 68 pF to 10,000 pF for the 0201 size component. A very thin (0.15mm) capacitor family, although available from some sources, will have a limited value range. 4.3.3 Formed Inductors PCB planar spiral inductors can be used as antennae or components for forming high frequency matched filters in a RFID system. The length of the spiral and the number of turns determines inductance. Spacing between turns will control the resonant frequency of the inductor. A wider spacing will typically reduce capacitance and raise the inductance frequency. The resistances and inductances of a formed spiral inductor can be calculated manually or by using a number of commercially available software tools

4.3.4 Discrete Inductors There are basically only two types of inductors that are suitable for embedding into the organic substrate; multilayer ceramic and thin-film multilayer. The multilayer ceramic products have a relatively small outline but their thickness may be too great. The thin-film inductor provides a small outline and a moderately thin profile that is likely more compatible for embedding.

4.4 Passive Component Integration (Nonorganic Base Material) The non-organic base material selected for mounting and interconnecting 2D and 3D components may be ceramic, silicon or glass. Although the interposers primary function is for interconnecting components on its surface, integrating passive component elements within the interconnects can contribute to improving performance and lowering power. The following will furnish an overview of some of the passive elements that could be considered for integration.

4.4.1 Formed Resistors Although polymer thick-film materials can be printed onto the silicon and glass interposer surface, however, thin-film resistor technology is the preferred solution for all applications requiring stability, low noise and uncompromised performance at high frequency. Although their appearance might be very similar, their properties and manufacturing processes are very different. Thin-film has a thickness in the order of 0.1 micrometer or smaller, while thick-film is around a thousand time thicker. The primary difference is the methodology for applying resistive film onto the substrate. The thin-film resistor is a metallic film that is vacuum deposited onto the substrates surface. Thick-film resistors are produced by printing and firing a paste-like formulation onto the substrates surface. The paste is a mixture of glass and metal oxides.

Thin-film materials can provide more precise values, has a better temperature coefficient and is more stable over time. The process for thin-film resistor forming is somewhat specialized. The resistive layer is sputtered (vacuum deposition) onto interposer surface. This creates a uniform

http://www.resistorguide.com/temperature-coefficient-of-resistance/


metallic film of approximately 0.1 micrometer thick. The resistive alloy is commonly a combination of Nickel and Chromium that are produced with different layer thicknesses to accommodate a range of resistance values. The layer is dense and uniform, which makes is suitable to trim the resistance value by a subtractive process. Resistor elements can be selectively trimmed using photo etching or by laser trimming. The process ablates narrow patterns into the resistive material to increase the resistive path and to fine-tune the resistance value.

Thin-film resistor process incorporates a high-stability, self-passivation and moisture-resistant “tantalum nitride” resistor element. An extremely thin layer (hundreds of Angstroms) of resistor material is deposited over the entire silicon wafer surface using a sputtering process. Usually a conductor layer is deposited on top of the resistor layer. Using a photo-lithographic process the substrate is patterned and the two layers are etched away independently to furnish both conductor and resistor patterns. The process offers a very wide range of resistance values (4.7 ohms to 1 Meg-ohms) with tolerances as low as 0.5 %. Material can be formulated to furnish values of 5 ohms/square to 250 ohms/square. Formed thin film devices provide low shunt capacitance and low-noise operation, ideal attributes for use in high performance microelectronic packaging.

4.4.2 Formed Capacitors Capacitors can be formed in the silicon substrate surface using a dry-etching process. A popular concept, referred to as ‘trench’ or ‘pillar’ capacitors has provided capacitance in the range of 80 nF/mm2 by using a thin coating (~16 nm) oxy-nitride dielectrics. The basic substrate topology is a 3D trench array with aspect ratio of around 20, as shown in Figure 4-5. This structure is finally capped with a metal electrode layer. After oxide deposition a second 8μm thick copper layer is applied to enable circuit interconnect.

Figure 4-5 Trench or Pillar Capacitor in Silicon Source: NXP Semiconductors Research This example represents only one solution for integrating capacitor functions within the interposer structure. Another type of capacitor for example, is known as a metal-insulator-semiconductor capacitor (MIS capacitor). Because silicon is the most commonly used semiconductor base and silicon dioxide is the most commonly used insulator material used in conjunction with silicon, these devices are most commonly referred to as metal-oxide-semiconductor capacitors (MOS capacitors). MOS capacitors can be used as sensors. For example, a temperature sensor can result from monitoring the shift in threshold, or flatband, voltage of the capacitor with changes in temperature. Furthermore, at a given temperature, the MOS capacitor can be used as a gas sensor by monitoring the shift in the threshold or flatband voltage as a function of the partial pressure of the gas.

Many of the processes developed for forming capacitor elements on a ceramic, silicon and glass


based platform are ‘proprietary’ and may require licensing for their use.

4.4.3 Formed Inductors Thin film inductors can be furnished on silicon and glass interposers. Both single-level and double-level suspended inductors can be fabricated and characterized in the multi-gigahertz frequency range. Three-dimensional suspended inductor structures were made possible using a sacrificial molding and electroplating technique. It is said that the multilevel suspended inductor structure can reduce the capacitive coupling with the silicon substrate effectively and achieve a large inductance-to-area ratio. It is found that the suspended double layer inductor was able to achieve an inductance greater than 8.0 nH.

Sputtering and electroplating are widely used to deposit the materials for the magnetic core in microinductors. Sputter deposited magnetic materials can generally have high resistivity, which results in low core eddy current loss and a relatively high factor of the micro-inductor. Several companies have demonstrated micro-inductors in dc–dc converters switching at frequencies between 1.2 and 5 MHz with achieved converter efficiencies mostly around 80%.

4.5 Semiconductor Die Issues Interactions with upstream and downstream process steps must be taken into account as well. This can extend to providing expertise that enables manufacturers to improve process results, adjusting processes to ease the integration of subsequent steps, or integrating processes. Challenges manufactures must resolve are:

• Difficulty integrating heterogeneous silicon processes. • Widely differing test requirements (logic, memory, analog, RF, etc.) • Sub-optimal device characteristics due to process integration • Low silicon yield due to large die size and complex process • Different operating voltages within the die • Complicated and lengthy design flow and complex IP issues • High development cost (masks, designers, IP, etc.) • Long development cycle time and mismatch with product life cycles

Redundancies may be needed within the package to meet reliability requirements because a single point of failure could result in a failure of the entire package. Developers of multiple die packaging must also solve key logistics issues:

• Accommodate incompatible die shrinks • Simplify management of multiple IC vendors • Enable package level test and burn-in • Allow the combining of high and low yield devices • Contribute to product quality and reliability • Maximize configuration flexibility

3D package innovations are proving to be far more predictable for a broad range of system-in-package applications. User companies have realized that many of these complex mixed-technology functions can be produced with higher yield and more economically if the semiconductors are individually fully tested before joining. 4.5.1 Surface Redistribution Redistribution is utilized when the existing bond pad locations on the die are spaced too close to accommodate efficient substrate circuit routing. I/O redistribution is a sequential process where additional conductive layers are added to the wafer’s active surface serially to provide a uniform contact array pattern (Figure 4-6).


Figure 4-6 Surface Redistribution

The uniform array better also facilitates die level testing and enables efficient circuit routing on or within the embedded component substrate. The process is generally performed while the die elements remain in the wafer format. The semiconductor surface is insulated from the wiring pattern and conductor paths are formed through a sequence of plating and imaging processes.

The following sequence represents the basic copper redistribution layer (RDL) process steps:

1. Apply metal adhesion layer over active side of wafer

2. Spin-coat photo resist over the wafer surface

3. Image and develop RDL circuit pattern

4. Electroplate Cu circuit and RDL contact site pattern

5. Remove photoresist

6. Chemically etch to remove remaining metal adhesion layer on wafer surface

7. Spin-coat photoimageable polymer over the wafer surface

8. Image and develop polymer coating to expose contact sites

9. Clean exposed Cu contact sites and apply process-compatible surface finish

4.6 Post-Process Validations 4.6.1 Solder on Pad (Flip-Chip) The semiconductor fabrication process typically furnishes the die with an aluminum bond pad for the traditional gold- or copper wire-bond interface process. When alternative interface methods are required, the semiconductor must be furnished with an alloy that will be compatible with the attachment material or interface method. Companies using solder, conductive polymer or direct-plated via interface will require an additional metallization process to provide copper termination capability at each bond site.

The solder bumping process is the most economical process. In this process, a precise volume of solder paste is deposited onto each contact site and heated to the liquidus stage to form a near-spherical contact profile. Solder bumping, however, is not the only option for flip-chip die attachment. The examples in Figure 4-7 are typical contact variations applied for flip-chip mounting.


Figure 4-7 Contact Variations for Flip-Chip Mounting 4.6.1 Known Good Die (KGD) The term known good die (KGD) was coined to designate bare die elements that are tested at various levels to demonstrate yield levels. An additional testing and screening procedure can be specified to obtain higher quality and reliability probabilities, sometimes referred to as “up-screening.” KGD processing requires the die be electrically certified during wafer-level probe testing or with a subsequent die-level test and screens to meet standard package part quality and reliability targets.

4.7 Package Assembly Variations Assembling semiconductor die onto a substrate or interposer is essentially the same process as standard I/C packaging in lead frames; however, substrate-based IC packaging for 3D applications can adopt a wider range of materials, and several alternative processes may be used in their assembly. 4.7.1 Die Stack (Wire-Bond) In an effort to improve component density, companies have experienced success in stacking multiple die elements directly onto a single substrate interposer using wire-bond processes. While most die elements are furnished with wire-bond sites at the edge of the die, SDRAM die elements have center-positioned wire-bond pad sites. This factor has complicated the die-stacking process, and because of the excessively long and unbalanced wire-bond interface, signal speed is significantly degraded. There are three array-type package configurations in wide use for stacking high-performance SDRAM:

• Opposing-face, top face-up, bottom face-down • Staggered stack RDL modified for edge bond • Face-up, RDL modified for edge bond (two- and four-die stack)

Stacking two- and four-memory die with perimeter-located bond pads has been fairly successful; however, a surface RDL must be added onto the wafer to reposition the wire-bond pads to the outer edge of the die. Additionally, these die elements will typically have the same physical outline.

When stacking die directly on top of one another, it will be necessary to add spacers between each die element to clear the wire-bond loop height. Examples of opposing-face and face-up memory package variations are compared in Figure 4-8.


Figure 4-8 Comparing Current Two-die and Quad-Die Package Solutions (Invensas) The overall package height can be a critical roadblock for a number of applications. Even though the die elements can be made very thin, the accumulated stack-up height generated by the added spacer and wire-bond loop profile on the top die may not be acceptable.

4.7.2 PoP Technologies Package stacking typically begins with the processor die element packaged onto the base substrate, and it will likely have significantly more I/O than any other closely related semiconductor functions. The processor die may be mounted face-up for wire-bond assembly or (after wafer-level redistribution and bumping) mounted face-down for direct solder attachment. The second-level package layer commonly furnishes memory functions (see Figure 3-5). Although the classic PoP is in wide use throughout the packaging industry, users have found that the joined package sections tend to warp during board-level assembly. Warping is attributed to significant solder defects (e.g., bridging, opens and dewetting).

The requirement for a larger solder ball contact and rather wide contact pitch on the upper package section is another issue. The larger solder ball is necessary to clear the mold cap on the lower package section.

To overcome the effects of warping during board-level assembly, the mold compound has been extended to the edge of the substrate. Vias in the mold are provided for access to the lower board contact features (see Figure 4-9). The vias, prefilled with solder, enable the use of much smaller solder balls on the upper package section and allow reduction of the spacing between contact sites.

Figure 4-9 Through-Mold Via PoP This technology is called through-mold via (TMV) or through-mold interconnect (TMI). The most common devices today have solder balls on the bottom package inside the molded via (see Figure 4-10). The memory ball is placed on the bottom package ball inside the molded via to create the connection.


Figure 4-10 Through-Mold Via Solder Balls

Analysts predict that although the package-on-package (PoP) configuration has a very secure position in the industry near-term, the newer generations of silicon products will be far more complex and require:

• Significantly higher pin-counts • Solutions for thermal management • Accommodation for much finer contact pitch variations

4.7.3 Through Mold Via (TMV) Adopting through-hole-via technology on the lower section of the PoP section enables significantly closer spacing of the package interface contacts (Figure 4-11). Via sites can be formed as part of the mold process or selectively ablated after molding. It is vital that the copper surfaces on the lands be free of any mold residue before filling with solder.

Figure 4-11 Lower PoP Section With Through-Mold Vias. Via holes are slightly tapered to provide a larger diameter on the top surface of the mold (Table 4-1 illustrates the typical differences between the bottom of the taper and top). Table 4-1 Through-Mold Via Examples

Position Average (µm) Minimum (µm) Maximum (µm) Standard Top 449 440 462 5.909 Bottom 313 309 321 3.465

(Table source: Amkor Technologies)

Depositing solder to fill the via sites includes solder jetting, printing or depositing several tiny solder spheres in each via followed by mass reflow processing to provide a solid solder fill. 4.7.4 Through-Mold Interconnect (TMI) The through mold interconnect process utilizes copper bond-wire on the lower section of the PoP package. The wire interconnect is arranged in a perimeter array pattern and encased in the mold compound encapsulating the semiconductor die mounted onto the organic substrate (Figure 4-12).


Figure 4-12 Lower PoP section with Through Mold Interconnect (Example source: Invensas) The TMI process can furnish an array configured contact pitch at or below 200µm. For example, a 14mm x 14mm package outline can be configured with more than four hundred (400) interconnects between the lower and upper package sections. This interconnect solution is very economical and lends itself to a wide variety of 3D PoP packaging applications. Because package assembly technologies utilize the existing semiconductor package infrastructure they do not require large capital investment and can be quickly implemented to provide increased PoP package I/O and performance.

4.7.5 High-Density PoP Current PoP interconnect technologies have attempted to improve package interface density with smaller solder balls and finer contact pitch. This is done by using laser-drilled and solder-filled vias in the mold cap or by adopting higher density PCB interposers.

The challenge is how to address the complexity of the next-generation multiple-die package assembly. To overcome the limiting aspects of the current method for PoP assembly, alternative very fine-pitch substrate interconnect solutions have evolved.

4.7.5.1 Copper Pillar Interconnect The developer of this copper pillar interconnect (CuPI) packaging technology states that when compared to solder ball-joined PoP, CuPI PoP provides a more stable package-to-package interface, produces a very reliable product and furnishes excellent electrical performance. Furthermore, the Cu pillar interface is not prone to fatigue by electromigration because current is distributed uniformly. The Cu pillar contacts are formed on the bottom surface of the upper package substrate using an additive plating process. The developer claims the Cu pillar contacts can be furnished with < 0.20 mm pitch (Figure 4-13).

Figure 4-13 CuPI PoP The joining of the Cu pillars on the upper package section to the adjacent Cu land features on the lower package section of the package employs a thermocompression reflow (TCR) technology. During the TCR process, underfill is first dispensed onto the top surface of the lower package substrate. The upper package section is placed and is then thermocompression bonded to the lower substrate.

4.7.5.2 Micro-Pillar


The micro-pillar (µPILR TM) PoP device has the advantage of an extended solder-wetting plane provided by the Cu pillar contacts, making it less susceptible to solder defects caused by minor substrate warping. One of the benefits of this high-density package substrate structure is the ability to reduce interconnect solder volume and tailor the solder shape to allow closer spacing of interconnects between package and board (see Figure 4-14).

Figure 4-14 High-Density μPILR Array Packaging (Invensas)

When comparing the µPILR contact profile to the more common solder ball connections, the contact geometry is significantly smaller in diameter and height, enabling a much lower finished package profile. The slightly tapered profile of the solid copper core contact is coated with an electroless nickel/immersion gold (ENIG) alloy which is compatible with either eutectic or lead-free soldering processes. 4.7.5.3 Bond Via Array (BVA TM) Bond via array (BVA) package technology employs a unique solid-copper wire-bond-based package stacking and interface technology that enables a substantial reduction in interface contact pitch between lower and upper PoP sections. The wire contacts are encased and physically reinforced within the mold compound that encapsulates the lower package semiconductor. The mold is designed so the wire contacts can extend from the top surface of the lower substrate to align with matching solder bump contact locations on the bottom surface of the upper package (see Figure 4-15).

Figure 4-15 BVA with Fine-Pitch Copper Wire Interconnect (Invensas)

The BVA wire-bonding process utilizes conventional wire-bond equipment enabling a contact pitch as small as 50 μm. The copper wire can extend to any length required for PoP interface.

4.7.5.4 Direct-Bond Interconnect (DBI) Direct-bond interconnect (DBI), as described by the developer, is a heterogeneous copper/silicon oxide to copper/silicon oxide joining process furnishing an in-situ electrical interface. The process can be utilized for joining silicon-based wafers, stacking individual die or mounting singulated or stacked-die elements to a silicon-based interposer structure. DBI is already proven for high-volume manufacturing of complementary metal-oxide semiconductor (CMOS) image sensors and


provides a scalable, low-cost solution for very high density and high I/O interconnect applications (see Figure 4-16).

Figure 4-16 Direct Bond Interface

DBI shown in Figure 4-16 is scalable to finer pitch and higher density sub-micron pitch semiconductors.

The bond strength of the Cu/SiO-to-Cu/SiO interface is 1 J/m2 at room temperature and will provide > 3 J/m2 after the 150 ºC annealing process. This is a solderless joining process and, because there is no air gap between surfaces, there is no requirement for underfill.

4.7.6 Folded Stack Packaging Flexible substrate materials enable folding of die elements into a very thin single fine-pitch square BGA (FBGA) package outline that is only slightly greater than the largest die of the set (Figure 4-17). Two-, three- and four-die assemblies have been developed, primarily for packaging memory elements; however, more complex mixed-component product variations have evolved for medical applications (e.g., hearing devices and implants).

Figure 4-17 Three-Memory Die on Flexible Circuit Substrate (Intel)

4.7.7 PoP Interposer (PoPi)


Pop interposer (PoPi) is a technology for maintaining an adequate gap, with small pitch, in 3D packages. This technology uses an ultra-thin picture frame interposer which is prestacked on the memory pads of the bottom package. The interposer elevates the memory pads to ensure during placement and reflow sufficient clearance is maintained between the bottom surface of the top memory package and the die of the bottom logic package. The memory package is placed on top of the interposer and then reflowed with the bottom package. Figure 4-18 shows an example of a PoPi device.

Figure 4-18 Package on Package Interposer (PoPi) 4.7.8 Thin Small Outline Package (TSOP) Stacking Leaded packages can also be stacked. The advantage of stacking thin small outline packages (TSOPs) is the use of low-cost components and quick integration time, using the industry mainstream DRAM packages. Figure 4-19 shows two 0.5-mm-pitch memory TSOPs stacked with an organic interposer. A plated-through hole (PTH) connects the memory packages.

Figure 4-19 Stacked TSOP Devices 4.7.9 Die Stack (Cu-to-Cu TSV) There are three primary wafer-to-wafer bonding methodologies for 3D TSV interconnects:

• Fusion (or molecular) bonding

• Metal-metal thermocompression bonding

• Adhesion bonding

Each of these methods has their advantages and disadvantages, but there is no standard process for TSV wafer preparation and joining.

There are also process control concerns associated with each method:

• Wafer-to-wafer alignment required for the fusion metal process +/- 150 nm • Metal oxide (if allowed to form) can prevent adequate bond formation • Excessive heat and bonding force can result in nonuniform bond strength between wafer

layers. For either Cu-to-Cu process variations, surface roughness control and oxidation are important to allow the opposing metal surfaces to come into intimate contact.


4.7.9.1 Cu/Sn/Cu Fusion Bond

Joining die elements in a 3D vertical format has been proven to alleviate a great deal of power dissipation concerns. This is because it enables significantly shorter interconnect between individual die elements.

Memory semiconductors are ideal for direct vertical joining because many of the I/O (pins) can be connected in parallel. Although a number of techniques have evolved for TSV and wafer-to-wafer joining, the solid-Cu-plated via methodology enables a copper-tin-copper fusion bond process to complete wafer interconnect.

The wafer joining process is considered low temperature because it requires no more than 400 ºC to complete the Cu-Sn-Cu fusion. This joining process illustrated in Figure 4-20 is a two-stage procedure that begins with the initial precise alignment and room-temperature prebonding of the wafers. Following prebonding, the wafer is exposed to an annealing process that includes high temperature and pressure. This joining process is significantly enhanced with the deposition of a thin layer of tin-alloy onto the exposed copper TSV features.

Figure 4-20 Fusion Bond Process Fusion wafer bonding is considered by some to be the most efficient method for metal-to-metal via joining. This joining process is a two-stage procedure that begins with the initial precise alignment and prebonding (die-to-interposer or die-to-wafer level platform). The system selected for performing this task must be able to maintain precise alignment accuracy. When the stacked wafers are heated to approximately 400 °C, the tin alloy will completely diffuse into the opposing copper TSV features to form a stable Cu-Sn- Cu (Cu3Sn) intermetallic at the TSV interface (Figure 4-21).

Figure 4-21 Cu/Cu3Sn/Cu Intermetallic Bonds


Due to the process complexities and semiconductor yield concerns associated with wafer-to-wafer joining, many companies opt to stack individual die elements. Although the TSV process is performed at the wafer level, the singulated die elements are easier to test. 4.7.9.2 Thermocompression Bonding Direct copper-to-copper is widely used for TSV bonding because the material has a high diffusion rate and has relatively soft ductile properties. Joining two copper planes requires thermal presses with a temperature range between 380 °C and 450 °C. The press must be able to apply a uniform force between 20 kN and 80 kN for 20 to 60 minutes to complete joining of the copper surfaces. The primary disadvantage of the direct Cu-Cu bonding process is the aggressive cleaning required to remove oxidization that rapidly forms on the unprotected Cu surface.

Gold can also be used for wafer-to-wafer joining, requiring temperatures (slightly below the Cu-Cu joining process) between 260 °C and 400 °C and an applied force above 40 kN for 20 to 45 minutes. The advantage over Cu-Cu joining is that Au does not form an oxide, eliminating the aggressive cleaning procedure needed prior to bonding Cu surfaces. The primary disadvantage is the fluctuating cost of gold alloy.

4.7.9.3 Adhesion Bonding Anisotropic conductive adhesives provide mechanical strength and electrical conductivity at TSV interconnection points. These materials can be spin or spray coated onto silicon wafers or applied as a film media and bonded at a moderate 250 °C.

The advantages of adhesion bonding are:

• Reduced space between wafers • Lower assembly process temperatures • Potential for reducing cost

The primary disadvantage of conductive adhesives is the need for an additional passivation (dielectric coating) requirement to insulate the backside of the wafer.

IPC-3406 details guidelines for electrically conductive surface mount adhesives. IPC-3408 provides performance requirements of conducting adhesives considering the chemistry of the adhesive and the material composition of the filler particles. Both standards furnish details for isotropic and anisotropic adhesives used for attaching flip chips prepared with noble alloy contacts. They cover performance requirements of the material when used in the assembly as well as long-term performance characteristics. 4.7.10 3D Interposer/Substrate Packaging This is a technology in which a silicon die element or multiple joined die elements are placed onto the silicon interposer with a conventional reflow solder process. The silicon or glass interposer interconnects the die elements on its upper surface and redistributes the conductors to a very fine-pitch contact array pattern on the lower surface. Solder bumps or pre-formed solder balls are furnished on the lower surface pattern for attachment to the organic based substrate. See also 8.5.

4.8 Cost Consideration Multiple-die 3D package technology using organic multilayer substrates will have a significant cost differential compared to single-die packages. Competitive pressures continually reduce costs to meet new targets; however, further costs may accrue if substrate layer counts increase. On the other hand, miniaturization and performance characteristics resulting from 3D package implementation is significant.

The following are some of the key reasons for higher substrate package cost:


• Higher-cost substrate (finer lines and spaces) • More robust substrate interposer materials • Addition of thermal enhancements • Electrical enhancements, shielding and impedance control • Very-fine-pitch semiconductor interface • High-temperature reflow requirements • Thinner materials to meet restricted profile heights

In general, it is difficult to create a standard pin count for 3D package designs because every variation has different requirements. Each package and die combination is unique; therefore, economies of scale that manufacturers can achieve with perimeter-leaded packages are not necessarily seen with the area array devices. Table 4-2 shows the history and expectations of the semiconductor industry as to what they expect to pay on a cost per pin relationship for the different technologies over the next several years. The shaded sections indicate a challenge and degree of difficulty in achieving the predicted goals.

Table 4-2 Semiconductor Cost History and Forecast

Year of Production 2012 2013 2014 2015 2016 2017 2020 2023 2026

Cost per Pin Minimum for Contract Assembly (Cents/Pin) Low-end, Low-cost package 0.21-0.40 0.20-0.38 0.20-0.36 0.20 -0.34 0.20-0.32 0.20-0.30 0.20-0.26 0.19-0.25 0.17-0.25 Mobile Device Package 0.38 0.3

7 0.36 0.3

5 0.34 0.33 0.3 0.27 0.2

4 Memory 0.24 0.23 0.22 0.21 0.21 0.21 0.2

1 0.2 0.19

Cost-performance 0.54–0.92 0.51–0.87 0.48–0.83 0.46–0.79 0.44–0.75 0.42–0.71 0.35–0.61 0.31–0.52 0.28–0.46 High-performance 1.4

1 1.34 1.27 1.21 1.15 1.09 0.94 0.8

1 0.73

Harsh 0.21–1.71 0.20–1.63 0.20–1.55 0.20–1.47 0.20–1.40 0.20–1.33 0.20–1.14 0.19–1.01 0.17–0.95 White - Solutions Exist Yellow - Solutions being pursued Red - No known solutions

4.9 Component Handling Semiconductor devices should always be stored in an enclosed antistatic shielding bag or conductive closed carrier when not being handled. This includes inventory storage, transportation and work in process (WIP). Further precautions during transportation include using dissipative carts with conductive wheels or drag chains in conjunction with a conductive floor when transporting ESD-sensitive devices in their shielded containers. 4.9.1 Packaging Semiconductor components are commonly shipped in partitioned carrier trays typical of those shown in Figure 4-22. The carrier trays are designed to be compatible with automated pick-and-place assembly systems and are sealed for shipping using antistatic/conductive plastic envelops. Warning labels on the packing will show that the contents are sensitive to ESD. The components should be kept in their original ESD packaging until distributed to the production floor. The sealed ESD envelopes will prevent the plastic-encased components from absorbing moisture from the air. If the seal is broken and components are partially unpacked, the unpacking should be done at a protected ESD-controlled workstation and any devices not used should be packed again in conductive or antistatic packing or carriers.


Figure 4-22 Partitioned Carrier Trays for BGA Components (Example source: Simplimatic) 4.9.2 Component Storage The detrimental effects of absorbed moisture in semiconductor packages during SMT assembly are well documented. Moisture can impact the wettability of the components’ surface layers. Furthermore, moisture penetration can initiate a popcorn effect that can cause cracking and delamination with the semiconductor package structure. The plastic mold compounds used for packaging commercial semiconductors simply do not provide adequate protection from humidity or harmful gasses penetrating the interior surface of the die element. The component manufacturer is responsible for establishing the level of moisture sensitivity level (MSL) of the device per J-STD-020. If the devices remain in an uncontrolled environment and retain moisture levels above those which are specified, it would be necessary to predry or bake-out the units prior to assembly. Further detail for handling, packing, shipping and use of moisture/reflow-sensitive surface mount devices is furnished in J-STD-033. 4.10 Thermal Management of 3D Components Three-dimensional packaging offers a high level of integration of electronic devices with enhanced electrical performance and functionality. However, stacking multiple active device or packaging layers proportionally increases heat dissipation rates per unit volume, and dielectric layers with low thermal conductivity that exist between chips can lead to high temperatures. Heat is the single biggest cause of failure in electronics. Statistically, reducing the operating junction temperature by as little as 10 °C can double a device’s lifetime, so managing thermal dissipation remains a primary challenge for multiple-die, configured components.

The more complex the 3D package, the greater the requirement for managing thermal rise of each individual component, particularly if they are all connected in series. The interactions between functionally different semiconductor elements become even more pronounced and are more challenging to characterize. It is not uncommon for a 3D-configured component developer to position the logic or processor die at the lower part of the stacked die or stacked package device with memory, controllers and other supporting die above it.

4.10.1 Thermal Conduction/Convection The thermal rise of the processor elements is generally much greater, so providing a thermal conduction path downward (Figure 4-23) becomes an obvious solution. However, when the thermal rise cannot be dissipated adequately though downward conductive methods, more extreme solutions will be introduced.


Figure 4-23 Thermal Conduction The goal of a 3D cooling system is to keep the junction temperature of the chip and the temperature nonuniformity of the system at or below the maximum allowable limit. Several innovations in cooling technologies are being pursued to address these needs. These include innovations in:

• Thermal interface materials • Mold compounds for embedded and fan-out packaging • Microfluidic cooling

Thermal assessment of 3D-packaged die elements will require exacting analytical calculations. These calculation procedures will require thermal specifications for each die in order to prepare empirical analysis for thermal modeling. A thorough thermal analysis will involve a broad range of tools to support and validate conclusions of the modeling data. A primary source for thermal rise is junction temperature (TJ). Maximum junction temperature (TJ Max) is normally furnished in the manufacturer’s specification or datasheet. This factor is then used for calculating the package-to-ambient thermal resistance for a given power dissipation.

An estimation of the chip-junction temperature, TJ, can be acquired from the following equation:

TJ = TA + (R θJA x PD)

where: TA = ambient temperature for the package (°C) R θJA = junction to ambient thermal resistance (°C/W) PD = power dissipation in package (W)

Starting from the heat source (transistor junction), heat may transfer through two paths. In the first path the heat transfers from the transistor junction through the molding compound by conduction, and then to the air surrounding the device by convection. In the second path, which is parallel with the first, heat flows from the junction of the device through the termination features (Cu wirebonds, solder balls and bumps or Cu pillars) into the package substrate and eventually through the conductor pattern on the host board.

4.10.2 Thermal Transfer Mechanisms The need for new cooling techniques is driven by continuing increase in power dissipation of electronic parts and systems. In many instances standard techniques cannot achieve the required cooling performance due to physical limitations in heat transfer capabilities. These limitations are principally related to the limited thermal conductivity of air for convection and copper for conduction.

Air-cooled heat sinks (see Figure 4-24) could be used for cooling 3D ICs. Since the surface area of the heat sink is usually much larger than the side area of the chips, most of the heat from a 3D IC will be conducted to the heat sink. Implementation of copper thermal vias can increase the effective thermal conductivity of the IC stack up and provide better thermal paths to the heat sink.


However, vias are obstacles to routing, so it is better to use as few as possible while meeting the thermal performance requirement.

Figure 4-24 Thermal Transfer Paths 4.10.3 Advanced Thermal Interface Materials Advanced thermal interface materials are required to control the die temperature against escalating power densities in 3D packages, lower cost materials and with increased reliability under emerging system conditions. This implies higher thermal conductivity with improved adhesion, strength and fatigue resistance. Thermal interface materials are based on thermal grease or gel that fill the gap between contact surfaces and reduce the thermal resistance. Traditional thermal interface materials have thermal conductivity of less than 10 W/mK. The thermal resistances are projected to reach 25 mm2 K/W with nominal bondline thicknesses of 50 µm to 100 µm and additional interfacial resistances as illustrated in Figure 4-25.

Figure 4-25 Thermal Resistance vs Bondline Thickness for State-of-the-Art Thermal Greases and Gels The limitations of grease and gels can be overcome with emerging materials such as:

• Solders • Solder composites (e.g., solder-graphite composites) • Advanced nanocomposites with copper nanowires, copper nanosprings, boron nitride

sheet, CNT or graphene


Bonded thermal interfaces with CNT-thermoplastic composites have demonstrated thermal resistances of 3 mm2 K/w and with advanced 1D and 2D nanomaterial, resistances of 0.4 mm2 K/w are projected. This trend toward lower thermal resistances is illustrated in Figure 4-26.

Figure 4-26 Advances in Thermal Resistance With Thinner and Higher-Conductivity Reliable Materials For high-power modules, nanosilver or nanocopper bonding materials are emerging as alternative to solders for lower thermal resistances. Engineering the pore structure and filling with polymer also provide better reliability projected with the lower interfacial stresses of these materials. Direct integration of a heat sink to the direct-bonded copper (DBC) or active metal brazing (AMB) substrate, without an intermediate baseplate, eliminates the need for the secondary transient intermodulation distortion (TIM) and reduces the contact resistance (see Figure 4-27).

Figure 4-27 Nanosilver Interconnections From Infineon (CuSn Intermetallic), Semikrion (left) and Infineon (right) 4.10.4 High-Conductivity Mold Compounds Emerging trends in 3D embedded packages are also driving advances in improved mold compounds and high-conductivity composite dielectrics. These packages are either based on:

1) Reconfigured molded dies as fanout wafer-level packages (FOWLP) or 2) Die embedding in packages with standard PCB infrastructure as shown in Figure 4-28


Figure 4-28 Advances in 3D Packages With FOWLP and Die-Embedding (Left) and High Thermal Conductivity Composites With Advanced Boron Nitride Fillers and Surface Treatments (Right) Figure source: (Liang, Moon and Wong, ECTC 2009)

Molding compounds are typically based on novolac resins with temperature-stability of up to ~ 175 °C. They have ~ 90 wt. % filler loading, with moisture absorption < 1 wt. % and thermal conductivity of ~3 W/mK. Mold compounds need to meet several criteria such as high degradation temperature, low melt viscosity for easy processing and engineered filler content for process ability.

There is an increasing need to improve thermal conductivity of mold compounds, while also increasing their thermal and voltage stability and electromigration resistance. Several innovations are pursued to accomplish this. These include incorporation of high-thermal-conductivity fillers such as BN, AlN or crystalline-silica fillers, surface treatment to enhance heat dissipation, prevent moisture adsorption at the interfaces, etc. An example is shown in the PoP in Figure 4-28.

4.10.5 Liquid Cooling Using high velocities and high-pressure commercially available microcoolers can handle about 1 kW/cm2. Liquid cooling methods for 3D semiconductor package applications are divided into two categories; indirect and direct liquid cooling. Indirect liquid cooling is one in which the liquid does not directly contact the components to be cooled. Direct liquid cooling brings the liquid coolant into physical contact with the components to be cooled. The indirect liquid cooling will typically rely on heat pipes and cold plates, while direct liquid cooling may incorporate liquid immersion or jet spraying. The heat sinking products range from machined, cast or extruded alloy configurations to sophisticated air-to-air, air-to-liquid, liquid-to-liquid and two-phase condenser and evaporator heat-exchange systems (see Figure 4-29).


Figure 4-29 Liquid Heat Pipe Exchange System (Figure source: Acrolab) Heat-exchange systems rely on heat pipes to transport or spread heat to a point remote from the semiconductor’s heat source having limited airflow. Manufacturers offer a wide range of heat pipe sizes suitable for processor integration as high as 50 W. The example shown in Figure 4-25 is said to have a thermal conductivity rating that is 20,000 times greater than solid copper, having the same physical geometry. 4.10.6 Microfluidic Cooling Microfluidic cooling addresses the challenges with solid-state and convection cooling. Liquid cooling has advantages over air cooling due to its higher specific heat and thermal conductivity of liquid compared to air. Water has superior thermal properties than other liquids and shows feasibility for cooling 3D ICs, but high electrical conductivity is one of its downsides. Dielectric liquids are preferred because of the electrical properties, but they have poor thermal properties. 4.10.7 Single-Phase Intertier Cooling Intertier cooling for 3D ICs utilizes integrated on-chip microfluidic cooling. Each tier consists of integrated microchannels, through-silicon electrical vias, through-silicon fluidic vias, solder bumps, and microscale polymer pipes. Solder bumps and electrical vias are used for power delivery and signaling. Pin fins can be employed instead of straight micro-channels to enhance heat transfer. 4.10.8 Two-Phase Intertier Cooling One of limitations of single-phase cooling is the bulk fluid temperature rise along the flow direction due to the sensible heating, which results in temperature nonuniformity on the chip. Two-phase cooling is an alternative approach for which the bulk fluid temperature depends on the saturation pressure. It has a higher heat transfer coefficient, so reduced fluid flow rates are required. The resulting smaller pressure drops can result in higher surface temperature uniformity. A comparison between a conventional air-cooled heat sink and two-phase microchannel heat sink (see Figure 4-30) shows the temperature difference between layers is reduced by more than 10 °C using microchannels due to the small thermal resistance of direct heat removal from layers. The two-phase microchannel cooling has the distinct characteristics of a nonuniform temperature distribution, even under a uniform heating condition. The temperature increases along the channel in the liquid-phase region due to sensible heating, and it decreases in the two-phase region due to decrease of the fluid saturation pressure along the channel.


Figure 4-30 Comparison of 3D ICs Utilizing Different Cooling Technologies 4.10.9 Heat Pipes

Heat pipes provide an enhanced means of transporting heat from the primary heat source to a heat sink, where it can be dissipated into the cooling medium by natural or forced convection. Heat pipes provide an indirect and passive means of applying liquid cooling. The internal walls of the pipes are lined with a porous medium (the wick) that acts as a passive capillary pump. When heat is applied to one side of the pipe, the liquid begins to evaporate. A pressure gradient exists causing the vapor to flow to the cooler regions. The vapor condenses at the cooler regions and is transported back by the wick structure, thereby closing the loop. 4.10.10 Microchannel and Minichannel Cooling Conceivably, a matrix of narrow channels may be incorporated into the package interposer for dissipating heat generated by the semiconductor(s) mounted on its surface. The word micro is applied to devices having hydraulic diameters of tens to several hundred micrometers, while mini refers to diameters on the order of one to a few millimeters. In many practical cases, the small flow rate within microchannels produces laminar flow, resulting in a heat transfer coefficient inversely proportional to the hydraulic diameter. In other words, the smaller the channel, the higher the heat-transfer coefficient. Unfortunately, the pressure drop increases with the inverse of the second power of the channel width, keeping the mass flow constant and limiting ongoing miniaturization in practice. 4.10.11 Thermal Modeling Thermal management should be considered during package selection to ensure high product reliability. All ICs generate heat when power is applied to them. Therefore, to maintain the device's junction temperature below the maximum allowed, effective heat flow from the IC through the package to the ambient is essential. Computational fluid dynamic and finite element base heat transfer software could be used to develop a correlation for convection heat transfer through the liquid module test bed. Alternate materials in the semiconductor package, such as aluminum nitride substrate carrier, aluminum nitride DBC, diamond heat spreaders, microstructures and thin-film insulation, could also be studied using simulation tools and then confirmed experimentally. When appropriate thermal models are combined with empirical data, the user can have high confidence that the results accurately reflect real-world applications. Electrical design tools such as PSpice® or Cadence® can be used to make simple thermal models of packages. The package elements are represented as resistors connecting to the board in a resistor network. When the package model is confirmed to agree with empirical data, then the model can be used to predict package variations, including: die sizes, exposed pad sizes, fused leads, or the number of grounds connected to planes. These "what if" models give a reasonably accurate prediction of customized configurations.


5 INTERPOSER/SUBSTRATE MATERIALS

5.1 Organic Interposer An interposer is an electrical interface between different levels of a die or package. It used in 3D assembly in order to connect devices using wider pitch and low cost technology connections. The interposer material could vary between organic substrate silicon or glass. 5.2 Glass Interposer Glass is used as an interposer/substrate material because it has lower dielectric loss and costs less than silicon (see Figure 5-1). Its lower costs stems from its wide use for liquid crystal displays (LCDs) because it is a large panel-sized substrate (see Figure 5-2).

Several glass materials are candidates for 3D applications because they have CTE similar to silicon (for minimizing die stress) and between silicon die and the package substrate (to balance the overall package stress). Also photosensitive glass provides simple TGV forming processing.

Glass also differs from silicon wafers because it can provide final substrate thickness from 50 µm to ≥ 700 µm to eliminate the back-grinding process. Glass size and shape are also more flexible than silicon wafers or panels (square or rectangular). Regarding panel shape, panels up to 500 mm x 500 mm are examined for utilization in PCB and LCD manufacturing equipment.

Figure 5-1 Simulated Insertion Loss (S21) of TGV and TSV Interconnects (Source: Georgia Tech)


Figure 5-2 Glass Wafer and Panel Substrates (Source: Asahi Glass)

5.3 Silicon Interposers The silicon base for semiconductor and interposer fabrication begins with the growth of a silicon ingot. Growing a silicon ingot can take anywhere from one week to one month, depending on size and quality specified. Growth of the ingot (as described by suppliers) requires chunks of virgin polycrystalline silicon that are placed into a quartz crucible along with small quantities of dopants. These materials are then heated to a temperature of 1,420 °C, somewhat above the melting point of the silicon.

The added dopants (commonly boron, phosphorus, arsenic and antimony) give the desired electrical properties for the grown ingot. Once the polycrystalline and dopant combination has been liquefied, a single silicon seed crystal is formed on top of the melt. Growth initially begins with a rapid pulling of the seed crystal. The pull speed is then reduced to allow the diameter of the crystal to increase. When the desired ingot diameter is achieved the growth conditions are stabilized (Figure 5-3).

Figure 5-3 Microcrystalline-Silicon Ingot (Example source: Addison Engineering)

After the ingot is fully-grown, it is ground to a rough size diameter (slightly larger than the desired diameter of the finished silicon wafer). The round ingot is then flattened on one surface to establish orientation. When it has passed a number of inspections, the ingot is sliced into moderately thin wafers, generally with the aid of a diamond-edge saw (Figure 5-4).


Figure 5-4 Flattened Feature on Wafer Edge Identifies Wafer Orientation During Fabrication Processes (Example source: Addison Engineering)

After the wafers have been sliced, a lapping process is employed to remove saw marks and any surface defects. Once the silicon wafers are lapped, they undergo an etching and cleaning process followed by surface polishing.

5.4 Ceramic Substrate/Interposer Alumina (Al2O3) and aluminum nitride (AlN) substrates (for high-power applications) are the most common compositions for ceramic substrate fabrication. Beryllium oxide (BeO) may also be considered; however, beryllium dust particles generated during the sawing and drilling processes have been deemed a health hazard.

The ceramic-based material for electronic substrate applications is furnished in panel format (Figure 5-5).

Figure 5-5 Ceramic Panel Prior to Metallization Example source: CeramTec)

The maximum panel size can be as large as 200 mm x 200 mm [8 in x 8 in]; however, the 127 mm x 127 mm [5 in x 5 in] panel size is more common. Ceramic suppliers offer a broad range of thicknesses for substrate applications: 0.25 mm, 0.38 mm, 0.50 mm, 0.63 mm, 0.76 mm, 1 mm, and 1.27 mm as well as special thickness such as 1.6 mm or 2 mm.

5.5 Conductor Characteristics (Copper Foil/Film) Typical PCB copper thicknesses for substrate applications are 17 μm and 34 μm; however, thinner copper may be specified for applications requiring higher circuit density.


The current carrying capacity of copper foil is determined by the allowable temperature rise above ambient resulting from the current flowing through it. See IPC-7092 for two tables on the current rating for different copper foil thicknesses to appropriately size the substrate power delivery structures.

As an example, to pass 10A of current on a 34 μm surface copper layer, the circuit must be designed with at least 5.0 mm copper traces to maintain a 20 °C rise in temperature above ambient for the conductor.

IPC-4562 covers metal foils supported by carrier films and unsupported foils suitable for subsequent use in PCBs, and it addresses the requirements for procurement of these same metal foils. Unless otherwise agreed upon between user and supplier (AABUS), metal foils shall be considered acceptable as long as the requirements in IPC-4562 are met. Although copper foil has been traditionally specified in terms of its weight in ounces per square foot, specifying copper foil thickness with measurable dimensions may prove more practical. The copper weight and thickness table in IPC-7092 lists the corresponding copper thicknesses in both metric and inch factors for various copper weights. 5.6 Conductor Characteristics (Metallization on Silicon) In metallizing silicon, it is common practice to first sputter a metal alloy adhesion layer on the silicon surface prior to applying the metals used to provide component termination sites (land patterns) and circuit conductivity. Adhesion-promoting metals include: nickel (Ni), molybdenum (Mo), chrome (Cr), tungsten (W) and titanium (Ti). These base materials are then over-plated with a more conductive metal (e.g., copper, gold, tin and palladium) in a pattern to provide the land pattern mounting sites and interconnect features. Copper has become a preferred alloy for interposer via and circuit plating. Following pattern plating, the remaining adhesion layer is chemically etched from the silicon surface, which is followed by applying a passivation layer to insulate and protect the remaining conductive circuit pattern. 5.7 Conductor Characteristics (Metallization on Glass) Glass is metallized very similar to silicon, but glass does not require a barrier layer since it is an insulating material. Other process steps, materials used and equipment used are the same as silicon. A metal alloy adhesion layer is commonly achieved by sputtering a thin metallic adhesive (Ti, Ti-Cu, Cr) and copper seed layer to accommodate additive copper electroplating for filling via holes and forming the conductive pattern on the upper and lower surfaces of the glass substrate. Alternative glass metallization methods have been developed for filling via holes with copper pastes and inks, which are lower cost versus plating. These methods are underdevelopment and need to demonstrate improved compatibility with RDL metallization processes. 5.8 Conductor Characteristics (Metallization on Ceramic) Two process variations are commonly applied for forming electrically conductive interconnects on ceramic-based substrates: thick film and thin film metallization.

Thick-film metallization refers to the thickness of the conductor layer applied to the surface of the ceramic panel. It is done with a screen-print process and is fired at high temperature for curing. Thick film compositions are typically thixotropic or pseudoplastic fluids that have a high viscosity at rest but a low viscosity when a shear force is applied during printing. Thickness of the deposited material will range from 10 μm to 13 μm, while thin-film conductor thickness (noted below) will be < 10 μm.

Thin-film metallization enables the sequential buildup of multiple layers of thin-film conductors,


resistors and insulators to the surface of a ceramic dielectric material. This is done by vacuum deposition or sputtering to create a nearly planar circuit. This technology can also selectively integrate thick-film materials and can be used to add surface layers to co-fired substrates. The primary advantage of thin-film processing is the finer line and space capabilities. See the thin film technology capabilities table in IPC-7094 for current fabrication capabilities for thin-film ceramic substrates.

6 PROCESS MATERIALS 6.1 Adhesives (Conductive and Nonconductive) IPC-3406 furnishes guidelines for electrically conductive surface mount adhesives. IPC-3408 covers performance requirements for conducting adhesives, considering the chemistry of the adhesive and the material composition of the filler particles. The standards furnish details of isotropic and anisotropic adhesives used for attachment of flip-chip packages or CSPs having noble alloy contacts. They cover performance requirements for the material when used in the assembly as well as long-term performance characteristics.

IPC-3406 defines the attributes of the polymer carrier and conductive particles in isotropic and anisotropic conductive adhesives to ensure reliable interconnection between the chip and the mounting structure.

Attributes of the polymer carrier include:

• Adhesive bond strength to various surfaces over time • Viscosity • Tg • Cure schedule • Purity

Conductive particle requirements include:

• Conductivity • Geometry • Size • Concentration • Composition • Compliancy • Purity

6.1.1 Polymer Adhesives Data source: Johns Hopkins APL Technical Digest, Volume 28, Number 1 (2008) Polymer adhesives generally fall into three main categories or applications:

• Thermally and electrically non-conducting • Thermally conducting and electrically non-conducting • Thermally and electrically conducting

Polymeric materials used for adhesive applications in electronic packaging are generally of two types: thermoset and thermoplastic. Thermoset materials- Polymers developed for high temperature curing will cross-link and become solid when subjected to the elevated temperatures. Thermoset materials (e.g., epoxies, polyimides, and cyanate esters) require exposure to elevated temperatures to cure or induce


cross-linking chemical reactions between the monomers. Depending on the adhesive chemistry, varying time periods are required to cure the polymeric system; cure schedules for epoxy formulations range from “snap cures” that require only a few minutes at 150–175°C to the more standard cure schedule of 0.5–2 h at 150–175°C; higher temperatures (e.g., 275°C) are required to cure polyimides. When used in hermetic packages, the materials are subjected to a bake-out (typically done in an inert environment such as flowing dry nitrogen or sometimes under vacuum) to outgas volatile components, and then the packages are sealed in dry nitrogen. Thermoplastic materials- Polymers formulated for microelectronic applications become softer at elevated temperatures. Thermoplastic materials include amorphous polymers (e.g., sulfone-based polymers, imide-based polymers, and polyarylates) and crystalline polymers (e.g., ketone-based polymers and polyphenylene sulfide). These materials do not require a cure and are processed by raising the temperature above a particular value at which the material becomes soft; this temperature is defined as the glass transition temperature (Tg). During the attachment procedure, the temperature is raised above Tg; therefore, rather high Tg is required in order for the adhesive joint to survive high-temperature exposure during subsequent processing. Despite simpler processing steps and the potential for rework, it should be noted that thermoplastic materials generally do not have mechanical shear strengths as high as those for thermoset materials. The particle fillers used to enhance the mechanical characteristic of polymers include inorganic materials such as silica, alumina, aluminum nitride, diamond, and carbon nanotubes; metals such as Ag, Au, Cu, Ni, and Al; and metal-coated polymer spheres to provide some elasticity in special z-axis interconnection applications. Polymer adhesives can be dispensed from tubes, screen printed, or placed on substrates in a tape format (generally that is pressure-sensitive). To ensure a good interface between the adhesive and die or substrates, cleaning of the components often is required before assembly, and, in most cases, some chemical additives are present in the polymer formulation to improve the interface adhesion. Voids, especially at the various interfaces, are to be avoided, so volatile solvents generally are not used in the current generation of microelectronic adhesive formulations. 6.1.2 Dry Film Adhesive Data source: Adhesives and Sealants Industry (ASI) In high-volume commercial applications, the use of 10 µm to 20 µm die-attach film adhesive has been proven to be reliable for single die attachment and stack-die applications from 2-3 layers. The 10 µm to 20 µm film adhesive not only ensures the thinner package outline required for 2D and 3D package applications but it also provides a more uniform and controlled flow of the adhesive. Key advantages of dry film adhesives for die attach include:

• Simplified adhesive handling • Delivery of precise adhesive quantities • Elimination of resin-bleed problems • Formation of uniform die perimeter fillets

A key advantage over the liquid polymer alternatives is the dry films ability to be cured on the die bonder without the need to go offline for adhesive cure These adhesives also provide greater bond-line-thickness uniformity, elimination of tipped die occurrences and prevention of die float that often happens with the liquid variations. 6.1.2.1 Die Attach Film Application Data source: Adhesives and Sealants Industry (ASI)


Applying die-attach film at the wafer level before singulation has a significant advantage over individually placing adhesive material at each die-attach site. To completely take advantage of die-attach film at the wafer level, however, the material selected must be optimized to withstand various process conditions that the film will be subjected to during the remaining stages of processing. The material must perform without degradation in any of its end use properties, including adhesion strength and thermal and electrical properties. Material must meet key attributes:

• Die attach film adhesive must be compatible with the adhesive layer of the dicing tape to prevent cross-contamination leading to residues and other side effects.

• Must enable multiple level die-stack bonding with high efficiency. • Provide a stable wire-bonding operation of up to 250°C for the highest production

rate possible. • Meet the performance requirements of JEDEC IPC level 3 or better for moisture

sensitivity after packaging.

In case of high-temperature applications beyond the typical 125-150°C, non-epoxy die attach materials are available to withstand long-term usage of 200°C and beyond. 6.2 Solder Materials (Data source: Kester) In compliance with RoHS and the Europeans WEEE Directive, a majority of electronic manufacturers have eliminated Lead (Pb) alloy solders and adopted solders that are Lead-Free (Pb-free) for assembly processing. The two main Pb-free alloys are variants of Tin-Silver-Copper and Tin-Copper. These alloys have higher melting temperatures and wet metal surfaces more slowly than solder compositions containing Lead alloy. Furthermore, the Pb-free solder joints look different in that the surfaces are not as reflective as Tin-Lead joints. Concerns have been addressed regarding flux compatibility, termination alloy compatibility and substrate finish compatibility with Pb-free solders. There have also been concerns about the high temperature profiles potential for warping or material decomposition of the thin substrates typically utilized for semiconductor packaging. The reflow process also requires strict monitoring to achieve adequate wetting and flow characteristics of lead-free solders. The chemistries, however, have become more thermally stable and offer the engineer the maximum operating window for process control. These optimized flux chemistries have resulted in solid reliability for the process and the assembly; further preserving production yields in-line with Pb solder processes. Materials shown in Table 6-1 are a reference listing of commercially available Pb-free alloys with their respective reflow temperature range. Table 6-1 Common Pb-Free Solder Paste Compositions (Table source: Kester)

Alloy Composition Melting Temperature (°C) Comments SnAg4.0Cu0.5 217 to 224 SnAg3.9Cu0.6 217 to 225 iNEMI alloy SnAg3.5 221 SnAg2.5Bi1.0Cu0.5 214 to 221 SnAg3.0Cu0.5 217 to 221 Favored in Japan SnAg3.8Cu0.7 217 to 218 Near eutectic SnAg3.5Cu0.7 217 to 218 Commonly used SnAg2.0Bi3.0Cu0.75 207 to 218 Low liquidus temperature SnAg3.5Cu0.9 217 Eutectic SnAg3.4Bi4.8 191 to 216 Low liquidus temperature SnBi7.5Ag2.0 191 to 216 Low liquidus temperature


SnIn20Ag2.8 175 to 187 Low liquidus temperature SnBi58 138 Low temperature SnIn52 118 Low temperature

The table above is not meant to be an exhaustive list and is not meant to preclude the potential use of other alloys, however, the SnAgCu (SAC) family is the alloy of predominant choice for all regions of the world. A goal for many is the selection of a eutectic alloy composition. The true eutectic composition is primarily Tin alloy with the addition of 3.5 to 3.8 percent Silver alloy plus 0.7 to 1.0 percent Copper alloy (SnAg3.5-3.8Cu0.7-1). The National Institute for Solder Technology (NIST) has defined the true eutectic composition as SnAg3.5Cu0.9. In Japan 2/3 of companies’ use a SAC alloy for reflow soldering but SnAg, SnZnBi, SnAgCuBi and SnInAgBi are also used to a lesser degree. The following includes alternative recommendations from a number of leading organizations:

• The NEMI consortium in USA recommends SnAg3.9Cu0.6 for surface mount reflow soldering.

• The JEITA lead-free roadmap in Japan recommends SnAg3.0Cu0.5 for reflow soldering with SnAg and SnZnBi as secondary alternatives.

• The IDEALS consortium in Europe preferred SnAg3.8Cu0.7 for reflow soldering. • SOLDERTEC lead-free roadmap in Europe recommends the Sn alloy with a Ag

content ranging between 3.4 to 4.1 and Cu content in the range of 0.45 to 0.9 for reflow.

The small percentage of Cu in these compositions increases thermal cycle fatigue resistance and slightly reduces the temperature where the material reaches liquidus. The addition of Bismuth (Bi) further reduces the materials liquidus temperature and is said to improve wettability during reflow processing. Most alloy compositions referenced above can be used for printing or dispensing but powder size will be significantly reduced for dispensing. 7 PACKAGE-LEVEL STANDARDIZATION (JESD30) The Joint Electron Device Engineering Council (JEDEC) is the primary North American organization responsible for establishing standards and guidelines for semiconductor package outlines. The JEDEC Solid State Technology Association, with its associated committees, is the engineering standardization body for solid-state products in the United States.

A principal function of JEDEC is to promote the development and standardization of terms, definitions, product characterization and operation, test methods, manufacturing support functions, product quality and reliability, mechanical outlines, solid-state memories and wireless interface networking systems. JEDEC also provides and administers a service whereby companies that manufacture discrete solid-state products may register their products according to a type designation system.

7.1 Package Outline Standards Limiting semiconductor package size continues to be a factor; however, the package outline will likely be controlled by the size of the largest die, number of interface contacts and the contact pitch selected for package interface. Because of the relatively high I/O required to interface multiple die, the interposer and/or substrate will commonly adopt a uniform array-configured ball or bump-contact design. The base structure selected must be mechanically stable enough to withstand the process


temperatures of the entire package assembly process (e.g., die attach, wire bond and encapsulation).

7.1.1 BGA

JEP95 defines a BGA package family in which one or more semiconductor devices are attached to either the top or the bottom surface of a dielectric carrier.

A BGA package outline can be square or rectangular with an array of metallic balls on the underside of the package which accommodate both mechanical and electrical connection from the package body to a mating feature such as a PCB. The surface that contains the die element(s) may be encapsulated by various techniques to protect the semiconductor (Figure 7-1).

Figure 7-1 BGA Package Outline

Table 7-1 represents the allowable variations for contact diameter and contact pitch.

Table 7-1 BGA Contact Diameter and Pitch Variations Data Source: JEDEC Publication JEP95, Section 4.14

Ball Pitch (mm) Ball Diameter (mm)

Min Nom Max

0.50 0.25 0.30 0.35

0.65 0.25 0.30 0.35

0.65 0.35 0.40 0.45

0.80 0.25 0.30 0.35

0.80 0.35 0.40 0.45

0.80 0.45 0.50 0.55

7.1.2 Fine-Pitch BGA (FBGA/FIBGA) A fine-pitch BGA (FBGA/FIBGA) package is a reduced-pitch (< 1.00 mm) version of a BGA package. An FIBGA is an FBGA with staggered (< 1.00mm) pitch. The carrier body of the package has a metallized circuit pattern applied to a dielectric structure (Figure 7-2).

One or more semiconductor devices are attached to either the top or the bottom surface of a dielectric carrier. On the underside of the dielectric carrier is an array pattern of metallized balls


which form the mechanical and electrical connection from the package body to a mating feature such as a PCB. The surface that contains the die may be encapsulated by various techniques to protect the semiconductor.

Figure 7-2 Fine-Pitch BGA Package (Fujitsu)

Although die elements may be attached to either the top or the bottom surface of this dielectric carrier, die attach to the upper surface of the carrier is most common. As with the BGA package described in 7.1.1, the array pattern of metallized balls on the bottom surface will form the mechanical and electrical connection between the package body and a mating feature such as a PCB. The surface of the carrier that contains the die may be encapsulated using various techniques to protect the semiconductor. Figure 7-3 represents the allowable variations for contact diameter (b) and contact pitch (p).

Figure 7-3 FBGA/FIBGA Contact Diameter and Pitch Variations (Figure source: JEP95 FBGA/FIBGA Design Guide 4.5)

Figure legend

A – contact diameter

B – contact pitch

Note to designer: A goes between top arrows; B goes between arrows on the side.

Table 7-2 FBGA/FIBGA Contact Diameter and Pitch Variations (Table source: JEP95 FBGA/FIBGA Design Guide 4.5)

Diameter

(Figure 7-3, A)

Pitch (Figure 7-3B)

Min. Nom. Max

0.80 0.45 0.50 0.55


0.40 0.45 0.50

0.35 0.40 0.45

0.30 0.35 0.40

0.25 0.30 0.35

0.65 0.35 0.40 0.45

0.30 0.35 0.40

0.25 0.30 0.35

0.50 0.25 0.30 0.35

0.20 0.25 0.30

0.40 0.20 0.25 0.30

0.15 0.20 0.25

Package outlines range from 2 mm square to 22 mm square with 0.50 mm increments allowed up to 10 mm. Although the JEDEC design guide exhibits a uniform contact pitch for all package outlines, some manufacturers have introduced products with multiple pitch variations. 7.1.3 Package-on-Package (PoP) The PoP configuration described in JEP95, consists of at least two microelectronic packages assembled in a vertical stack. The technology accommodates differing die outlines and enables the mixing of heterogeneous die functions. It also enables the utilization of multiple die sources or multiple sourcing for same-function die.

Vertically stacking provides an efficient solution for system-level packaging because each section can be fully tested before joining. The JEDEC design guide details two variations (see Figure 7-4):

• The flange-type construction has a substrate or carrier that extends outward beyond the perimeter of the die, which forms a flange with respect to the die.

• The second variation is a fully over-molded BGA PoP with TMV technology.

Figure 7-4 JEDEC PoP Construction Variations


PoP contact pitch and diameter are dependent on the surface area remaining outside the die attachment area of the carrier for joining the upper and lower package sections. The bottom surface of the lower package section can be fully populated or selectively depopulated. Both upper and lower package sections follow the general ball size and pitch variation guidelines furnished in JEDEC Standard 95-1, Fine-Pitch Ball Grid Array (FBGA) Design Guide, section 4.5.

7.1.4 TMV PoP The TMV package described in JEDEC Registered Outline MO-302 furnishes detail for a very thin, fine-pitch, fully over-molded, stackable BGA family adopting 0.40 mm contact pitch. When the PoP design guide outlined in JEDEC Standard 95-1, section 4.22 is applied to the contact size and pitch, variations will have greater latitude. This registration is in compliance with the fine pitch, square ball grid array (FBGA) PoP guidelines in JEDEC Standard 95-1. 7.1.5 Wafer-Level BGA (WLBGA) Wafer-level BGA (WLBGA) is a BGA in which the body size is equal to the die size. This package is sometimes called a “real chip-size” BGA, wafer-level CSP or a flip-chip-type package. JEDEC JEP95 defines a finished WLBGA package that is commonly furnished with an array of metallic balls on the underside of the package; however, other contact variations have evolved.

The package substrate is the semiconductor die with or without a redistribution layer. It may have a square or rectangular shape with metallic balls applied onto the circuit side of the die. The array contact pattern provides both mechanical and electrical connection from the package body to the next-level component such as a package substrate of the host PCB. The size of the package is equal to the die size (see Figure 7-5).

The ball or bump contact diameter is measured in a plane parallel to the seating plane (datum) (see Table 7-3). The measured value for each ball or bump contact is the largest such diameter for that ball or bump. The measured values are usually within the ranges specified for each pitch.

Figure 7-5 Contact redistribution at the wafer level provides a method for furnishing a uniform array format to better accommodate face-down mounting


Table 7-3 Comparing WLBGA Contact Pitch (e) to Ball or Bump Contact Diameter (b) Range (Table source: IPC-7094)

Seating Plane

Diameter

Min. Nom. Max

0.65 0.35 0.40 0.45

0.65 0.30 0.35 0.40

0.50 0.30 0.35 0.40

0.50 0.25 0.30 0.35

0.50 0.20 0.25 0.30

0.50 0.15 0.17 0.19

0.40 0.20 0.25 0.30

Typically, when balls are present, they consist of eutectic lead/tin solder or lead-free solder alloy; however, raised solid-copper post or pillar contacts have proven to be a viable alternative, especially for very fine-pitch WLBGA applications.

In a wafer-level BGA (WLBGA), all processing required to attach a silicon IC chip on a PCB is performed at the wafer level. The term WLBGA is used to describe only individual chips after wafer dicing. The dimensions of the body accommodate assembly only of a die with a specific size; these outline dimensions may change as a result of process refinement of the semiconductor element.

The format of the device may be square or rectangular, but this aspect ratio may also change as a given device is redesigned to conform to a new die size. The aspect ratio will likely differ for devices of the same functionality from multiple suppliers. The contacts on the WLBGA may be spherical, bumps or other protruding terminals constructed from a variety of alloy and/or polymer materials.

7.1.6 Stacked-Die Packaging Standards

A number of process variations have been developed for stacking and interconnecting die elements within a single-package outline, however, JEDEC documents focus mainly on the physical aspects of the finished package, not on how a package is manufactured. Users are directed to utilize the existing BGA package standards or registered outlines when developing their products.

JEDEC JC-63, however, contains primarily electrical interface items related to multi-chip packages (MCPs) and stacked CSPs (SCSP) of mixed-memory technologies (e.g., Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, etc.). These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies. The section also contains silicon pad sequence’ information for the various memory technologies to aid in the design and electrical optimization of the memory subsystem or complete memory stacked solution.


8 PRINTED BOARD AND OTHER MOUNTING BASE OR BOARD STACKUP CONSIDERATIONS As a key part of planning for semiconductor substrate applications It is important to research the various products in order to choose the one best meeting the design requirements. The attributes that should be considered are:

• Moisture absorption • Fire retarding capability • Electrical properties • Mechanical properties • Thermal properties

Because the package substrate will be exposed to a broad range of thermal extremes during package assembly and later when attached to the host circuit board, selecting organic materials exhibiting higher decomposition temperature (Td) and glass transmission (Tg) temperatures is paramount. The designer and fabricator should concurrently review material selection for cost, performance and process efficiency. 8.1 Printed Board Technology (data source: TTM Technologies) Advancement in printed board technology has been prompted by numerous factors. When the electronics industry was bound by new regulations to eliminate lead from solder materials, new formulations of laminate need to evolve. In addition, component packaging innovations were introduced with smaller contact features and very high I/O. Through miniaturization of components and semiconductor packages the boards could be made smaller. More components on a smaller board platform then drove suppliers to higher circuit densities. Boards that are classified as high-density-interconnect (HDI) are characterized by unique attributes including:

• Laser ablated and plated microvias • Very fine lines and spaces • Multiple layer construction, blind and buried vias • Adapting very thin dielectric materials

This increased density enables more functions per unit area. Higher technology boards will often have multiple layers of copper filled stacked micro vias creating a structure that enables even more complex interconnections. These very complex structures provide the necessary routing solutions for today's higher pin-count semiconductors utilized in high technology products. 8.1.1 Multilevel PCB Substrate A multi-level substrate is commonly applied when it becomes an advantage to integrate key components within the substrate structure. These components are generally closely associated with the semiconductor(s) mounted on the substrates outer surface (see Figure 8-1).


Figure 8-1 Two-Level Substrate With Embedded Components

Advantages gained when adapting embedded component technology include more efficient surface area utilization and improved electrical performance. Furthermore, as frequencies rise and circuits become more complex, additional passive elements may be required in order to maintain signal integrity. For detailed process information refer to IPC-7092, Design and Assembly Process Implementation for Embedding Components. 8.2 Mounting Base Both flip-chip and wire-bond assembly processes will be impacted by the physical attributes of the organic substrate material selected. Flip-chip configured die are generally furnished with solder compatible contacts (see Figure 4-7). The land pattern geometry for mounting the flip-chip configured component will likely be very small and have very close spacing. And, although via pad and hole locations for subsurface circuit routing may be fanned out from the die elements mounting site, it’s not uncommon for designers to place via holes within the flip-chip land pattern. If vias are integrated within the land pattern the designer must specify that via holes be plated closed, plugged or tented. This will prevent or minimize void propagation in the solder interface during the reflow processing. Furthermore, land pattern metallurgy, and certain solder mask chemistries can adversely affect underfill flow and encapsulant adhesion.

• IPC-4201 specification covers the requirements for base materials commonly referred to as laminate or prepreg, to be used primarily for rigid or multilayer printed boards for electrical and electronic circuits.

• IPC-4202 standard establishes the qualification and quality conformance requirements for flexible base dielectric materials to be used for the fabrication of flexible printed circuitry.

8.3 Surface Finish for Placed Components Substrate surface finishes serve several functions, these include: solderability surface protection, wire bondable surface, and conductive polymer joint interface. Although semiconductor packaging is the focus of this document, other components and assembly operations must be taken into consideration. While no surface finish is ideal for all applications, technologists will adopt plating or coating materials that will provide a reliable interface and ensure high manufacturing yields.

8.3.1 Electroless Nickel/Immersion Gold (ENIG) The ENIG plating process first applies an electroless nickel as a barrier coating over the substrates bare copper contact sites. A thin immersion coating of gold alloy follows to prevent oxidation of the nickel surface. This copper surface finish is highly resistant to corrosion, and is both solder process compatible and, with aggressive cleaning of the surface, wire bondable.

Note: the chemistry and process may be incompatible with some passivation and solder mask materials.


8.3.2 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) Similar process to the ENIG plating described above, ENEPIG is formed by the deposition of electroless nickel, followed by electroless palladium, with an immersion gold flash. ENEPIG has exceptionally wide application: it is suitable for soldering, gold wire bonding, aluminum wire bonding, and contact resistance. 8.3.3 Organic Solderability Preservative (OSP) OSP is an anti-tarnish coating of an organic compound (such as a benzimidazole-based compound) that is applied over exposed copper surfaces to prevent oxidation. An OSP is commonly a water-based organic compound that selectively bonds with copper to provide an organometallic layer that protects the copper, preserving its solderability. Various chemistries of OSPs are available. Some common ones are benzotriazole, imidazole and benzimidazole.

8.3.4 Electrolytic Nickel/Electrolytic Gold (ENEG) Electrolytic Nickel and Gold processes have been specifically engineered to provide the widest operating window for pattern plating of nickel and hard or soft gold. The individual products in the process have been specially formulated to provide the optimum metal distribution for improved throwing power and surface distribution. The electrolytic gold plating processes exhibit excellent adhesion and have minimal attack on aqueous resists. Electrolytic nickel/electroplated gold is applied after pattern plating and most often before solder mask. Solder mask applied over electrolytic nickel/electroplated gold may exhibits lower adhesion than other surface finishes.

8.3.5 Direct Immersion Gold (DIG) Direct immersion gold plating is generally applied after solder mask processes are complete. Gold-on-copper provides a noble metal that seals the exposed Cu surface against oxidation and maintains solderability. Gold immersion plating, however, is not as robust as ENIG plating and can exhibit poor Au-to-Cu adhesion characteristics. Solder joint characteristics, however, are said to be excellent when the film thickness is within the range of 30nm to 80nm. On the other hand, excessive copper surface roughness can affect uniform solder flow,

8.3.6 Immersion Silver (IS) A process similar to OSP, silver alloy is deposited directly on the exposed copper surfaces following solder mask application. The process provides a flat surface for solder or conductive polymer joining. An issue that seems to have been mitigated with the newer solder alloy compositions and flux chemistries is micro voids that propagate at the solder interface. When the micro voids are excessive they have the potential to initiate cracks that, over time, can result in solder joint failure.

8.3.7 Immersion Tin (IT) Immersion tin is a metallic solderability preservative that prevents copper oxidation and preserves solderability throughout the assembly process. Immersion tin, like Immersion silver and OSP, is deposited directly on the exposed copper surface to provide a flat surface for applying solder paste. During the solder reflow process, the combined copper and tin alloy forms an intermetallic that enhances solder joint robustness. Tin alloy combined with tin-rich soldering alloys, however, can promote tin whiskers in some environments. These tiny whiskers can cause electrical shorts and lead to product failure.

8.3.8 Copper (Chemical Deposition and Electroplate) Copper plating is commonly used for providing electrical continuity in via holes and to build-up conductive circuits on the substrates outer surfaces. This is a multi-stage process that begins with a chemical pre-treat of the panel followed by a seeding of the hole walls with micro-particles of


palladium. The next step is to chemically deposit a one-micron thick layer of electroless copper over the via-hole walls. Copper is finally deposited using an electroplating process. While adhering to the via hole walls the process will build-up additional copper over the outer surfaces of the substrate.

Note: This plating processes described above are simply meant to be an overview and may vary somewhat between suppliers.

8.4 Embedded-Component Technology

The electronics industry recognizes that to maximize a product’s performance potential, the substrate can no longer act only as a platform for mounting and interconnecting electronic components on the outer surfaces. Both passive and active component elements are candidates for embedding (Figure 8-2).

Figure 8-2 BGA Package Adopting an Embedded-Component Substrate In addition to minimizing the component’s outline, embedding one or more active die within the substrate structure has the potential for enhancing performance due to the shorter interconnect length between active die elements.

8.4.1 Formed Resistor Process The most mature and economical process developed for embedding passive components is defined as forming. Using various ink formulations, copper foil-based materials and filled dielectric composites, a broad range of resistor and capacitor elements are being distributed within the layering structure of the PCB. Inductor elements can be furnished as well by chemically etching a narrow copper conductor pattern within the circuit.

Several thin-film resistor technologies are available. Supplied as laminate, sheet materials with resist values that range from 25 Ω/sq to 1 kΩ/sq are available. Thin-film laminates are comprised of a layer of resistive material deposited onto copper foil which are then laminated to the core structure of the dielectric base material with the resistor element side facing down. The circuit pattern is then chemically etched to define the basic conductor path and land features. This is followed by a secondary etchback process to define the resistor elements geometry (Figure 8-3).


Figure 8-3 Pull-Up and Pull-Down Resistors Using Thin-Film Material (Example source: Ohmega Technologies)

The example in Figure 8-2 depicts a nickel-phosphorous (NiP) metal alloy that is electrodeposited onto the matte (tooth side) of the copper foil. Because of its thin film nature, it can be embedded within layers without increasing the thickness of the component substrate or occupying any outer surface area required for mounting die elements. Other thin-film resistor approaches include:

• Chromium silicate (CrSi) resistive sheets deposited onto polyimide film • Tantalum nitride and nickel chromium sputtered directly onto the substrate

8.4.1.1 Design Criteria for Sheet Film-Type Resistor Elements

All aspects of the system’s thermal dissipation must be considered in the component substrate design. Critical thermal dissipation requirements may require thermal profile modeling or actual prototypes to ensure proper configuration is achieved. Furthermore, because the sheet resistance of the thin film-embedded resistor is isotropic, the resistor patterns can be designed in any orientation required by the I/O or to optimize spacing. The resistive foil is an integrated part of the system and should not be considered as an isolated element when designing for thermal dissipation. Factors that affect thermal dissipation in the system are:

• Circuit configuration • Circuit thickness and material type • Thermal conductivity of dielectric • Proximity of power or ground planes to resistors • Ambient temperature • Additional system cooling or heat-sinking • Resistor size (total resistor area)

Careful planning is paramount. When selecting embedded passive component candidates, the designer must consider the optimum value and tolerance range of the materials. Drift limits following thermal shock or humidity exposure can be an issue as can be aging behavior of dissimilar materials. More detailed process variations for formed resistor methodologies are furnished in IPC-7092.

8.4.2 Capacitor Formation Process Forming a capacitor element within the multilayer circuit structure is somewhat more complex. There are two primary techniques for fabricating embedded capacitors: planar


and discrete. 8.4.3 Planar Capacitance A planar capacitor is produced when dielectric material is laminated between opposing copper circuit layers. These copper planes generally provide the power and ground layers of the component substrate.

Because these copper planes extend across the entire substrate, the PTHs or microvias connecting the power and ground planes can be placed very close to the power and ground inputs of the device. This close coupling results in lowering loop inductance. Low inherent inductance will deliver current to the device on a very short time scale, greatly damping fluctuations of the voltage at the device input.

8.4.3.1 Plane Layer Separation Capacitance value is achieved using materials of different dielectric constants and different dielectric thicknesses. The planar capacitor simply sandwiches a dielectric material between two layers of copper foil.

IPC-7092 notes that the dielectric layer may be a common organic composite, polyimide, organic polymer thick film (PTF) or ceramic thin film (CTF) composite. The PTF or CTF composite dielectrics can be applied for both discrete and planar capacitors. PTF material density is equal to 20 pF/mm2, while CTF materials will have a density rating of approximately 24 nF/mm2.

8.4.4 Discrete Formed Capacitor Element Since area is defined by component size, capacitance value in discrete components is achieved by use of different dielectric thicknesses combined with materials of different dielectric constants. Additionally, use of multiple layers in ceramic capacitors increases the capacitance directly proportional to the number of layers.

Although the fabrication process is significantly more complex, layer stacking of capacitor elements (Figure 8-4) provides a smaller footprint and greater capacitance density.

Figure 8-4 Formed Multi-Layer Capacitor Element

Discrete formed capacitors can be designed to furnish values ranging from 1 pF to1 μF. The lower values are principally used for filtering, timing and A/D functions and require high tolerance and stability. The higher values are used for decoupling and energy storage and primarily require high capacitance but can tolerate a significant variation in tolerance and stability.


8.4.5 Discrete Inductor Forming Inductor elements can be integrated directly into the copper circuit layers. Formed inductors are current loops configured to induce a magnetic field for storing and controlling inductive energy. Inductance is measured in henry units (H), an effect that results from the magnetic field that forms around a current-carrying conductor. Current flowing through the inductor creates a magnetic field that has an associated electromotive field which opposes the applied voltage.

Figure 8-5 Etched Copper Spiral Inductor Pattern

The total length of the spiral and number of turns determine the inductance of the element. The spacing between turns will control the resonant frequency of the inductor. A wider spacing between conductors will typically reduce capacitance and raise the inductance frequency.

8.4.6 Discrete Component Placement The interconnect platform can become a key enabler in developing a system-level product. A significant number of semiconductor packaging specialists have already developed multiple-die component substrate structures utilizing large-scale embedded component technologies. Both passive and active component elements are candidates for embedding.

8.4.6.1 Discrete Resistor and Capacitor Placement Companies are furnishing very thin, small-outline resistors and capacitors that are proving to be ideal for embedded-component applications. The outlines of available components are as small as 0.4 mm x 0.2 mm (01005) and 0.6 mm x 0.3 mm (0201). Discrete thick-film and thin-film resistors are offered in a very thin 0.015 mm profile.

Very small-outline capacitors are also available; however, due to the value selected, the dielectric thickness of these devices can increase, which requires a cavity feature within the component substrate (Figure 8-6). The cavity-mounted component is then encased within the prepreg material of the subsequent build-up circuit layer.

Attachment and termination methods of these components are detailed in IPC-7092.


Figure 8-6 0201 Components Embedded Into a Cavity Feature in the Substrate

8.4.6.2 Discrete Inductor Placement Miniature inductor components have been developed with a small outline and low profile using thin-film metal patterns on a ceramic base material. These smaller outline inductor elements range in size from 1.6 mm x 0.8 mm x 1.0 mm thick down to 0.61 mm x 0.31 mm x 0.28 mm thick. Manufacturers claim the miniature inductors furnish up to twice the rated current and half the DC resistance of comparable ferrite inductors. The value range for the small-outline discrete inductor elements, however, is somewhat limited.

8.4.6.3 Active-Die Element Placement Several methods can be used for embedding semiconductor elements, but the die bond sites will require some preparation. Aluminum-plated bond pads, traditionally furnished on the wafer-accommodated aluminum- and gold-wire-bond interconnect, will not be compatible with other termination methods. When a semiconductor die is placed within the layers of the primary interconnect substrate, the die must have terminals with a plating compatible with the interconnect process.

A number of processes have been developed to furnish contact features that are compatible with a wide range of interconnect methodologies. Generally referred to as under-bump metallization (UBM) (see 8.4.6.6), the secondary plating process will furnish a strong barrier to prevent the diffusion of other bump metals into the active area of the semiconductor element. Typical die-to-package substrate interface methods include:

• Solder bump • Solder ball • Conductive polymer • Copper pillar or post • Copper wire-bond

If solder bumps or solder ball contacts are to be provided on the bond sites, the final UBM plating material must be readily wettable for reflow soldering. 8.4.6.4 Electroless Nickel/Immersion Gold (ENIG) A relatively low-cost UBM process chemically etches the aluminum bond surface and applies a zinc alloy seed layer that enables an electroless nickel plating process. An immersion gold plating process follows to prevent oxidation of the nickel alloy. The thin gold coating maintains long-term solderability and prevents nickel oxidization and passivation.

Component land

Ablated

Resin coated copper


8.4.6.5 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) Electroless nickel/electroless palladium/immersion gold (ENEPIG) surface finish provides a solder-compatible surface and a gold or aluminum wire-bondable bond pad surface. The electroless palladium is typically in the 0.05 µm to 0.15 µm range topped with the immersion gold being plated in the 0.025 µm to 0.05 µm range. 8.4.6.6 Copper Under-Bump Metallization (UBM) Plating A more robust plating process provides relatively thick copper alloy on the bond sites. To prevent oxidation, the copper surface is plated or coated with a surface preservative. Copper wire-bond has become the preferred interface technology for a broad range of 3D packaging applications (Figure 8-7).

Copper wire offers significant cost advantage over gold wire and has proved to be an excellent replacement due to its similar electrical properties. Self-inductance and self-capacitance are nearly the same for Au and Cu wire, and Cu wire has significantly lower resistivity.

Figure 8-7 3D Die-Stack Package Using Cu Wire-Bond Processing (Source: Amkor Technologies)

8.4.6.7 Redistribution Layer (RDL) Process Redistributing the wire-bond sites to a uniform array pattern on the die element’s active surface is used to enable more efficient conductor routing when the die element is mounted face-down onto the package substrate. The RDL process is performed following basic copper UBM plating. Redistribution employs an additive copper plating process following a passivation process that covers the active surface of the die (Figure 8-8).

Figure 8-8 Additive Redistribution Layer to Array Contact Site (Source: Amkor Technologies)


As noted above, the interface contact can be a solder bump, preformed solder ball typical of that in Figure 8-7 or a copper pillar or post prepared for reflow solder processing or thermocompression bond interface.

8.5 Substrate and Interposer Materials (Package Level) While stacked die and stacked package solutions have grown rapidly as a near term response, there remain issues with power, latency, and bandwidth. A number of new semiconductor families are emerging that will demand greater interconnect densities than possible with today’s organic substrate fabrication technology.

Two alternative base materials have already evolved as more suitable for the both current and future very high-density package applications. The two base materials with the physical attributes considered capable for the very high-density interposers are silicon and glass. Both materials require adopting unique via formation and metallization methodologies to enable the interface between one side of the interposer to the other. Once the vias are formed between the two sides of the interposer, a metallization process is applied to complete die-to-die and side-to-side interconnect. The example shown in Figure 8-9 illustrates the primary elements that represent the 2.5D/3D package technology.

Figure 8-9 Merging Organic and Silicon-Based Materials for 3D Semiconductor Packaging 8.5.1 Organic Circuit Structure The package substrate developed for the 2.5D/3D package applications is typically fabricated in a panel format using the epoxy-glass family of dielectric as its base, with copper foils furnished for land pattern features and interconnecting circuits. The substrate may serve simply as an interconnect platform to further fan-out the contact pattern for PCB mounting, or it may include


embedded passive and active die elements for expanding package functionality. See 8.4 for more detail regarding embedded-component substrate fabrication. 8.5.2 Ceramic Circuit Structure (Data source: AdTech Ceramics) Electronic packages typical of those furnished in Figure 8-10 are produced with the co-fire multilayer ceramic process have four distinct processing stages:

• Materials preparation • Green processing • Sintering • Postfire processing

Alumina is the most popular ceramic material for multilayer packages. Because it has been used for many years its performance is well characterized, with a proven track record. Alumina offers high strength, good thermal conductivity and excellent electrical properties.

Figure 8-10 Ceramic-Based Interposer (Example source: AdTech Ceramics) The fabrication process for ceramic interposers includes four distinct steps; these are material preparation, green processing, sintering, and post-fire processing. Material preparation consists of milling raw materials into a dielectric "green tape". Green processing consists of punching cavities, via punch, via fill, screen-printing, and lamination. Once the green process is complete, the ceramic/metal composite is "co-fired" in a carefully controlled atmosphere. Post fire processing consists of additional printing, sawing, machining, and brazing. Almost all packages are plated with Ni and Au for both solder and wire bond applications. 8.5.2.1 Metallization on Ceramic The metallization process for ceramics is largely dictated by the base material composition. Alumina and aluminum nitride require refractory metals such as tungsten (W) and molybdenum (Mo) for high temperature sintering in protective atmospheres. Also available are a variety of thin and thick film surface metallization. Ceramic packages are typically supplied with gold over nickel (Au/Ni) plating on the metallized areas, and can have metal components attached by brazing or soldering. Nickel is plated on all exposed metal surfaces to allow brazing and enable solderability. Final plating may be either electroless or electrolytic nickel and gold. Electrolytic plating requires that all exposed circuits be temporarily electrically connected through a lead frame, internal tie bar, or a combination of the two. A combination of electrolytic and electroless plating can be used if designs require. Before beginning the design process, it will be prudent to discuss the application and state expectations with candidate suppliers because design rules and process capability can vary a great deal from one ceramic interposer fabricator to another.


8.5.3 Silicon Circuit Structure Silicon interposer circuit routing enables very close coupling between related die elements, thereby minimizing the interface requirements and broadening the contact pitch between the interposer and organic-based package substrate. The contact features located on the individual die elements may have a pitch as small as 30 μm to 50 μm, while the contacts on the bottom surface of the Si interposer are fanned-out to a wider 150 μm to 200 μm pitch. The wider-pitch contact pattern on the bottom surface of the Si-based interposer will better accommodate solder ball or solder bump contacts for reflow solder attachment to the top surface of the organic-based package substrate. 8.5.4 Glass Circuit Structure Glass interposer circuit routing enables very close coupling between related die elements to reduce the circuit path between active die elements. Typical of an Si-based interposer, the glass-based interposer is designed to increase the contact pitch between the interposer’s bottom surface and the organic-based package substrate. 8.6 Dielectric Encapsulation Dielectric encapsulation can be described as the use of heat and pressure during lamination to force the prepreg resin system to flows into and around the copper signal/plane voids. The result is the resin fully encapsulating it to provide an adhesive bond from layer to layer. 8.6.1 Reinforced Prepreg Reinforced prepreg contains a mechanically and thermally stable structure, typically an e-glass (silica-based) fabric which is impregnated with resin. Reinforced prepreg provides improved dimensional stability of the overall dielectric composition 8.6.2 Unreinforced Resin Unreinforced resin is a homogenous composition of the target PCB resin system with no base reinforcement. 8.6.3 Resin-Coated Copper (RCC) Resin-coated copper is unreinforced resin applied to a layer of copper. The intention of the coated copper is for it to be used as one circuit layer within a PCB. RCC is generally used in microvia buildup layers. 8.7 Via Hole Preparation and Interconnectivity There is a broad range of process technologies that have evolved for glass-based interposer applications. The challenges developers have faced include physical strength of the glass materials, proficient via-hole formation methodologies and reliable via-hole and surface plating techniques. 8.7.1 TGV Connection to Board Copper The primary role of glass-based interposers is to redistribute the contact features of one or more semiconductor elements mounted on the upper surface to a contact format and pattern on the lower surface best suited for conventional printed board fabrication technology. This pattern, when furnished with a base metallization of copper, can accommodate a number of different interface variations typical of that applied to bare die flip-chip mounting (see examples shown in Figure 4-6).


8.7.2 TGV Connection to Component Terminations Die elements may be mounted onto the glass interposer with the active surface of the die facing up for wire-bond processing or facing down for direct-interconnect processing. Examples of face-up die mounting and wire bond interface are detailed in 4.7. Methodologies suitable for face-down die applications are exhibited in 4.6 and 4.7.3.4.

8.7.3 THROUGH GLASS VIA (TGV) FORMATION Reliable metallization of via walls is an essential requirement for the use of glass interposer applications. There are numerous methods to form holes in glass for TGV. These methods include:

• Mechanical drilling • Powder blast • Electrostatic discharge • Chemical ablation • Laser ablation

There are pros and cons to each method used with challenges presented by the ability to scale in size, achieve acceptable sidewall roughness (and associated mechanical reliability), overall cost and throughput. Variations in targeted properties, such as blind vs. through vias, sidewall shape/roughness and aspect ratio also provide challenges (Figure 8-11).

Figure 8-11 TGV shown has a 35μm top diameter in 100μm thick glass. Figure source: Corning

In some combined processes, a laser is used to modify the properties of photosensitive glass or other unique glass materials. For example, when hydrogen fluoride is combined with laser ablation, the etch rate in the laser-exposed areas is significantly faster than the etch rate in unexposed areas (Figure 8-12).

Figure 8-12 TGV-Formed Glass Substrates


Figure source: Asahi Glass

In general, 10 µm minimum TGVs are common, but sizes can vary based on ablation methods and system settings. Interconnections are achieved using copper physical vapor deposition (PVD), TSV metallization, copper paste or copper ink (see Figure 8-13).

Figure 8-13 Metallized TGV X-ray Photos Figure source: Dai Nippon Printing

8.7.4 Through-Silicon Via (TSV) Formation Through-silicon vias enable electrical connections through a silicon wafer from the active side to the backside of the die elements. This technology provides much higher interconnect densities than wire-bond or flip-chip interface technologies, especially when vertically joining die elements. TSV for interposer applications enables a higher level of functional integration of heterogeneous die elements within a small finished package outline.

The vias are commonly formed using a deep reactive-ion etching (DRIE) process. The most common technology used for performing the high-rate DRIE is referred to as the Bosch process. Although named for its inventor, the process is also known as ‘pulsed’ or ‘time-multiplexed’ etching, a process that alternates repeatedly between two modes to achieve nearly vertical hole structures. During the pulsed etching process, a passivation layer is formed onto the vias sidewall to block further chemical assault and prevent additional etching. These etch/deposit steps are repeated until the ablation reaches the desired depth. Although it is possible to etch via holes all the way through the silicon base, it is common to stop the etching process at a predetermined depth that will better promote blind via filling during the metallization process.

In preparation for blind via filling a seed layer of copper or tungsten is first applied to enable electroplating the additional copper required to complete the via fill operation. Electroplating is commonly employed for via sizes that range between 5μm and 20μm. To finally access the metallized ‘blind’ vias on the opposite surface of the wafer, a combination of grinding and/or etching processes are utilized. Further pattern plating processes are finally employed to provide surface interconnect features as illustrated in Figure 8-14 (see 5.7 and 8.7.5 for additional metallization process description).


Figure 8-14 Copper-Filled TSV Interface Between Wafers Active Side and Backside Example source: STATSChipPac 8.7.5 Via Filling Following via-hole formation, the holes are filled with a conductive polymer or plated closed with copper using an electroplating process. A number of companies are furnishing electrically conductive polymer products for via filling; however, a majority of TSV users have adopted a copper plating process to fill the tiny vias. The copper via filling process is achieved through a number of alloy deposition steps that begin with applying a thin adhesion layer to the wafer surface as well as via features using a radio frequency (RF) magnetron sputtering process. This is followed by a metal-organic compound deposition to provide a conformal, continuous and low-resistivity Cu seed layer. Electroplating is finally performed using a copper sulfamate plating solution. The copper electroplating process is complete in a relatively short time; however, while electroplating via features, a thin Cu layer (~10 μm to 20 μm) is deposited onto the active surface of the wafer. This surface can be processed to retain circuit interconnect features or, if interconnect is not required, removed to leave only the via sites exposed for die-to-die or die-interposer joining.

8.7.6 Alternative Via Plating on Silicon-Based Interposers

Two plating methods can be applied when filling ablated via holes in silicon-based interposers: conformal deposition and bottom-up deposition (both are compared in Figure 8-15). Conformal deposition is very fast, but it is susceptible to void formation within via holes. The bottom-up plating process, although slower, is generally void free.

Figure 8-15 Comparing Via Deposition Methodology. (Source: NEXX Systems) Although a majority of Si interposer fabricators prefer copper-plated vias, a number of companies are furnishing electrically conductive polymer products for via filling. 8.7.7 Conductor Forming on Silicon Interposers


This surface can be processed to retain circuit interconnect features or, if interconnection is not required, removed to leave only via sites exposed for die-to-die or die-interposer joining. Following wafer thinning to expose via sites on the bottom surface, a thin copper seed layer (~10 μm to 20 μm) is deposited onto both surfaces of the wafer. Electroplating is performed using a copper sulfamate plating solution in preparation for additional additive-copper plating to form the circuit pattern on the interposer top and bottom surfaces. Following the build-up layer of copper, the thin seed layer remaining is chemically ablated.

8.8 Buildup Layers and Via Hole Preparation (Redistribution Layer (RDL) on Silicon and Glass) Providing conductive circuits on silicon and glass wafers and panels requires implementing a fully additive metallization process. The metallization requirement is common to both dielectric materials; however, the process for providing the circuit pattern is very different. 8.8.1 Silicon Interposer Metallization The RDL process for silicon wafers or silicon panels begins by depositing a thin layer of metal (commonly a 100 nm-thick titanium-chromium-aluminum composition) to form the adhesion or ‘seed’ layer for plating other alloys. Photoresist is then applied over the surface and the circuit pattern is lithographically imaged to expose the seed layer for buildup metallization. When the material is immersed into an electroplating bath, a metal alloy (typically 5 µm to 10 µm Cu) is deposited onto the exposed circuit pattern. After copper plating, the photoresist is stripped, leaving the original seed layer metallization exposed to enable removal using a wet chemical etch process. 8.8.2 Glass Interposer Metallization Metallization of glass wafers or panels has proved to be a significant challenge due to poor adhesion between glass and metals. Developing a process for metal adhesion to the smooth glass surface and at the same time filling the through-glass-vias (TGVs) has shown to be a challenge as well. One approach for glass metallization is based on sputtering of a thin titanium-copper (TiCu) seed layer and subsequent buildup using electroless nickel deposition. This approach takes advantage of the relatively good adhesion exhibited for very thin sputtered films on glass surfaces and combines this with the ability of electroless plating of high aspect ratio of TGVs that are inaccessible to metallization by sputtering alone. More information on glass via formation and plating is furnished in 8.7.3. Although a number of methodologies have proved successful, companies and academia are also focusing on new developments in high-strength glass for interposer development. It is expected that a number of alternative metallization approaches will continue to evolve as well.

9 DESIGN METHODOLOGY 9.1 Design Challenges When considering 3D assembly, the design may be done by different people using different tools. Data exchange formats between different design houses and logistic are very important. All components may not be in the same CAD file and in the same format. An example is a PoP device, which because it is the top component is not part of the board assembly CAD file. Many times designs for 3D components, such as SiP, are not compatible with the board design, and they use different library symbols and formats. An ODM that wants to build on the substrate and mount it to a board will have to deal with the compatibility of different system that needs to be converted.


9.1 Total Circuit Consideration Designers of the substrate interposer and assembly process will need to establish the performance level and reliability requirements for the product. These requirements should be defined and ranked by a concurrent engineering or cross-functional team through a process such as quality function deployment (QFD) used to capture the voice of the user. IPC-D-279 defines the characteristics of various design concepts such as design for manufacturing (DfM), design for assembly (DfA), design for testability (DfT), and design for reliability (DfR).

Some of the basic reliability requirements and considerations include:

• Anticipated service life • Acceptable failure rate(s)/probability as a function of time • Life-cycle environment(s) • Definition of acceptable performance • Criticality of function(s) • Fabrication supplier qualification • Assembly system requirements • Available test equipment • Repair, replacement and warranty strategy

The component substrate interposer can be developed as an active structure with integrated or embedded component elements or it can be passive, simply interconnecting components that are to be mounted on the interposers’ outer surfaces.

The circuit design rules and fabrication methodologies for the following base material variations have very different requirements.

9.1.1 Internal (Embedded) Component Mounting When substrate size must be minimized, many companies adopt embedded-component technology. The idea of embedding components has become common for a number of applications. Those in the early stage of adopting the technology, however, should work closely with a designer or engineer who understands the benefits and risk differences (see 9.4).

9.1.1.1 Organic-Based Interposers Discrete passive and active components selected for embedding within an organic multilayer substrate structure will be subjected to a number of physical stress conditions. In addition, component parts may be as thin 25 µm, and terminal plating must have a metallization compatible with the joining process. The initial placement of the device onto the innerlayer substrate surface is not a significant concern but the PCB manufacturing process is a complex series of operations.

Lamination is the most stressful operation, and it may be repeated several times for more complex buildup structures. See IPC-7092 for more comprehensive guidance on selecting components for embedding and termination options.

9.1.1.2 Ceramic-Based Interposer Design Ceramic base materials exhibit very high thermal conductivity characteristics, making them ideal for advanced processor package applications. Because the coefficient of thermal expansion (CTE) is relatively low, bare die attachment will not be compromised. Typical ceramic material variations include; alumina (Al2O3) aluminum nitride (AlN) and low-temperature co-fired ceramic (LTCC) for multilayer applications. Ceramic substrates can provide high circuit routing density (100 μm lines and spaces). Formed passive resistor and inductor component elements may be included within the layer structure or on the substrates surface.


9.1.2 External (Surface) Component Mounting On external substrate surface locations where components are to be placed, the component parts selected should be configured with terminals designed specifically for solder or conductive polymer attachment. Each device type will have a specific land pattern geometry to accommodate the electrical and mechanical interface (refer to IPC-7351).

9.1.2.1 Solder Attachment A common material used in joining surface mount components is a paste-like composition of flux and tin alloy-based particles. The material is first applied to all land pattern features using a stencil or deposition process. Components are placed onto the land patterns and transferred into the reflow-soldering oven. The temperature is gradually raised to melt/reflow the solder particles in the solder paste, which joins the component terminals to the land pattern features.

9.1.2.2 Conductive Polymer Attachment Anisotropic conductive materials are widely available in both thermoset and thermoplastic chemistries. Manufactures offer these materials in a paste for screen and stencil printing and in a liquid form for dispensing (similar to that described above).

Following component placement, the joining material will cure to a solid state. The cure temperatures required may range from room temperature for two-part epoxy systems to a range of 80 °C to 175 °C for other single-component materials.

A few anisotropic materials are available for ultra violet (UV) curing. Thermoset materials typically cure more quickly in a thermal environment.

9.1.3 Internal (Embedded) Component Mounting Formed or placed components selected for mounting on internal layers of organic-based substrates will have many of the same attributes as those located on the outer surfaces. The methodology for electrically and mechanically attaching passive components is outlined in 9.4. The methods developed for attaching and interconnecting active components is detailed in IPC-7092 and also 8.4.6.3. 9.1.4 Circuit Interface Techniques Circuit interface criteria are somewhat product dependent. When the interposer outline is limited, the circuit interface will be minimized, especially for multiple-die, high-density and high-pin-count semiconductors. The circuit will typically include very short coupling distance between components.

9.1.4.1 Organic-Based Interposer Design The organic substrate core is typically manufactured using conventional PCB techniques. The substrate can have as few as two circuit layers or multiple circuit layers. Once preliminary component placement is established, the designer must address the conductor routing strategy. A power and ground plane scheme is typically established to accomplish the signal returns to enable an impedance control strategy and promote electromagnetic interference (EMI) protection. All layers reserved for conductor routing are then defined, and the routing direction for each circuit layer is specified (horizontal or vertical). During this planning phase, component land patterns and via hole patterns and sizes must be established.

Substrate developed as an interposer for component packaging will require a higher density interconnect strategy than required for conventional PCB applications. IPC-2226 identifies three


levels of complexity that define feature sizes for HDI construction (see Table 9-1). This table has been copied from IPC-2226 for reference purposes only. The reader is advised to reference IPC-2226 directly. Table 9-1 Typical Feature Sizes for HDI Substrate Constructions (Table source: IPC-2226)

Although the minimum circuit conductor width and spacing in the HDI document are shown to be in the 50μm range, a number of high-volume component substrate supply specialists are capable of furnishing 30μm wide conductors. The designer is strongly advised to thoroughly understand the suppliers’ capability, design rules and process alternatives before proceeding with the organic


substrate interposer design.

9.1.5 Internal Discrete Heat Sink 9.1.5.1 Organic-Based Interposer Design Managing the thermal rise of specific components is often a critical reliability concern. Whether mounted on the outer surface or embedded within the substrate layer structure, the designer must define the path needed to direct potentially damaging heat away from the device. The copper planes within the mounting base can contribute to transferring heat from components, and the use of dedicated thermal vias can further promote thermal dissipation by transferring heat to other layers of the organic substrate.

There are a number of thermal management materials designed to help the semiconductor in dissipating this heat by filling the gap between the semiconductor and heat spreader. Thermally conductive polymers are efficient for both die attach and thermal transfer to the heat spreader. The heat spreader may be as simple as a solid copper foil plane within the circuit structure or a heat slug that protrudes through the bottom surface of the interposer to interface with a broader heat-transfer feature on the host PCB.

9.2 Layout Strategy Component package design has become highly specialized. Many of the more established component packaging developers have the expertise to provide all necessary disciplines to develop the product. There are also competent designers and service bureaus that can be utilized when needed.

This decision is usually put forth when a project proposal is forwarded to management. The project engineer (or program manager) prepares the initial proposal and scheduling. The program manager will establish the program timeline and identify resources (personnel and equipment) necessary to accomplish the program goals.

Qualifications are critical to fulfilling the requirements. If company management determines internal resources are not readily available for a specific activity, they will need to establish an outsourcing plan or employ specialists to overcome the existing skill deficiencies.

9.2.1 Product Functional Description The process for determining packaging methodology is based on many factors. The first factor is to establish the components’ functional and performance requirements and develop an analysis to prepare a preliminary schematic. Wherever possible use established technology to minimize risk and time to market. Developing a basic high-density planar interposer for mounting and interconnecting components on its outer surface is common for multiple die or system-in-package applications.

9.2.2 Engineering Actions The interface between the engineering and design functions depends on many factors, including contractual vs. in-house approach, engineering’s degree of comfort in relinquishing control to design function, time available, etc. It is recommended that some degree of regular communication be maintained during the design process to avoid misinterpretations and miscommunication.

The statement of work (SoW) for outsourced can define more than the design, and its requirements should identify the deliverables. This portion of the SoW is critical. If the company


has a system for management control or configuration management, a person responsible for the system needs to input the SoW and monitor the deliverables.

9.2.3 Design Density Analysis After approved documents for schematic/logic diagrams, parts lists, end product and testing requirements are established, a feasibility density evaluation should be made. This should be based on the maximum area required for the parts and their attachment sites (land patterns) exclusive of interconnection conductor routing. The total substrate geometry required for component mounting and component termination will be developed and compared to the total area established for the finished component outline.

Reasonable maximum values for this ratio are:

• < 70 % for a less complex design (Level A) • 71 % to 90 % medium complexity design (Level B) • > 90 % (Level C)

Component density values higher than these will be a cause for concern. The lower these values, the easier to design a cost-effective, functional multiple-die component.

When the surface area required for component mounting exceeds the established package outline dimensions, the developer will likely consider one of three alternative process variations:

• Die stacking (wire-bond or TSV interface) • Package stacking (PoP, BVA) • Embedded component substrate (ECS)

An ECS designer will first determine the components and circuitry to be contained within the substrate layer structure as well as the components and circuitry that will be confined to the outer surfaces of the substrate. The density analysis should add a factor for providing test point access of the internal components so the functions within the substrate base can be verified before adding additional layering and external components. Further detail regarding area analysis of embedded component substrates can be found in IPC-7092.

9.2.4 Embedded Component Selection Although many discrete passive and active devices may remain mounted on the outer surfaces of the interposer structure, embedding passive components and one or more silicon-based semiconductor elements within the inner layers of the structure will enable greater utilization of the structure. This can improve performance among other benefits. For example, by embedding the uncased semiconductor element on an inner layer of the circuit vertically in line with a related semiconductor package mounted on the outer surface, the conductor interface can be minimized. Close coupling of semiconductor elements significantly reduces inductance and contributes to increased signal speed. Passive component elements, resistors, capacitors and inductors may be formed (printed or etched) within the circuit layers or, when small enough and thin enough, they can be placed onto the inner layers before lamination. Semiconductor die elements prepared for embedding must be very thin and furnished with contact features that are compatible with the termination method applied. 9.2.4.1 Embedding Passive Components Several materials properties must be considered when deciding whether or not to embed a particular component in a circuit:


• Available tolerance of the embedded parts • Drift limits following thermal shock or humidity exposure • Aging behavior • Temperature coefficients of capacitance or resistance (TCC/TCR) • Power-handling capacity (may include geometry of part) • Breakdown field and leakage currents • Q – especially important for RF and filter applications

Additional concerns include the available space for embedded parts, especially large capacitor elements. Also consider the physical density of embedded parts and the cost effectiveness of embedding components.

9.2.4.2 Embedding Active Components Silicon-based semiconductors are processed in a wafer format. The silicon wafer size is typically dependent on the complexity of the die element and the required volume needed to meet market demand. The active element of the semiconductor is commonly interfaced with the next-level package or carrier through wire-bond technology using contact metallization applied while the die elements remain in the wafer form.

There are numerous die-attach techniques that have been developed to join the uncased die-level device to the substrate. These include reflow soldering, ultrasonic, thermocompression bonding and anisotropic conductive and isotropic conductive polymer adhesives. Gold-to-gold interface can be considered, as well using thermocompression and ultrasonic energy used to complete the flip-chip bonding process.

The bond pads or lands on the die are commonly furnished with aluminum alloy for gold wire bonding. For those requiring solder, conductive polymer or copper via interface, the bond sites must be prepared with a copper metallization (see Section 7 for expanded detail).

9.2.5 Embedded-Component Circuit Interface IPC-7092 states that once the circuitry is defined, a preliminary component arrangement should be established. The entire circuit must be considered so all conditions for the final product are anticipated for both the manufacturing process and the testing that will be part of the fabrication sequences.

A preliminary estimate is made as to the number of layers that must be added to finalize the circuit. The initial determination established the component density based on one-sided or two-sided component mounting. The concepts develop a relationship that places those components that connect to one another in close proximity to simplify interconnection routing. An embedded-component base core considers those components to be mounted on the mounting base, be it a double-sided or multilayer product.

The mounting base circuitry is usually dedicated to interconnecting the components that are attached to either or both sides of the core. In this manner, the components to be embedded can be tested at a stage before any other layers are added. If there are remaining components that are part of the circuit, their placement and interconnection become the next part of the preliminary component arrangement. Depending on the complexity, additional conductive layers may be added to the embedded component base core. The external conductive surfaces have multiple functions. They provide lands for attaching components to the top surface and termination features on the bottom of the ECS (see Figure 9-1).


Figure 9-1 Embedded Semiconductor Substrate

9.3 Multilayer Substrate Construction and Geometries

9.3.1 Build-Up Circuit Layers on Glass Base Structures: The back end of the line (BEOL) process is used to make interconnections in very fine line and space silicon wafer applications, whereas WLP is used for > 1 µm RDL resolution. Traditional PCB buildup layer forming processes are used for panel-based glass interposers (see Figure 9-2).

Figure 9-2 Glass Interposer with 40 µm Pitch Bumps and L/S = 2 µm / 2 µm Traces (Source: SHINKO Electric Industries)

9.3.2 Build-Up Circuit Layers on Silicon Base Structures Silicon interposers provide an optimal integration platform enabling the direct routing between two and more active devices. The interconnect metallization of the connecting circuit is commonly separated from the silicon surface with a passivation layer (see 8.8 for greater detail). To further facilitate new semiconductor elements having ever shrinking contact pitch and high I/O, however, a single metal distribution layers may not be adequate. When these factors arise it will be necessary to consider implementing buildup circuit layer technology (see Figure 9-3).


Figure 9-3 Two-Layer ‘Buildup’ Circuit Interposer The addition of this second buildup metal and dielectric layer onto the surface of the wafer will eliminate the need to resort to extremely narrow lines and spaces to complete the interconnect. The buildup redistribution metallization can be fabricated directly onto the primary passivation or can be routed over the second layer of passivation to add additional compliancy. 9.4 Component Attachment on Multilevel Assembly Components can be mounted directly onto the inner layer base-core substrate using deposited solder paste and reflow processing or secured using an anisotropic conductive polymer and thermal cure process. Handling and placement of the very small passive components or thin semiconductor elements prepared for face-down mounting (see Figure 4-7) will require a high level of positional accuracy. Conductive Polymers- Anisotropic materials are a resin system that contains a filler of fine particles of silver or gold alloy, widely available in both thermoset and thermoplastic chemistries. Manufactures offer these materials in a paste for screen and stencil printing, and in a liquid form for dispensing. The cure temperatures after component placement may require only room temperature for the two-part epoxy systems to a range of 80°C and 175°C for other single component materials (see 6.1.1). Dry Film Adhesives- Semiconductor die elements designated for embedding are much thinner than those prepared for conventional package applications. When embedding die in the face-up condition, whether for wire-bond or micro via interface, the overall finished profile of the die element must be minimized (see 6.1.2). Solder Attachment- Solder processing will require an alloy composition that will ensure a robust electrical and mechanical interface between the component terminals and the land pattern provided on the substrate. To accommodate precision dispensing systems and control paste viscosity the solder paste material is furnished in small syringe like containers (see 6.2). 9.5 Circuit Routing Strategy (Organic and Nonorganic) As a general rule, the contact complexity of the uncased semiconductor die components does not exclusively determine the circuit density or the number of signal layers required. Other factors such as the final form factor, the contact pitch and, when multiple die elements are mounted on the same structure, the distance between parts. A more complex side-by-side or stacked die component set, for example, may easily justify more signal layers than those required for a single die application. 9.5.1 Organic-Based Substrates For organic (FR-4) based package substrate applications, designers are advised to distribute the copper conductor patterns evenly on all circuit layers. This provides a balanced structure and ensures better dimensional stability, reducing the materials tendency to bow, twist and warp during assembly processing. Guidance for determining circuit density and how to calculate tightly linked components or the substrate wiring capacity is detailed in IPC-2226.


9.5.2 Silicon and Glass Interposers Circuit routing on non-organic (silicon or glass) interposer structures will be limited to only two surfaces. While the bow, twist and warp condition may not be concern for these materials, increasing circuit density with build-up processing can be more complex (see 8.3.5). 9.5.3 Ceramic-Based Substrates and Interposers Circuit routing strategy for ceramic based substrates or interposers will depend on the fabrication process selected. When materials are furnished in a pre-fired rigid panel format the circuit will be printed or deposited onto one or both surfaces. Additional circuit patterns can be built-up on either or both surfaces as well but for higher density applications designers may consider multilayer ceramic technology. Similar to the strategy noted for the organic based substrate above, the circuit is deposited onto very thin layers of ‘green’ ceramic material, aligned together and fired at high temperature to complete the joining process (as described in 8.5.2). 9.6 Documentation In order to provide the ultimate degree of flexibility in the communication between disciplines, especially since some close relationships between partners often foster reduced descriptions, the documentation package has been segmented into five descriptive sections:

• Package design • Package specification • Substrate/interposer fabrication • Assembly process sequence • Electrical test and product verification

Each section is considered a stand-alone set of requirements, and is made up of a set of data that encompasses a variety of techniques or media in order to foster the data transfer of the descriptions needed to establish the degree of detail for producing the final product. 9.6.1 Documentation Package In preparation for developing the 2D, 2.5D or 3D semiconductor package a documentation package will be prepared. This package documentation shall include the following information:

• Package Design o Mechanical and electrical specification for die element(s) o Interconnect diagram and net list o Mechanical detail for die element(s)

• Package Specification

o Base material specification o Finished package outline dimensions (L-W-H) o Thermal management requirement

• Substrate/Interposer Fabrication

o Base material specification o CAD design file o Panel array format

• Assembly Process Sequence

o Assembly sequence process data o Test and performance specification o Electrical continuity testing

• Electrical Test and Product Verification


o Component functional in-circuit test o End product functional test o Environmental test verification

9.6.2 Bill of Material (BOM) A bill of materials is a list of all the different materials and components to be used in the manufacture of the semiconductor package. The information is arranged by a specific category of material or components and then by the OEM Design Number (ODN). This is the number assigned by the owner of the file. Each ODN has a list of attributes and is accompanied by a list of the various specific uses of the materials or components on the electronic assembly, each with its name or reference designator. 9.6.3 Software Tools and Data Transfer Software tools are available to assist the designer in describing the package assembly with details sufficient for tooling, manufacturing, assembly, inspection and testing requirements. The IPC-2581 standard can be utilized to specify a data file format used for transmitting information between a designer and a substrate/interposer manufacturing or assembly facility. The files are also useful when the manufacturing cycle includes computer-aided processes and numerical control machines. Although the CAD software tools utilized to deconstruct the file will permit the extraneous materials, it is recommended that only the material requirements identified as mandatory or optional are included in the data file in order to reduce file size transfer. 9.6.4 General Rules for 3D Design Two or more homogeneous semiconductor die can be encased within a single, fine-pitch ball grid array (FBGA) package outline. This process enables increased functionality in a relatively smaller package outline. The design of a multiple die package, however, requires a clear understanding of the relationship between die elements:

• The designer must first establish the critical interface criteria between related die elements within the package.

• The next concern is in defining the critical signal paths between the package and associated components on the PCB structure.

Other issues include managing and distribution of heat generated by semiconductor elements, establishing efficient power and ground distribution and careful attention to positioning key signal I/O locations to maximize interconnect efficiency between closely associated components on the host board.

10 ASSEMBLY OF 3D PACKAGES ON PCBS 10.1 PoP Assembly Process The PoP assembly process principle is similar to standard SMT. It starts with applying paste on the PCB lands and then placing the bottom package on the printed paste. In the next step, which is unique to PoP, the top package is dipped in a flux or paste reservoir with a known depth. As a result of the dipping process, the solder spheres on the top package are now coated with flux or paste. The top package is then placed on the top side of the bottom package on the printed board. The printed board then continues to the reflow oven, where both the top and bottom packages are soldered together at the same time. Figure 10-1 illustrates the PoP assembly principle.


Figure 10-1 PoP Assembly Principle 10.1.1 PoP Fluxing Options A fluxing module, which is available on most pick-and-place machines, is required for fluxing capability. Using one of these modules, the top BGAs are dipped into the flux film to apply the desirable amount of flux on the balls. There are two fluxing options used to create a controlled thin film of flux:

• Linear flux unit – A controlled thin film of flux is created by a fixed plate with a set cavity height and a blade which kneads the flux back and forth at the top of the cavity (Figure 10-2a)

• Rotating drum flux unit – Flux rotates in a drum, and the flux height is set by a squeegee blade (Figure 10-2b)

A B Figure 10-2 PoP Fluxing Units There are advantages and disadvantages to each of these fluxing unit options. The linear unit is less sensitive to changes over time, requiring less process control, but it will require a new fixture for each flux height, thus increasing cost. A concern with the rotary flux unit is centrifugal force can result in flux depth that is deeper at the edge of the drum and thinner at the center. For smaller prototypes and many product changes, the rotary flux unit is preferred. 10.1.2 PoP Fluxing Process To ensure a successful dip transfer process, flux material and process parameters must be evaluated and optimized.

Flux applied to a fixture with a known depth

Top package is dipped into flux

Top package is placed on bottom package

PoP board is going through the reflow oven

Bottom package is placed in a standard SMT process


10.1.2.1 Flux Coverage To ensure a successful SMT process, flux dip height should be between 50 % and 60 % of the BGA ball size. Figure 10-3 indicates the flux coverage of the BGA ball.

Figure 10-3 BGA Flux Coverage Too much flux height can cause open joints due to package floating, flux outgassing, surface insulation resistance (SIR) contamination and underfill issues. Too little flux height can cause incomplete collapse or open joints due to warpage. 10.1.2.2 Dwell Time (Hold Time) Speed Dwell time is defined as the length of time the BGA balls are in contact with the flux. As dwell time increases, there will be a slight increase in flux transfer amount, since the flux is given more time to cover the ball. The following are typical flux dwell time values

• 30 milliseconds (ms), low dwell • 200 ms, medium dwell • 500 ms, long dwell

10.1.2.3 Retracting Speed Retracting speed must ensure uniform flux on each ball. Too much acceleration can lead to excess flux or a string that can cause bridging at reflow. Typical values are 40 mm/sec to 200 mm/sec. 10.1.2.4 Retracting Force The vacuum nozzle must have sufficient force to pick the PoP package from the flux reservoir. 10.1.3 Flux Height Statistical Process Control (SPC) If flux is not visible on the ball, it is difficult to determine if good flux transfer occurred. Use one of the following methods to assess flux transfer consistency:

• Weigh the package before and after dipping • Use a dyed flux, which can be seen with automated optical inspection (AOI) • Place the dipped part on a copper coupon and inspect the coupon for flux transfer

uniformity See Figure 10-4 for flux transfer to a copper coupon.

50%-90% of the solder ball size

Dip flux


Figure 10-4 Flux Transfer to a Copper Coupon Most assembly houses ensure good control of solder height in the machine reservoir. This provides a level of confidence that good flux transfer to the BGA balls happened during flux dipping. Flux height is measured manually with a wet film gauge or a collar gauge. Figure 10-5 shows two type of gauges for measuring flux height.

Figure 10-5 Flux Height Measurement In high-volume manufacturing, a SPC chart can be made by measuring flux height every four to six hours to check that no significant change happened.

10.1.4 Paste Dip Pop assembly can also utilize solder paste for dipping instead of flux. Solder paste provides additional metal to the flux to help reduce the gap created from warpage between the bottom and top packages. It uses the same assembly process techniques as flux dip. Good paste dip needs to guarantee a monolayer of solder paste powder particles on the package ball. The solder paste for dipping is a fine-grain solder powder (usually type 5 or 6 paste) and has less metal loading. The potential trade-offs of using fine powder are:

• Slightly higher chance of solder balling • Shorter pot life • Slows melting due to sphere oxidation • Risk of bridging at fine pitch

Figure 10-6 shows the bottom termination side of the upper package section’s solder balls after paste dipping.

Excessive flux deposit

Non uniform and insufficient flux deposit

Good flux deposit


Figure 10-6 Solder Balls After Paste Dip 10.1.5 Prestacking Process In this process, pre-stacking of units is done on special pallets or carriers. The bottom part is then placed on the carrier in an assembly process similar to SMT. The top part is then flux dipped and placed on the bottom part, and then the carrier tray goes through the reflow oven. The unit is then placed on a tray or tape and reel and shipped to the SMT house, where the parts will be treated as standard SMT parts. See Figure 10-7.

Figure 10-7 Carrier with Prestacked Packages

The benefits of pre-stacking are the SMT house does not need a dipping process because SMT is done in a one-step placement process. The disadvantages of pre-stacking are PoP units going through an extra reflow cycle and the challenge of testing pre-stacked units. In addition, there are always questions about who is responsible for failure after SMT.

10.1.6 TMV/TMI Assembly Considerations TMV and TMI PoP technology have several SMT assembly challenges. SMT yield issues may arise when attempting to introduce a TMV/TMI process on an existing SMT line without doing any process characterization. The operators should also carefully select and optimize the flux/paste formulation used for dipping during PoP assembly. The flux needs to remain active and also be aggressive during the higher reflow temps required for SAC. The flux also needs to work on a large soldering surface for TMV balls that are two times larger than the pad size on a standard PoP (flange PoP) (see Figure 10-8). Since there are more oxides present on the lead-free ball that was reflowed than there are in a virgin pad surface, the flux will need to be more active to remove the additional oxides.


Figure 10-8 Soldering Surface of TMV Balls Adequate reflow is required to drive heat for complete coalesces through a small gap between packages after the balls collapse. As the memory collapses, closing the gap between the components, it is difficult to maintain adequate heat for complete coalesces (see Figure 10-9).

Figure 10-9 Ball Collapse The SMT process window for TMV/TMI packages is much narrower than that for standard PoP (flange PoP). Due to soldering challenges, it is recommended to use N2 during reflow to increase SMT yield. Microscopic visual inspection of the top joints is impossible on TMV/TMI PoP because there are no visual top joints after reflow (see Figure 10-9). Visible top package solder balls indicate an abnormality in the SMT assembly process, which could be a result of:

Incomplete ball collapse Package warpage Package tilt

X-ray analysis may be the best option for TMV/TMI PoP failure analysis, but even X-ray analysis can prove to be very difficult as the number of memory rows increases. 10.1.7 PoP Package Standoff Height (SOH) PoP package total Z height is defined as the total height between the board and the top of the package after assembly (see 10-10).

Soldering Surface


Figure 10-10 Z Height of a PoP Most applications have specifications for total Z height. Cases are designed to fit with very little air gap, sometimes with clearance only a few micrometers over a PoP package. The demands for low-profile devices are so challenging the product design width depends on the ball collapse of the packages during assembly. In some cases, only a frame is placed at SMT, and a shield cover will be placed after SMT. Most PoPs have a very low profile of total Z height of 1.1 mm to 1.8 mm after assembly. The SMT process can impact the total package height by changing the solder joint height, which some refer to as joint SOH. Figure 10-11 shows a cross-section of a PoP device which indicates the top and bottom package joints’ standoff height.

Figure 10-11 Joint Standoff Height (SOH) Stencil thickness, stencil aperture and flux or paste dip processes impact solder volume of the joint. As the devise pitch goes down, the ratio of paste to ball is increased and so is the impact on the Z height. Table 10-1 shows the mean and standard deviation of SOH of 0.4 mm PoP with 200 µm balls printed with different stencil opening. Table 10-1 SOH of 0.4 mm PoP With 200 µm Balls

Stencil Opening (µm) SOH (µm) Std (µm) 225 116.5 8.5 250 134.6 12.7 275 142.5 9.5

Board design could impact the Z height, like pad size and solder mask openings vs. nonsolder mask pads. Additionally, the reflow process N2 vs. air or inverted reflow to assembled PoP can impact the SOH.

Z height

SOH

SOH


10.1.8 PoP Die Gap PoP die gap is defined as the distance from the top of the bottom package to the bottom of the top package after stacking. The gap will ensure the die will not interfere with the top memory and cause it to tilt or lift during reflow. Figure 10-12 shows a cross-section of a flip chip PoP and the gap between the top of the bottom package silicon and the bottom mold of the top package memory.

Figure 10-12 PoPi Die Gap 10.2 3D Printing 3D printing is printing in more than one level. It can be done with a static 3D stencil mask or dynamically when the stencil mask is moving during the material deposition process. 3D printing is required when mounting components on PCBs with two or more levels. It will require a special stencil and squeegee when using the static approach, or a newer process like additive or jet printing. 10.2.1 Jet Printing (see manufacturer) Jet printing solder paste is an evolving technology which allows for applying solder paste to a 3D board in situations in which stencil printing is difficult. A special formulation paste is needed for jet printing. Currently dot size of 300 µm is possible for 0.4-mm pitch BGA. 10.2.2 Cavity Printing Cavity technology can be an effective solution to reduce total thickness (Z height) of the assembled PCB when the design utilizes 3D stacked devices. This is also referred to as a reservoir print. In this approach, the PCB will have a cavity where components need to be mounted on two levels of the board. Figure 10-13 shows a board with a cavity. A special stencil is needed to print the cavity on the two levels of the PCB. The stencil has a pocket matching the PCB cavity. Two types of 3D stencils are used: 3D electroformed and 3D welded stencil.

Figure 10-13 Cavity Board and 3D Stencil


Figure 10-14 shows a picture of 3D electroformed stencil with PoP apertures on a pocket for the cavity level on the right and apertures on another PoP on the top level.

Figure 10-14 3D Stencil With a Cavity Pocket on the Right A special squeegee is needed to successfully print inside the cavity. A slit-metal squeegee can be designed in which the slit area deflects at a different angle when it goes into the cavity during printing. It is important to adjust the squeegee on the machine to the location of the cavity during machine set up. See Figure 10-15.

Figure 10-15 Slit-Metal Squeegee Methods such as a pressure-printing head can also be used to apply pressure onto the cavity for successful printing. Figure 10-16 shows an assembled PoP mounted into a PCB cavity.

Figure 10-16 PoP Mounted Into a PCB Cavity 10.2.3 Cavity Keep-Out Zone As a general design guide, for a simple step-down stencil, the distance from the step edge to the nearest aperture (Z1 in Figure 10-17) should be 0.9 mm [35.4 mil] for every 0.025 mm [0.98 mil] of step-down thickness (see also IPC-7525). When a 3D stencil is needed for a deeper cavity, the design guide for Z1 is the cavity depth plus 1.27 mm [50 mils], including the stencil fabrication side wall slope, the PCB wall tolerance and alignment of the squeegee. Z2 is the distance between the aperture and the cavity on the flat level. Usually this keep-out zone is less conservative than Z1; at least 150 µm [6 mils] will be needed, plus the foil thickness.

Cavity area Cavity area


Figure 10-17 Cavity Keep-Out Zone 10.3 Multilevel Placement When dealing with a step board or cavity board, the placement machine program need to take into account a panel with varying thicknesses. Each machine has a different specification for the maximum Z axis travel allowed. This will define the depth of the step or cavity allowed for placing a component on the board. Varying 3D level depths may need to be programmed individually with different nozzle Z-height offsets for each level. Figure 10-18 shows a multilevel PCB with three Z-heights.

Figure 10-18 Multilevel PCB 10.4 Die Attachment 10.4.1 Direct Chip Attachment (DCA) Mounting the semiconductor in the facedown orientation (flip-chip) requires additional preparation to the die element. The most basic process provides a solder compatible copper metallization to each wire-bond site. The bond sites are then furnished with a small volume of solder alloy that, when heated to a liquid state, form a raised bump feature for subsequent soldering onto mating lands provided on the substrate surface. Reflow solder processing is the most common technique for flip-chip assembly and a substantial infrastructure already exists for supplying systems for both high and low volume manufacturing. Common methods for mass reflow soldering include:

• Hot Air/Gas Convection • Infrared • Conduction • Vapor Phase

To assure long-term reliability, the solder alloy composition selected must be compatible with the contact alloy and surface finish supplied on the mounting structure. In addition, both temperature and the cycle time required for soldering the lead-bearing solder and the lead-free solder can differ a great deal. The tin/silver/copper alloy compositions, for example, become liquidus at a

Level 1

Level 2

Level 3


temperature range that is much higher than the eutectic tin/lead alloy and the time duration for completing the joining process may need to be extended as well 10.4.2 Die-to-Substrate Reinforcement A common solution for overcoming thermal mismatch between die and interposer is to physically stabilize the die element using a liquid epoxy based underfill material (Figure 10-19).

Figure 10-19 Capillary Flow of the Liquid Epoxy Fully Encapsulates and Stabilizes the Area Between Two Parallel Surfaces The relatively small thermal expansion mismatch between the silicon die (~3 ppm/°C) and the substrate (5 ppm/°C to 17 ppm/°C) is most responsible for solder joint fatigue during thermal cycling. The temperature range of the cycling and the size of the copper pillar, solder bump or ball array and overall die size are the main factors determining the lifetime of the assembly. 10.5 Reflow Soldering Considerations for 3D Components Reflow soldering is commonly done in a convection oven with heated air. SnAgCu (SAC) solder is mostly used which requires high reflow temperature. A profile could be good for melting the bottom solder balls of a PoP device with TMV but not sufficient to melt the top solder balls. Also, the ball alloy can be different on different components. The handheld market uses solder spheres with alternative alloys to the SAC 305 and 405. This is done for increased drop performance. Those alternative alloys have low silver content which raises the melting temperature of the spheres. The reflow temperature needs to be applied to all levels of assembled components (see Figure 10-20).

Figure 10-20 Soldering Material in PoP assembly


It is recommended to attach a thermocouple to each solder joint interface when dealing with 3D assembly to ensure minimum peak reflow temperature is ~ 20 ⁰C above the liquidus of the solder alloy used. 10.6 3D Component Inspection Techniques Nondestructive inspection is done by X-ray. Most SMT houses use 2D X-ray for BGA inspection. PoP packages have at least two layers of packages. It is a challenge to identify bridges and open joints since the balls are overlapped or mixed in the 2D view. Laminography X-ray is recommended for PoP where the top and the bottom can be inspected separately. When a SiP package is mounted on a board, inspection with 2D X-ray becomes very difficult. It will be hard to distinguish between parts on the boards and parts inside the SiP. Figure 10-21 shows an image of a PoP package where the memory balls (top package) are overlapping the bottom package balls. It is very difficult to identify bridges or other defects in this 2D view.

Figure 10-21 PoP Package With Overlapping Memory Balls Figure 10-22 shows the same package viewed with laminography X-ray. The top and the bottom packages view are separated, so it is easy to identify bridging and to see voids or other defects.

Figure 10-22 PoP Package With Overlapping Memory Balls Viewed With Laminography X-Ray


3D laminography provides a high-resolution nondestructive 3D imaging of a sample. It utilizes a variable objective lens for magnification flexibility for detecting defects such as head and pillow (see Figure 10-23) and nonwet opens, but the disadvantage of this technology is the time it takes to scan and construct the image.

Figure 10-23 Head on Pillow 3D Image A common inspection method is to use 2D X-ray that can tilt the X-ray source to produce a 3D view and detect head on pillow defects and bridging (see Figure 10-24).

Figure 10-24 2D X-Ray View of TMI PoP With HoP Defect on the Memory 10.7 Board-Level Rework Rework of 3D Components at the board level is typically handled like any other component on a PCBA once the 3D package has been installed. Any necessary rework can be accomplished by simply utilizing the various methods detailed in IPC-7711/7721. The reason for this is the resulting 3D package, in most all scenarios, will be very similar to a standard BGA, bottom termination component (BTC) or land grid array (LGA) package. Rework methods for each of these types of packages are detailed in IPC 7711/7721. For a 3D component to be successfully used in standard assembly and rework environments, the unique detail of the internal construction of the 3D component should not dictate specialized rework methodologies at the next higher board level assembly. If for some reason specific internal construction did dictate specialized processing or handling, those requirements should be clearly stated in the part data documentation.


In the event a 3D package is not encapsulated (enclosed in a final plastic or ceramic package) similar to any other traditional surface mount technology (SMT) such as BGA, BTC or LGA but rather is in a hybrid multimodule form, then specialized handling may be necessary. Robotic grippers may be required to remove the component and certainly would be required to replace such a nontraditional construction. Most offline semiautomated rework stations employ some type of vacuum nozzle system which is utilized to remove and then pick and place the new replacement part. Without a finished enclosed plastic or ceramic package, the use of vacuum nozzle systems is not possible. This standard does not address rework of 3D packaging internal to the package itself. This type of activity would typically be performed by the original component designer and manufacturer. Additionally, any internal modification of a specific 3D package at the next higher assembly level would most certainly void any warranty offered by the original designer and manufacturer. 3D components can include a variety of highly complex and specialized advanced construction techniques such as TSV connectivity and complex silicon oxide layer-to-layer bonding which are beyond the scope of this document. Some of the primary methods for performing board-level rework of 3D packages are discussed in more detail in the following sections. Manual rework or rework by hand utilizing a hot-air pencil or similar device is not recommended for packages of this nature due to the complexity involved. Factors that exclude manual rework for these types of packages are the inability to apply uniform heating and control the rate of heating as well as the inability to align the new replacement package on a blind placement due to hidden solder connections under the package. 10.7.1 Rework with Convection Reflow Soldering Convection rework achieves solder reflow by heating the surrounding fluid or air to transfer heat to the target device and intended area. Convection heating techniques are used extensively with semiautomated rework stations largely due to the precise thermal control they provide, including the ability to be thermally profiled. Bottom- and top-side preheat are always recommended with any type of rework operation to avoid thermal shock and subsequent damage to the component and/or substrate. One downside to the convection heating approach is the necessity to utilize custom nozzles to direct the flow of heat around and under the subject component. This often requires forethought in the design for manufacturability (DFM) area where clearance and keep-out zones are maintained in the event rework is required. These semiautomated systems typically utilize a vacuum nozzle system to pick and place components along with either a semiautomated or fully automated vision-alignment system. 10.7.2 Rework With Infrared (IR) Reflow Soldering Infrared (IR) systems were once utilized extensively across the electronics assembly industry, and they still are in some areas. These are particularly efficient heating systems generally operating in the range of 70 % efficiency or better. However, IR systems are notorious for yielding nonuniform heating, producing potential shading affects and can be sensitive to color. These concerns may make 3D component rework with IR challenging. Bottom- and top-side preheat are always recommended with any type of rework operation to avoid thermal shock and subsequent damage to the component and/or substrate. 10.7.3 Rework With Laser Soldering


Laser soldering involves precisely locating energy (heat) to a target location or solder joint. One advantage of a laser soldering system is it doesn’t require customized nozzles (as in convection heating) to direct the flow of heat around the desired target. Another advantage for laser-based soldering is the solder to be reflowed is in the line of sight of the laser; thereby, directing most of the energy directly to the solder to be reflowed and not into the component or substrate, subsequently minimizing the risk of thermal shock to the device or the substrate. However, because most 3D components come in some variation of BGA, BTC or LGA and inherently utilize hidden solder connections, laser soldering will likely prove to be difficult for these types of packages. 10.8 Underfill Underfill is widely used to improve reliability of packages mounted onto organic and ceramic-based substrates. Solder joint fatigue and mechanical shock often caused failures in these assemblies. Inserting a curable liquid epoxy resin between the die and substrate and host board can dramatically improve assembly reliability by distributing CTE mismatch or mechanical shock caused stress over the entire area of the component rather than the solder joints. 10.8.1 Package-to-Board Reinforcement Material coverage will be dictated by the specific mechanical enhancement goals. Figure 10-25 (from J-STD-030) illustrates three common board-level underfill coverage variations.

Figure 10-25 Package-to-Board Reinforcement Source: J-STD-030 Example ‘A’ represents a capillary flow underfill process where material is dispensed at the components’ edge, fully filling the space between the bottom surface of the component and the mounting surface of the host board. Example ‘B’ illustrates corner-applied underfill material to overcome package warping during thermal excursions and mechanical shock. Example ‘C’ is typical for the no-flow, fluxing underfill that provides localized reinforcement of the solder ball-to-board interface. 10.9 Material Selection and Application When determining the appropriate underfill material and methodology for package and board level assembly, material coverage type as well as appropriate material properties should be considered. The following describes traditional types of underfill materials currently available in the market.


10.9.1 Capillary Flow Underfill (CUF) The material developed for underfilling semiconductor die is formulated to flow by capillary action into the gap between the die element with raised contact features and the interposer or PCB substrates surface (Figure 10-26).

Figure 10-26 Edge Dispensing of Underfill Material (Figure source: Henkel AG) A wide range of low-modulus capillary flow underfill material is available for flip-chip applications. The term ‘modulus’ defines the mechanical property of linear elastic solid materials measured in Pascal units (Pa) of pressure or stress. For example, underfill material required to flow into very narrow spaces would likely be very low viscosity (in the range of 10 Pa to 50 Pa). For larger die having Cu-pillar or Pb-free solder bump or ball contacts, a 30 Pa to 55 Pa viscosity may be considered. 10.9.2 No-Flow/Fluxing Underfill No-flow underfill contains fluxing material to promote solder ‘wetting’. The material is generally printed or dispensed onto contact sites on the interposer or PCB substrate before placing the flip-chip die (Figure 10-17, example ‘C’). The flip-chip component is then placed onto the dispensed underfill. The downward force of the placement process displaces the flux laden underfill material to allow the flip-chip solder alloy contacts to physically meet the land pattern features on the interposer or PCB substrate. The assembly is then reflowed to complete the contact to land pattern joining while simultaneously curing the underfill material. The cured material forms a stress absorbing compliant matrix that distributes the stress imposed by the CTE mismatch between the die and substrate. The matrix provides enhanced environmental protection and shock resistance. 10.9.3 Removable/Reworkable Underfill Removable and reworkable underfill formulations have been developed that enable removal of array configured devices without damaging the mounting surfaces. Manufacturers of these materials state that the user simply heats the interposer or PCB substrate to 180 °C to 220 °C to soften the underfill encapsulant. Once the temperature is stable, the material can be cut or scraped away. To remove the component, the solder joints’ temperature must be elevated above liquidus. 10.9.4 Corner Bonding/Glue Bonding Capillary flow underfill processing provides the most reliable solution to improving mechanical reliability; however, capillary underfill requires specialized dispensing systems, material flow time


and thermal curing procedures. Corner bonding, on the other hand, provides an alternate approach to improving mechanical reinforcement. Small amounts of underfill material are dispensed at the four corners of the die after solder paste print but before placement (Figure 10-17, example B). During the reflow solder process, the underfill simultaneously cures, providing mechanical coupling between all four corners of the flip-chip die and the PCB interposer. 10.9.5 Molded Underfill (MUF) Underfill and die encapsulation for package-level applications is a single-step process. Simultaneously injecting underfill and mold material for high-volume semiconductor packaging has proved to be simpler and faster than the two-stage underfill/mold process traditionally employed. The illustration in Figure 10-27 compares the physical differences between the two process variations.

Figure 10-27 Comparing Two-Step Underfill Plus Mold Process (A) to the One-Step Molded Underfill Packaged Die (B) The mold material used for the MUF process relies on a polymer composite with a high content of very fine filler particles. Higher filler distribution in the mold compound improves the materials’ CTE, improves flow characteristics and minimizes voiding under the die. MUF is commonly performed in a strip format using a batch vacuum-enhanced mold process to promote a high throughput rate and further eliminate voiding concerns. 10.9.6 Vacuum Underfill (VUF) Vacuum injection systems have been developed to furnish void-free underfill processing. The system uses a two-head injection that can process multiple-die strip carriers at twice the unit-per-hour throughput than non-vacuum processes. The vacuum underfill (VUF) process applies a vacuum to one side of the multiple-die strip, while material is injected between die and substrate surfaces. The injected material moves through the contact array to create a complete, void-free bond between the die element’s bottom surface and interposer substrate surface. Because the unit can inject higher viscosity underfill materials, it can be used on larger die applications to help avoid CTE concerns associated with traditional packaging. 10.9.7 Wafer-Applied Underfill Prior to coating the wafer surface with liquid the epoxy-based fluxing underfill material, the individual die elements on the wafer must be furnished with some form of raised contact feature (e.g., solder-capped Cu pillar, solder alloy bump or ball). Before applying the underfill coating, a fluxing material must be deposited onto each contact feature. The material must be designed specifically to provide fluxing action between the die contact features and the interposer land pattern metallization. The flux material can be either stencil printed or dispensed onto each contact to a thickness ranging between 10 μm and 25 μm and dried to stabilize the coating. The fluxing underfill is finally applied to the wafer’s surface using a spray spin-coat process and partially cured to a b-stage. Following die singulation, the components are ready for direct placement onto the interposer or PCB substrate. The b-stage condition of the underfill compound is formulated to retain position of the placed die element during reflow solder processing.


10.9.8 Underfill Inspection Voids or air gaps in underfill are a common problem across underfill applications, from the smallest to the largest die. The consequences of having voids in underfilled parts depend on the package design and use model. Voids typically result in a loss of reliability. Ultrasonic acoustic imaging is a powerful tool. It allows the user to detect voids in the underfill material on the actual production part before or after cure. The size of the void to be detected can be limited depending on the package and equipment used, so there is a need to check with the equipment makers to understand what size void can be detected. These tools are also useful in reliability testing to detect delaminating and interconnect failures. Figure 10-28 shows an image of a void in an underfilled package taken with an acoustic microscope.

Figure 10-28 Void in Underfill Under Array-Configured Flip-Chip Die (Figure source: Sonoscan) 10.9.8.1 Causes of Voids There are several potential root causes of voids. Describing them and their root causes helps devise tests to troubleshoot them. Some causes include:

• Flow pattern voids. There are several subcategories here, but all of these voids occur during the time the material is flowing under the die or package. The leading edge of the wave front traps a pocket of air.

• Moisture voids. This type of void occurs during curing, when moisture from the substrate outgases. This commonly occurs in organic substrates.

• Voids caused by bubbles in the fluid. This is rare in fluids that materials suppliers packaged, as most suppliers are careful about packaging materials air free. However, mishandling the fluid or repackaging after receipt from the suppler can introduce bubbles. In some cases, suppliers provide samples or experimental fluids that may not be properly degassed. If not configured properly, some automated dispensing equipment can also induce bubbles in the fluid path during dispense.


• Contamination voids. Contamination of excess flux or other sources of contamination can occur in a variety of ways.

10.9.8.2 Void Characteristics Void characteristics can help match them up with their root causes. These include:

• Shape – Are the voids round or some other shape?

• Size – Voids are usually described as the area they cover in the plane of the die.

• Frequency – Do you get on average one void per 10 parts, or 10 voids per part? Do voids occur during specific times, all the time, or randomly?

• Location – Do the voids appear in one place of the die or randomly? Do they appear attached to interconnect bumps? What is the relationship of the void to the dispense pattern?

10.9.8.3 Test Strategies The first step in evaluating void formation is to determine if the voids occur before or after curing. This can be helpful in eliminating some root causes. If the voids are not present after dispensing but are present after curing, flow pattern voids, or voids caused by bubbles in the fluid, can be eliminated as a root cause. At this point, it would be good to look for moisture problems, contamination problems, some source of outgassing during cure, or problems with cure profiles. Most underfill materials are designed to shrink during cure to create compressive stress on the interconnect bumps and thus improve reliability. This shrinking can give any outgassing source the ability to create a void. If the voids are present with the same characteristics before and after cure, it is a good indication that some flow pattern during the underfill process caused the void. If the number of voids changes after cure, there could be more than one root cause. In some cases, contamination can cause two different types of voids; they can create an obstruction during flow, then outgas during cure. 10.9.8.4 Flow-Pattern Voids Two or more flow fronts meeting to trap a pocket of air cause flow-pattern voids. One cause of this can be the dispense pattern. Dispensing on multiple sides of a BGA or die can improve the speed of the flow, but it increases the probability of trapping a void. Experimentation with various dispense patterns or parts with a quartz die or transparent substrate is the most direct method of understanding how the voids are formed and how to eliminate them. The use of underfill materials with different die colors for various dispense passes can be a good tool to visualize flow. 10.9.8.5 Moisture Voids Moisture in the package substrate can outgas during cure, creating a void during the cure process. These voids are often random in placement and can have finger- or snake-like shapes. They usually are seen in packages using organic substrates. To test if voids are caused by moisture, one can prebake the parts for several hours at temperatures above 100 °C, then dispense immediately on the parts. Once it has been established that moisture is the root cause, further testing to establish optimal pre-bake times, temperatures, and storage protocols can be designed. A good metric for water content is to track weight gain of a part with a precision analytic balance.


10.9.8.6 Effect of Contamination Some flux contamination issues can be remedied with a prebake procedure and also act like moisture-induced problems. It is easy to test for the difference. Moisture-induced problems will recur if the part is exposed to humidity; flux contamination problems will not. Contamination issues caused by excess flux often create irregular or random flow variations, particularly at the interconnect bumps. If the voids that are occurring during flow show this characteristic, it would be prudent to investigate cleaning results or sources of contamination. In some cases, flux contamination can show up after cure in a series of small bubbles on the side of the die opposite the dispense side because fluid flow can carry the flux residue to the far side of the die.

11 TESTING AND PRODUCT VERIFICATION

11.1 Establishing Test Requirements Testing 3D die-stacked packages with mixed function die has been a serious defector because of the unique testing requirements of dissimilar functions. Combining logic functions with memory in a single package outline, for example, has always proven difficult. This is because testing and burn-in requirements for memory devices are very different than those required for logic functions. Additionally, when companies stack several functionally different die elements within a single package outline (die stack), the differences in die sizes and the die quality can adversely affect package assembly yields.

PoP products, on the other hand, enable suppliers to functionally test each section before joining. Testing before joining has proven far more practical for both supplier and user. This is because sections can be supplied as separate units and joined together at the board-level assembly stage or furnished as a single package-level product which has been thoroughly tested and certified to be ready for PCB mounting.

11.2 Assembly Process Qualification Users of over-molded, organic-based semiconductor packages have experienced a number of challenges. Both single- and multi-level package families, when furnished on an organic substrate, are more sensitive to the effects of the thermal profile developed for reflow solder attachment. Users have experienced excessive warping of the package substrate, which typically occurs during the reflow process heating stage. As the substrate temperature exceeds the point of glass transition, the rigid resin-based laminate relaxes somewhat, allowing the material to reach a condition that can result in deformation. The deformation is most prominent at the outer edge area and corners of the substrate sections. When the warping results in the substrate deforming away from the circuit board surface, the solder joints can elongate or separate from the opposing surface. When the substrate warps downward at the edge or corner areas, the contacts will compress, often forming a common connection or short between adjacent contact sites. Both of these conditions can be avoided with refinement of the reflow solder profile.

The temperature level and timing are dependent on individual assembly complexity and the specific reflow oven. Many have found, however, that when the materials are exposed to a gradual thermal rise through the solder liquidus threshold and peak temperature, substrate warping is minimal and self-correcting.


11.2.1 Package-Level Stress Test The purpose of establishing a controlled stress test procedure for the 2.5D and 3D packaged semiconductor(s) is to provide confidence that the design and assembly processes will furnish a product that is capable of meeting its intended use environment. To ensure confidence suppliers of the finished 2.5D and 3D semiconductor package shall implement standardized test methods and reporting procedures. Test methods specified by the user or selected by agreement between user and supplier, will be enable evaluation of the performance and reliability of the finished semiconductor package. In addition, the testing provides an approximate means of relating the results from these performance tests to predict the reliability and life cycle of the product for the intended use environments and conditions. One or more of the following test methods may be applied to qualify semiconductor packages:

• JESD22-A100D, Cycled Temperature Humidity Bias Life Test • JESD-A102E, Accelerated Moisture Resistance - Unbiased Autoclave • JESD22-A104B, Temperature Cycling • JESD22-A106B, Thermal Shock • JESD22-A108D, Temperature, Bias, and Operating Life • JESD22-A110E, Highly Accelerated Temperature and Humidity Stress Test (Hast) • JES22-B103B, Vibration, Variable Frequency • JESD-B104C, Mechanical Shock • JESD22-B110B, Mechanical Shock – Component and Subassembly • JEP-122, Failure Mechanisms and Models for Semiconductor Devices • JEP-131, Potential Failure Mode and Effects Analysis (FMEA) • JEP-143, Solid State Reliability Assessment Qualification Methodologies • JEP-158, 3D Chip Stack With Through-Silicon Vias (TSVS): Identifying, Evaluating

and Understanding Reliability Interactions • J-STD-020, Moisture-Induced Stress Sensitivity for Classification of Plastic Integrated

Circuit Surface Mount Devices • J-STD-035, Joint IPC/JEDEC Standard for Acoustic Microscopy for Non-hermetic

Encapsulated Electronic Components • IPC‐9701, Performance Test Methods and Qualification Requirements for Surface

Mount Solder Attachments • IPC/JEDEC‐9702, Monotonic Bend Characterization of Board‐Level Interconnects • IPC-9703, Mechanical Shock Test Guidelines for Solder Joint Reliability • IPC-9704, Printed Circuit Assembly Strain Gage Test Guideline

Resulting data evolving from stress testing will permit the analytical prediction of the package reliability based on a generic database and technical understanding.

The user or by user/supplier agreement team shall defined the quality policy and objectives for establishing a quality management system to ensure that the quality policy and quality objectives are understood, implemented and maintained. A quality manual is prepared with procedures, specifications, regulations, rules and detailed work instructions (Figure 11-1). Operators must be trained and keep detailed records of duties carried out according to the prescribed methods based on the latest documents to ensure that the constructed quality system is implemented in the prescribed manner.


Figure 11-1 Quality Document System (example source: ISSI) The quality system must be periodically checked and evaluated through the internal quality audits as well as external audits by the user/customer or certified agencies to provide opportunities for continuous improvement. 11.3 Substrate Test Coupons The quality level for organic substrates developed for multiple die, 2.5D and 3D package applications shall be IPC Class 3 or better. Typically, one or two panels or arrays are submitted for testing, along with the associated coupons that are furnished on the panel surface. The coupons are useful tools for the supplier to perform their own in-house lot acceptance testing, as the coupons are representative of the panel. When submitting samples for testing, sending a fabrication drawing with the samples is equally important because many requirements within the IPC documents are “as specified.” Without knowing the requirements, the test laboratory cannot always determine if it is acceptable versus nonconforming. By submitting the drawing, it will save the suppliers and the users of the product the time and effort of combing through the final report to find these items later. The test coupons should reflect the specific substrate characteristics. When coupons are used to establish process control parameters, they shall consistently use a single hole size or land configuration that will reflect the process. Coupon examples are furnished in the IPC-2221, Generic Standard on Printed Board Design. Coupons have been developed to measure and assess the following:

• Plating thickness and bond strength • Thermal stress on inner layer interconnect integrity • Solder resist testing • Conductor and land peel strength • Surface insulation resistance • Moisture and insulation resistance • Layer registration targets

The document furnishes detailed criteria for selecting appropriate coupon design and recommend placement locations.


12 RELIABILITY 3D components, which include SoCs, interposer, TSVs as well as SiP and PoP designs, are becoming more complex in package design structure and materials characteristic. 3D components consist of many features such as micro bumps, thinned die, TSV, interposers, copper, gold and aluminum wire-bond processing. The finished package can include different materials with diverse properties and varying CTE that can be difficult to model and to predict reliability and lifecycle. 12.1 Reliability Considerations Semiconductor manufacturers are adept at specifying their devices ’thermal performance’, but users often require more life cycle information. They expect to understand the components performance characteristics when the device is used as intended, that is, mounted to a board and possibly attached to a heat spreader or other forms of thermal control. There is no single set of test conditions for a universally applicable characterization. In order to provide some characterization, manufacturers specify thermal behavior for worst case mounting conditions or conditions typical of the application. Users must relate the test data and specifications to their particular thermal environment. The user must be cognizant of the differences between electrical and thermal domains. Considering how the electrical and thermal domains differ is a good way to avoid some common misconceptions and misunderstandings. One key difference between the domains is that in the electrical domain the current is constrained to flow within specific circuit elements, whereas in the thermal domain heat flow is more diffuse, emanating from the heat source in three dimensions by any or all of the three thermal transport mechanisms. In electrical circuit analysis current is limited to defined current paths and that allows us to use combined circuit elements, such as resistors, capacitors, etc. But in the thermal domain the thermal path is not so constrained, so using combined elements is not as appropriate. Even in relatively simple mechanical systems, defining combined thermal components is often an exercise in estimation, intuition and tradeoffs. Users may want to use combined elements to model their thermal systems, but they must remember that to do so many simplifying assumptions are often made. A second major difference is that coupling between elements is usually a more prominent behavior in the thermal domain. Isolating devices in electrical circuits is usually easier than isolating elements in thermal networks. Therefore, good thermal models usually employ thermal coupling elements, while many electrical circuits do not require them. There are quite a few commercially available thermal modeling software packages available. Whether selecting a new commercial package or using one that your company already has developed, it will be important to understand how they differ. Some of the differentiating features are:

• Cost, including hardware and maintenance fees • Simulation speed • Training required for competency • Ability to model responses to time varying power waveforms • Ability to import files from other CAD packages • Method of managing boundary conditions • Ability to use a multi-level nested mesh • Ability to link thermal models to models in other domains (e.g., electrical models) • Ability to view and export a simulation’s results • Customer support, including technical literature • Numerical method used to solve the governing mathematical equations


The modeling software selected should have the ability to model all modes of heat transfer, which for convection requires the ability to model fluid flow. The product selected should also include a software library that contains common thermal transfer elements, such as heat spreaders, enclosures, PCBs, etc. 12.2 Design for Reliability (DfR) Principles Reliability is the ability of a product to deliver designated functions under given conditions, for a specified period of time and within an acceptable level of confidence. The reliability of 2.5D and 3D component assemblies requires a definitive design effort to be carried out during the developmental phase of the product to meet reliability requirements. Short-term reliability is threatened by ‘early-life failures’ generally attributed to insufficient production quality. These ‘infant mortalities’ can be reduced by appropriate screening techniques prior to shipping, but they can’t be eliminated. Longer-term failures are the result of premature wear-out damage caused by inadequate design of any elements within the package. Reliability qualification requirements are given in the IPC-9700 series together with well-defined test methodologies. 12.3 End-Use Relationship The intended end use of any product ultimately determines what level of reliability is required. J-STD-001 has established three general end-product classes to reflect differences in producibility, complexity, functional performance requirements and verification (inspection/test) frequency. It should be recognized that there may be overlaps of equipment between these classes. Ultimately the end user is responsible for defining the product class and this information should be stated on the procurement documentation for the hardware. With this said, each of these classes will have different storage and operational requirements and most likely will have different reliability requirements. The following is a general explanation of these three classes of hardware, (see J-STD-001 for details concerning the specific requirements for each of these classes).

• IPC CLASS 1, General Electronic Products – Includes products suitable for applications where the major requirement is function of the completed assembly.

• IPC CLASS 2, Dedicated Service Electronic Products – Includes products where continued performance and extended life is required and for which uninterrupted service is desired, but not critical. Typically, the end-use environment would not cause failures.

• IPC CLASS 3, High Performance Electronic Products – Includes products where continued high performance or performance-on-demand is critical, equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life support or other critical systems.

Each of these three classes most likely will have different reliability requirements as dictated by the end user and the intended use environment (see Table 12-1).


Table 12-1 Accelerated Testing for End-Use Environments (Table source: IPC-7092)

12.4 Effects of Lead-Free Materials and Pure Tin Finishes on Reliability In traditional SMT electronic assembly, the use of a lead-free or pure tin finish materials would typically require some level of ‘‘lead free/tin whisker mitigation plan’’ depending on the hardware class. With EC Technology, this concern is typically, although not always, eliminated due to the fact that the metallic surfaces of the components, vias, terminations, wire bonds etc., are fully encapsulated with some type of fill material, thereby eliminating the ability of a tin whisker to propagate and create a short. Depending on the particular class of hardware and the end-user requirements, this may or may not be necessary. Most Class 3 hardware such as military hardware, some degree of mitigation will be required and this mitigation is directly related to end-product reliability. The Government Electronics and Information Technology Association (GEIA) Standards address Lead Free Risk Mitigation and Tin


Whisker Mitigation methodologies. Two of these standards are GEIA-STD-0005-1 and GEIA-STD-0005-2. If the EC Technology makes use of some sort of free volume cavity airspace or non-filled volume, then the pure tin/tin whisker concern will need to be addressed as discussed above. Additionally, depending on the type of PCB cavity fill material utilized, the tin whisker concern could still exist if a ‘‘soft’’ fill material is utilized. Tin whiskers have shown that they can easily penetrate and propagate through silicon, urethanes and acrylic coatings. So the fill material that is utilized and how thick the spaces are (metal to metal) in the fill material should be considered in order to ensure that acceptable reliability could be achieved due to potential future tin whisker growth. 12.5 Validation, Qualification and Accelerated Aging Test for Reliability Performance test methods and qualification requirements are specified in IPC-9701 for traditional SMT assemblies. IPC-9701 also includes guidelines for lead-free solder joint reliability testing. However, in the current absence of generally useful lead-free reliability acceleration models and because there are multiple lead-free alloys in use, there are no qualification requirements for a lead-free solder joint. EC technology is similar to lead-free technology in the sense that little to no data exist, and the pitfalls and best practices are still being determined by industry. Any work concerning this technology has been very limited, and a lot of information has not been made available or shared across the industry. Generally speaking, validation and qualification tests should follow the guidelines given in IPC-SM-785. However, for large components with significant heat dissipation, components of asymmetric construction and CTE mismatches, temperature cycling tests may be inadequate to provide the required information. Full functional cycling, including external temperature exposure, internal power cycling and some level of sequential static humidity soaking, may be necessary to fully evaluate the reliability of EC hardware. Additionally, for EC technology, board flexure and bend tests may be required since the components are now mounted internal to the board and the solder connections may not be as compliant as necessary to ensure acceptable reliability. For high-reliability military environments, accelerated aging based on sequential life testing using humidity soaks and thermal cycling may be required. Equations such as the Hallberg-Peck equation, the Arrhenius equation and the Coffin-Manson equation can be utilized to determine the level of duration and thermal parameters needed to determine if the hardware will meet its expected life. Generally, validation and qualification tests should follow the guidelines given in IPC-SM-785 and/or IPC-9701. Test conditions and thermal cycle durations furnished in IPC-9701 have been designed to assist manufacturers in establishing reliability criteria for electronic products life cycle (see Table 12-2).


Table 12-2 Temperature Cycling Requirements, Mandated and Preferred Test Parameters within Mandated Conditions (Table source: IPC-7092)

Although accelerated temperature cycling (ATC) is often conducted, for some products, ATC needs to be combined with mechanical shock and/or vibration testing. A single set of ATC test conditions or inadequate ATC test conditions may not provide valid conclusions. Thermal cycling may be required. Equations such as the Hallberg-Peck equation, the Arrhenius equation and the Coffin-Manson equation can be utilized to determine what level of duration and thermal parameters are needed to determine if the hardware will meet its expected life. 12.6 Environmental Testing In defining operating environments, product testing may extend beyond what may be conceived as general use conditions. Electronic products are likely to be subjected to excess physical shock, humidity and operating temperature extremes. Temperature variables can adversely affect the 2.5D and 3D component structure, transferring stress to the components’ terminal interface causing acute damage to devices. Key environmental issues to consider:

• Product must operate reliably while exposed to extremely high and low temperature • Device performance must not be affected by humidity or other atmospheric conditions • Product must withstand physical stresses typical of the product use or application

Component reliability is generally evaluated while mounted onto a test vehicle (TV) representing the end-use product. The test vehicle is typically an organic-based PWB with terminal access to specific signal output for monitoring the test. In regard to preparation, JEDEC Test Method A113 specifies preconditioning of devices before assembly onto the test vehicle as well as reliability testing. The first steps of the procedure are to specify electrical functional tests, followed by visual examination and moisture reduction using a bake-out process. The bake procedure recommends a 24-hour minimum temperature exposure at 125 °C for 24 hours.


IPC-9701 establishes specific test methods to evaluate performance and reliability for board-level electronic assembly. The tests are designed to replicate actual use environments of the electronic assemblies. The reliability of the solder joint attachment of 2.5D and 3D components to the TV circuit board may require moderate to extensive physical stress testing. The stress testing is designed to qualify a product for specific use categories and/or environments by establishing different levels of performance and reliability of the solder attachments. Testing provides confidence that product is capable of meeting its intended goals, and it allows comparison of results from different test programs while permitting the analytical prediction of reliability based on a generic database. During the products use, the solder joints for component attachment can be subjected to a variety of loading conditions that can lead to premature failure:

• Cyclic differential thermal expansion • Vibration (transport) • Mechanical shock (high acceleration)

In developing the thermal stress test (Table 12-3) the IPC working group that developed the IPC-9701 standard focused on two issues: temperature range and thermal cycles. Table 12-3 furnishes typical thermal conditions and cycle parameters representing a number of product categories noted in Table 12-1. The specific temperature range, number of thermal cycles and dwell time at each level is the responsibility of the supplier or by agreement between the supplier and user. Table 12-3 Thermal Stress Test Parameters

Temperature Range Thermal Cycles 0 °C to 100 °C 100 - 25 °C to 100 °C 200 - 40 °C to 125 °C 500 - 55 °C to 125 °C 1000 - 65 °C to 150 °C ≥ 2000

13 DEFECT AND FAILURE ANALYSIS Failure analysis (FA) is the discipline of analyzing data to determine the cause of failure. It is a methodical approach allowing the best opportunity to find the cause(s) of product failure. In FA, the operator will write a report on the findings, along with the summary of results. The benefits of FA are:

• Identify and contain problems quickly • Accelerate new designs to market • Develop in-depth knowledge of products/processes

There are two methods used to identify product failure:

• Destructive failure analysis (DFA)

• Nondestructive failure analysis (NFA) 13.1 Nondestructive Failure Analysis (NFA)


Nondestructive failure analysis (NFA) techniques are commonly used to evaluate the properties of materials, components or systems without causing damage. Because NFA does not permanently alter the article being inspected, it is a highly valuable technique that can save both money and time in product evaluation, troubleshooting and research. The following methodologies may be considered for NFA:

• Electrical test: functional test (FT), modeled fault test (MFT), IDDQ, time domain reflectometer (TDR)

• External optical inspection: optical microscope, confocal laser scanning microscopy (CLSM)

• Internal nondestructive inspection: acoustic microscopy (AM), X-ray, infrared thermography (IRT), infrared (IR) microscopy, magnetic current imaging (MCI)

• Internal optical inspection: optical microscope, total internal reflection microscopy (TIRM) • Electrical probing: Nanoprobing • Chemical analysis

A number of in-process tests are performed on samples to verify manufacturing processes are in control and to quickly detect deficiencies to facilitate corrective action. 13.1.1 Electrical Testing 13.1.1.1 Functional Testing (FT) Functional testing (FT) is typically implemented at the last stage of assembly to ensure final quality control and to confirm the device under test meets its functional specifications. 13.1.1.2 Modeled Fault Testing (MFT) Modeled fault testing (MFT) describes the behavior and assumptions of how elements in a defective circuit behave. The purpose of fault modeling is to model physical defects that appear in the device under maximum stress conditions. 13.1.1.3 IDDQ IDDQ (the IEEE symbol for the quiescent power supply current in a MOS circuit) testing is used for evaluating ICs to detect manufacturing faults. It relies on measuring the supply current (IDD) when the circuit is not switching and inputs are held at static values. 13.1.1.4 Time-Domain Reflectometer (TDR) Time-domain reflectometer (TDR) tests are used to characterize and locate faults or discontinuities in a connector, PCB or any other electrical path between a suspect component and interposer or substrate. 13.2 Internal Nondestructive Inspection As the industry trends toward complex designs, extreme miniaturization and the adoption of novel material sets, product reliability of long-term operations is becoming a major concern. Detecting defects in the electronic assembly without resorting to destructive means, however, will require reliance on a wide number of available methodologies. 13.2.1 Acoustic Microscopy (AM)


Acoustic microscopy (AM) has the ability to create images by generating a pulse of ultrasound, which is focused to a pinpoint spot. Using this acoustic methodology, a broad range of defects can be identified without compromising the physical integrity of a good component. By passing sound waves through samples submerged in a liquid (typically DI water), areas of defects such as cracks, delamination and voiding can be detected (see Figure 13-1). The sound travels at different speeds in different materials. Sound travels faster through solid or denser material, while it is blocked by vacuum or air (voids and delamination). By focusing on different planes, the process allows examination of specific interfaces within a device (e.g., mold compound-to-die, die-to-attach material, attach material-to-package-substrate, etc.).

Figure 13-1 Acoustical Microscopy (AM) Can Identify Voids, Delamination and Cracks (Figure source: Sonoscan) 13.3.2 X-Ray Imaging X-Ray imaging, in particular real-time X-ray, is a nondestructive analysis tool for creating an immediate through-transmission view of a sample. The tool enables users to identify and diagnose varying densities within a sample. X-Ray tools typically include software to enhance image quality when needed and focus on and measure defects discovered within a sample. Advances in X-ray technology have enabled much higher resolution. Where traditional X-Ray tomography relies on a single stage of geometric magnification, more advanced systems have evolved that employ a unique two-stage process based on synchrotron-caliber optics for 3D submicron imaging, optimizing both resolution and contrast. Typical capabilities include, but are not limited to submicron defects, void percentage, solder sphere formation and post-mold wire-sweep inspection. Advances in this technology have enabled much higher resolution. Where traditional X-ray tomography relies on a single stage of geometric magnification, more advanced systems have evolved that employ a unique two-stage process based on synchrotron-caliber optics for 3D submicron imaging, optimizing both resolution and contrast. 13.3.2.1 Example X-Ray Image Solder bridging between solder ball or bump features is usually attributed to a solder paste printing error or solder slump prior to placing the interposer onto the substrate surface. The


example shown in Figure 13-2, viewed from the bottom surface of the 3D packaged semiconductor, clearly shows a solder bridge between contacts.

Figure 13-2 3D Submicron X-Ray Imaging Distinctly Identifying Solder Bridging (Figure source: Invensas) 13.3.3 Infrared (IR) 13.3.3.1 IR Thermography (IRT)/Thermal Imaging All objects emit IR radiation as a function of their temperature. This means all objects emit IR radiation. IR energy is generated by the vibration and rotation of atoms and molecules. The higher the temperature of an object, the more motion there is; therefore, more IR energy will be emitted. The energy source may be attributed to elevated thermal conditions within the substrate or interposer circuit, or it could be the due to defects within the semiconductor(s). IR cameras detect thermal radiation. They do not recognize the actual temperature. Infrared thermography (IRT), thermal imaging and thermal video are examples of infrared imaging science. Thermographic cameras usually detect radiation in the long-infrared range of the electromagnetic spectrum (roughly 9,000 nM to 14,000 nM, or 9 µm to 14 µm), and it produces images of that radiation, called thermograms. Since IR radiation is emitted by all objects with a temperature above absolute zero according to the black-body radiation law, thermography makes it possible to see one's environment with or without visible illumination. The amount of radiation emitted by an object increases with temperature; therefore, thermography allows one to see variations in temperature. When viewed through a thermal imaging camera, warm objects stand out well against cooler backgrounds. 13.3.3.2 Infrared (IR) Microscopy IR microscopy refers to microscopy performed at IR wavelengths. In the typical IR microscopy system configuration, a Fourier transform infrared spectrometer (FTIR) is combined with an optical microscope and an IR detector. The IR detector can be a single-point detector, a linear array or a 2D focal plane array. The FTIR provides the ability to perform chemical analysis via IR spectroscopy, and the microscope and point or array detector enable this chemical analysis to be spatially resolved (i.e., performed at different regions of the sample). As such, the technique is also called IR microspectroscopy. This technique is frequently used for IR chemical imaging, in


which the image contrast is determined by the response of individual sample regions to particular IR wavelengths selected by the user, usually specific IR absorption bands and associated molecular resonances. A key limitation of conventional IR microspectroscopy is that the spatial resolution is diffraction-limited. Specifically, the spatial resolution is limited to a figure related to the wavelength of the light. For practical IR microscopes, the spatial resolution is limited to 1X to3X the wavelength, depending on the specific technique and instrument used. For mid-IR wavelengths, this sets a practical spatial resolution limit of ~3 μm to 30 μm. 13.3.4 Magnetic Current Imaging (MCI) A typical magnetic current imaging (MCI) sensor configuration is sensitive to magnetic fields in the perpendicular z direction (i.e., sensitive to the in-plane x-y current distribution in the device under test). This does not indicate missing vertical information; in the simplest situation, if a current path jumps from one plane to another, getting closer to the sensor in the process, this will be revealed as stronger magnetic field intensity for the section closer to the sensor and also as higher intensity in the current density map. This way, vertical information can be extracted from the current density images. Through the use of a sensitive magnetic sensor, currents in ICs can be imaged via the magnetic fields they produce. Unlike thermal, optical, ion or electron beam techniques, low-frequency magnetic fields are not affected by the materials in the semiconductor or package. These systems measure the magnetic field associated with a flowing current. The closer the sensor is to the current path, the better the resolution. Only shorts can be detected using MCI technology. 13.3.5 Internal Optical Inspection Internal optical inspection, which is commonly known as total internal reflection microscopy (TIRM), is complementary to phase-contrast microscopy. Objects at and near the surface of a semitransparent substrate can be observed by illuminating the sample from within using a polarized laser beam at an angle greater than or equal to the critical angle of the sample material and then by examining the opposite side of the surface using an optical microscope. Although the technique is similar to dark-field microscopy, additional information can be obtained concerning the size and depth of scattering sites on or near the surface. 13.3.6 Electrical Probing- Nanoprobing Nanoprobing is a method of extracting a device’s electrical parameters through the use of nanoscale tungsten wires, which are used primarily in the semiconductor industry. The characterization of individual devices is instrumental to engineers and IC designers during initial product development and debug. It is commonly utilized in device failure analysis laboratories to aid with yield enhancement, quality and reliability issues and customer returns. Commercially available nanoprobing systems are integrated into either a vacuum-based scanning electron microscope (SEM) or atomic force microscope (AFM). Nanoprobing systems that are based on AFM technology are referred to as atomic force nanoprobers (AFPs). FA plays a crucial role in the production of semiconductors and 3D semiconductor packaging. It provides usable process and design feedback on the root cause of any detected failures. The FA engineer may need to probe anything from bond pads to submicron features. For high-volume manufacturing, dedicated probe fixturing and product-specific test software will be utilized. For low-volume applications or products still in development, manual probing with measuring systems may remain a viable option. 13.3.7 Chemical Analysis


Material composition control is critical in maintaining durability and stability for the intended use of the semiconductor package. As these product families have diversified, there has also been a rapid integration of new alloys, coatings, polymers and emerging materials including fiber-reinforced composites and advanced ceramics. Manufacturers are constantly developing lighter, stronger and more heat- and chemical-resistant alloys/materials designed to meet a variety of specific end-environments. Chemical analysis is also valuable for identifying hazardous contaminants that may affect assembly processing or operator safety. Furthermore, devices that will ultimately be implanted into human patients must be free of contaminants and particles so the patient won’t suffer infection or, worse, rejection of the implant. If the manufacturer chooses to develop this capability in-house, there are companies that offer chemical failure analysis services on metals, coatings, encapsulation and other nonmetallic materials. 13.4 Destructive Failure Analysis (DFA) Destructive failure analysis (DFA) processes are utilized to discover electrical and physical evidence contributing to component failure. The intent is to clearly identify the cause of a failure through straightforward but sophisticated analytical measurement systems, benchtop equipment, and a range of other techniques. Using appropriate equipment and work processes, the location of the failure cause is determined, isolated and then physically characterized. Results and conclusions derived from DFA can then be communicated to those supporting the processes in order to implement changes that limit and/or eliminate the cause of failure. 13.4.1 Cross-Sectioning (X-Sec) Cross-sectioning (X-Sec) observation of specimens with a microscope has become widely accepted for investigation into the causes of defects. This method is commonly used in evaluating electronic parts and for uncovering the causes of failures that cannot be accurately determined from external nondestructive test and inspection methods. Cross-sectional observation becomes particularly useful for identifying the points of voiding, cracking or material decomposition. When the cross-sectioned sample is embedded into a resin material (see Figure 13-3) the resulting specimen allows visual examination of the die element, package structure and interconnecting layers. Preparation of cross-sections involves four operations: cutting, grinding, chemical etching and mechanical polishing. Equipment such as a stereoscopic microscope on low-magnification (10 X to 30 X) or SEM methods is commonly employed for physical FA evaluation.

Figure 13-3 Cross-Sectioned Specimen Embedded in Resin (Figure source: ESPEC)


The cross-section of the 3D semiconductor package example furnished in Figure 13-4 illustrates the complexity of high-performance products. While solder defects on the solder-tipped copper micro-bump contacts are rare, bridging between closely spaced solder ball or bump features is common.

Figure 13-4 Die-to-Silicon-to-Substrate Assembly (Figure source: Invensas) 13.4.2 Parallel Lapping (P-lap) Parallel lapping (P-lap), also known as delayering, is a commonly used process in FA, debug and general construction analysis in the production of ICs. In many cases it is necessary to remove layers from the IC for inspection, whether it be electrical testing, deposition uniformity or device integrity investigation. The precise removal of these layers requires accuracy, knowledge of components and materials systems, and equipment capable of implementing precision polishing techniques. P-lap is useful for removing specific device layers when evaluating the design of any device or to locate specific failure mechanisms. Equipment used for specimen preparation must be adaptable to many different materials such as nitrides, oxides, aluminum, copper and low-dielectric-constant materials. Unlike the cross-section process for viewing the component from its edge, P-lap requires horizontal grinding and polishing of the package. The process enables the FA analyst to employ the use of the stereoscopic microscope or SEM to identify any nonconforming anomalies within the package structure. Wet-chemical etching, however, will be required for silicon-level accessibility. 13.4.3 Decapsulation The decapsulation process is the removal of encapsulation material covering the die surface on the packaged part. Opening devices by decapsulation allows inspection of the die, interconnects and other features typically examined during FA. Device FA often relies on the selective etching of polymer encapsulation without compromising the integrity of the wire bonds and device layers. The most common technique used for decapsulation is a wet-chemical process. The encapsulation and mold compound on many products are susceptible to being dissolved by highly concentrated acids. Since the vast majority of semiconductor die are protected by a passivation layer that is relatively impervious to these acids, there is little risk of damaging the device during this process; however, care must be taken with aluminum bond pads not covered by passivation to ensure they do not etch away along with the mold compound. Specialized equipment is available to perform a wet decapsulation with pressurized streams of heated acid that can be directed onto the area of the IC package being examined (see Figure 13-5).


Figure 13-5 Semiconductor Package Decapsulation System (Figure source: Jet Etch) Though wet decapsulation is the most common method for decapsulation, it may not appropriate for all types of semiconductor FA. For example, the acids and solvents can wash away any contaminants on the semiconductor die surface that may have contributed to the component failure. If something in the failure characteristics or device history suggests that contamination might be present, a different decapsulation approach may be considered. For plastic-encapsulated devices, a reactive plasma etching process is commonly employed. The plasma oxidizes the plastic mold compound, turning it into a fine ash that can be easily cleaned away to reveal any defects, contaminants or corrosion remaining on the die surface. 13.5 Optical Inspection 13.5.1 Optical Inspection (Postassembly) Optical inspection is vital to quality control in manufacturing. As miniaturization evolves, particularly in the 3D semiconductor packaging industry, there is a demand for more powerful inspection techniques. Endoscopy, line scanning, laser scanners, optical imaging and 3D microscopes all are powerful tools for examining both geometric and surface characteristics. 13.5.2 Confocal Laser Scanning Microscopy (CLSM/LSCM) Confocal microscopy, most frequently confocal laser scanning microscopy (CLSM), is an optical imaging technique for increasing optical resolution and contrast of a micrograph by means of adding a spatial pinhole placed at the confocal plane of the lens to eliminate out-of-focus light. It enables the reconstruction of 3D structures from the obtained images by collecting sets of images at different depths (a process known as optical sectioning). A conventional microscope sees as far into the specimen as the light can penetrate, while a confocal microscope only sees images one depth level at a time. In effect, the CLSM achieves a controlled and highly limited depth of focus. 13.5.3 Examples of Observed External Inspection Defects 13.5.3.1 Head-on-Pillow Defect


The term head-on-pillow defines an assembly process defect in which the spherical contacts of a BGA or CSP device do not unite with the deposited solder paste on the land during the reflow solder process (see Figure 13-6).

Figure 13-6 Head-on-Pillow Solder Process Defect (Figure source: Alpha-Cookson) 13.5.3.2 Package-on-Package (PoP) Joining Defects Endoscopic optical inspection systems are suited for finding possible defects at area arrays that occur during processing or rework. Only the perimeter contact features will be in view; however, the viewable image will represent the condition of the solder interface in areas within the package parameter. The example shown in Figure 13-7 illustrates a typical solder process defect of array-configured package-on-package (PoP) components.

Figure 13-7 Poor Coalesce Between Sphere and Interposer Land 13.5.3.3 Nonwet Open Joint The term wetting means the solder has become molten at its most ideal liquidus state to enable the component terminals and the substrate land patterns to form an electrical and mechanical bond. When the solder does not reach the enabling temperature, the terminal and land materials will not wet, resulting in an open solder joint. Excessive oxidation on either or both surfaces can


also impact wettability. Figure 13-8 illustrates the nonwet defect attributed to excessive oxidation of the solder sphere contacts on a PoP/BGA component.

Figure 13-8 Nonwetting Defect, Exhibiting the Effect of Excessive Oxidation 13.5.3.4 Bridging on PoP Solder bridging is the unintended connection between solder sphere contacts (see Figure 13-9). It is commonly caused by package warp during solder processing, but excessive solder volume at these locations can contribute to the defect as well.

Figure 13-9 Endoscopy Edge View of Solder Bridge Between BGA Sphere Contacts 13.5.3.5 Solder Ball Oxidation Oxidation of the spherical contacts on BGA- and PoP-configured components continues to be a key concern because it can compromise reflow solder joining process integrity. The condition is commonly attributed to the period of time between stages of assembly processing, and it is accelerated when components are exposed to high-temperature and/or high-humidity storage environments. The example shown in Figure 13-10 is typical of spheres that do not coalesce during the package-to-package joining process.


Figure 13-10 Defect Attributed to Oxide Contamination 13.5.3.6 Insufficient Solder/Flux Inadequate solder paste volume can affect acceptable wetting of the solder sphere during the reflow process. Poor wetting is commonly attributed to the lack of flux activity. Lower activity solder pastes (e.g., ROL0, halide-free, no-clean pastes) tend to acerbate this nonwet defect, especially when joining to interposer surfaces furnished with bare-copper OSP or on NiAu in which the nickel base metal may have experienced oxidation or plating contamination.

Figure 13-11 Comparing Wetting Characteristics of Two Surface Finishes (Figure source: Kester) The test coupons shown in Figure 13-11 represent SAC no-clean paste applied to plated copper on two surfaces. The test coupons were reflowed in air using the manufacturer’s recommended thermal profile. The example on the left shows dewetting, while the example on the right exhibits good wetting. The pooling of solder was due to the base metal being difficult to solder-connect. The molten solder initially spread across the surface, but an inadequate intermetallic bond was formed, resulting in surface tension pulling the solder away from the surface. 13.5.3.7 Incomplete Solder Reflow Solder paste consists of two critical components: metal solder powder and flux. Both play an important role to ensure good solder joint formation during the reflow process. An insufficient reflow temperature will prevent the solder ball, the solder paste or both from reaching liquidus temperature and becoming fully molten to coalesce and form a metallurgically sound solder joint interface.


13.5.3.8 Missing Solder Ball Although rare, array-configured components may reach the assembly area with one or more missing solder ball contacts. This may be due to poor manufacturing inspection procedures at the supplier source or damage that has occurred during testing, packaging or handling. Replacing the missing solder ball will require the technician to locate a source that will furnish a sphere with the same diameter and alloy composition as the original part. Additionally, when attaching the sphere, the same flux material and thermal profile should be applied. 13.5.3.9 Nonuniform or Missing Solder Deposition Uniform solder paste deposition is vital for ensuring reliable joining of BGA and PoP components. The solder paste volume will ultimately define the overall crest height of the molten solder on the PCB land during reflow. A higher crest height of the molten solder paste mass will increase the likelihood it will contact the solder ball. If the solder volume is reduced or not present, the contact sphere cannot make physical contact and coalesce with the PCB land. 13.5.3.10 Voids and Uneven Solder Excessive solder voids can create a reliability issue, especially in applications in which the assembly will be exposed to thermal cycling conditions or flexing during box-builds and in applications in which the end product will be exposed to vibration. Also, excessive voids in the interface can reduce thermal performance and electrical integrity. Smaller voids can impact reliability by changing the crack propagation pattern. Studies have shown that there is no reduction in reliability when overall void volume is ≤ 25 %; however, excessive small voiding on interface surfaces can promote crack propagation.

14 SUPPLIER SELECTION AND QUALIFICATION There are four recommended steps in selection and qualification of a PWBA supplier. These are described in 14.1 through 14.4. 14.1 Factory and Process Audits A first step to selecting a supplier is to have relevant, up-to-date information on existing and new suppliers. The following are recommendations for obtaining these data. Hold a conference call with manufacturing and engineering management to gain an understanding of their product characteristics and the types of equipment and processes used. At this stage, user and supplier should agree on the specific objectives of an audit. Before the visit, send the supplier a questionnaire. The questionnaire should request:

• Detailed list of supplier equipment list • Roster of technical personnel • Vendor’s process control, inspection and quality procedures • Data on yield for other products the supplier is building • Process flow and sequence to assess whether they are compatible with your product • References from current customers and permission to call them about supplier’s quality

and delivery performance Note: If the supplier is not willing to provide this information, you need to assess whether or not to keep them on or add them to your supplier list.


In addition to asking the supplier to provide information, the supplier should also provide information to ensure product meets your quality, reliability, volume and yield requirements. This information should include:

• Information about the product being manufactured • Types of components used in the product • Product volume • Summary of vendor selection and qualification procedures (summarized below plus

additional internal procedure for supplier selection) 14.2 Site Visit Procedure An on-site audit should begin by reviewing the major objectives of the audit with management personnel responsible for the audit. At this point, it is important to fine-tune the objectives of the audit. The audit should include time on the factory tour and one-on-one interviews with key personnel in CAD and circuit design, manufacturing, quality, purchasing, test, customer service and purchasing. These interviews generally take place following the factory tour. 14.3 Design and Process Evaluation During the interviews and factory tour evaluate design (for manufacturability), process documents and quality data. Critically examine all major process steps such as:

• Adhesive dispensing • Paste printing • Pick and place • Reflow and wave soldering • Inspection and repair • Any other issues of concern

The auditor should review incoming material (e.g., PCB issues, adhesive, paste, board and component solderability, etc.) and quality control practices and investigate the supplier’s operator and engineering training material and practices. Spend some time unaccompanied on the factory floor to talk openly and freely with operators and inspectors, taking extreme care to ensure production is not disturbed. 14.4 Observations and Recommendations Prepare a brief presentation on the findings of the audit for the supplier management and invited personnel (generally those who were interviewed). The presentation should be essentially an interactive discussion and focus on two major areas. First it should detail findings on various areas of the investigation. It should essentially represent a bill of health for the facility, with strengths and weaknesses. The second part of the presentation should make specific recommendations for improvement. The key objectives of the recommendations are to achieve high quality, reduce rework and lower product cost. The recommendations should include step-by-step action items and a realistic time frame for the supplier to accomplish the resolution of issues discussed during the presentation. If the supplier addresses those issues, the next step is to send sample products for the supplier to build, with clearly specified quality, reliability and yield requirements. If the first batch of sample boards meets the requirements, build a few more batches of products over the next few months. Look for a trend line in quality and yield improvement. If the supplier meets all the requirements, negotiate pricing and contractual requirements for approving the supplier for a long-term partnership relationship.


15 GLOSSARY OF ACRONYMS AOI Automated optical inspection BGA Ball grid array BVA Bond via array CSP Chip scale package CTE Coefficient of thermal expansion CuPi Copper pillar interconnect DBI Direct-bond interconnect DCA Direct chip attachment DRAM Dynamic random-access memory FBGA Fine-pitch ball grid array IC Integrated circuit KGD Known good die LCD Liquid crystal displays MCM Multichip module MEMS Microelectromechanical systems PCQR Product compliance and quality review PoP Package on package PoPi Package on package interposer PTH Plated-through hole RF Radio frequency RDL Redistribution Layer SiP System-in-package SIR Surface insulation resistance SMT Surface mount technology SoC System on chip SOH Standoff height SPC Statistical process control TCR Thermocompression reflow TGV Through-glass Via TMI Through-mold interconnect TMV Through-mold via TSOP Thin small outline package TSV Through-Silicon via UBM Under-bump metallization WLBA Wafer-level BGA

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