Date: 5/Dec/16

Revision: 1.0

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OpenLDI TX/RX Built-In Self Test (BIST) Design Example on Cyclone V User Guide

Table of Contents1.0 Introduction....................................................................................................................................3

2.0 Requirements.................................................................................................................................3

3.0 Theory of Operation.......................................................................................................................4

4.0 How to Reconstruct the Design......................................................................................................5

Design Example Overview..................................................................................................5

Creating the Qsys System..................................................................................................6

5.0 System Console Graphic User Interface (GUI)..............................................................................12

6.0 Results..........................................................................................................................................14

7.0 Conclusion....................................................................................................................................14

8.0 Revision History............................................................................................................................15

9.0 References....................................................................................................................................15

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Introduction

The objective of this design example is to implement a simple Built-In Self Test (BIST) of an Open LVDS Display Interface (OLDI). The LVDS Serializer (SER) and LVDS Deserializer (DES) IP blocks are implemented with the ALTLVDS MegaFunction and are connected together with a simple external loopback HSMC card. A PRBS pattern generator sends data to the SER, which is looped back to the DES via the LVDS interface and sent to the PRBS Checker block.

The IP is available for download in the Intel FPGA Design Store.

Requirements

Software: Quartus® II Version: 15.1

Hardware: Cyclone V GT FPGA Development Kit https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html

HSMC Loopback Connectorhttp://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=495

The HSMC Loopback Connector is connected to the DEV KIT as shown in Figure 1.

Figure 1 – Hardware configuration (CV GT) & HSMC Loopback Card

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Theory of Operation

Figure 3: Block diagram of design example

To test the reliability of the OpenLDI TX/RX, PRBS generator is used to generate a test pattern that feeds into the OpenLDI_TX IP. The IP will map the data into the OpenLDI JEIDA 24bpp standard (See Figure 3). The 24-bits represent 8 bits per sub pixel for RGB888 color space. The 4 control bits in this example design are tied to “0” and “1”. It will then be transmitted through a serializer over 4 channels and looped back into the OpenLDI_RX IP. The IP will deserialize and re-map the data to its respective components. PRBS checker is used to check if the PRBS pattern transmitted is correctly received. A system console GUI is used to count the number of bits that correctly and flag an error if bit error is received.

Figure 2: OpenLDI JEIDA 24bpp data mapping and timing

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How to Reconstruct the Design

Design Example Overview

Figure 3: LVDS OpenLDI BIST Block Diagram

Creating the Qsys System

For PRBS Data Pattern Generator, 32 bit is selected. Since the OpenLDI IP input is 24 bit, a Data Format Adapter is required to convert the 32 bit to 24 bit. Since the Data Format Adapter converts 8 bits per symbol, you can also choose any value that is the multiple of 8. More about Data Format Adapter in the following pages.

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Figure 4: Avalon Data Pattern Generator Settings

In this design example only a 24-bit data pattern is required to represent the RGB bits. Thus, Avalon-ST Data Format Adapter is inserted. It converts the 32-bit data pattern to a 24-bit data pattern.

Figure 5: Avalon-ST Data Format Adapter Settings

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The Avalon-ST Data format adapter outputs 24-bit data, and also an out_valid and out_ready signal. Since the OpenLDI_TX IP input has only 24-bit (RGB) data, and valid signal input, the out_ready signal is not used.

Figure 6: Output Signals from Avalon-ST Data Format Adapter

Figure 7: Input Signals for the OpenLDI TX

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To connect Data Format Adapter to the OpenLDI_TX IP blocks, an Avalon-ST Timing Adapter is used. On the “Output Interface Parameters” uncheck the “Support Backpressure with the ready signal” box as shown in figure 7.

Figure 8: Avalon-ST Timing Adapter Settings

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The OpenLDI_TX IP block maps the signals according to the OpenLDI specification and transmits them over 4 serialized LVDS channels using a 7:1 scheme. 24 bits are RGB data. The other 4 bits are control bits which in this design example, we have pulled high/low accordingly. In this design example, two control signals are tied LOW, and two are tied to HIGH. The 24 data bits representing RGB are sent to the 24-bit PRBS checker input.

Figure 9: OpenLDI_TX (SER) Settings

Figure 10: OpenLDI Color Mapping for 24 bits per pixel (JEIDA 24bpp)

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On the receiver’s end, the OpenLDI_RX (DES) IP will deserialize the 4 LVDS channels and re-map the parallel data. Different FPGA devices may have a different default bitslip. For Cyclone V, it is typically set to 2. With this setting the correct word boundary alignment is obtained from the beginning without needing any special training patterns.

Figure 10: OpenLDI_RX (DES) Settings

User Push Button and LEDs

The design is also connected to user push button (USER_PB0) to perform system reset as well as health check indicator. LED0 will turn on when error flag is detected. LED1 and LED2 will turn on when the SERDES is operational.

Schematic Signal Name FunctionUSER_PB0 System ResetUSER_LED0 Error Flag (when error bit detected)USER_LED1 OpenLDI_TX SER is LOCKED (operational)USER_LED2 OpenLDI_RX DES is LOCKED (operational)

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System Console Graphic User Interface (GUI)

The LVDS OLDI BIST consist of Data Pattern Generator, generating PRBS7 random data, feeding 24bits of data (representing the 24 bit RGB data) into the OpenLDI_TX IP. Four channels of serialized data are then loopbacked to the OpenLDI_RX IP which deserializes it and sends it to the PRBS checker. A system console GUI displays the amount of data transmitted and number of bit error(s) found if any.

To invoke the system console:

Tools System Debugging Tools System Console.

You have to source the dashboard.tcl to invoke the GUI.

Command: source dashboard.tcl

Or, if you have copied it to the “scripts” folder, you can click to open the GUI.

Figure 12: System Console View

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Figure 12: OpenLDI_Self_Test View

Once the GUI appears, do the following steps:

1) Click “Start Link Test”. This will enable the Data Pattern Generator and start transmitting. To stop transmitting, click “Stop Link Test”

2) The default bitslip should have the correct word boundary alignment from the start. If not, you can optionally bitslip the Deserializer.

3) The “locked” LED would turn GREEN when the Data Pattern Checker is locked on to receiving the correct data continuously.

4) Click “Check” to start check for Total Bits Transmitted, and Total Error Bit Detected. When the LO counter overflow, HI will count up by 1.

5) Click “Inject error” to insert 1-bit error.

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6) Click “Clear” to reset all records of Total Bits Transmitted, and Total Error Bit Detected.

The HI and LO refers to the Lower Word and Higher Word as explained in: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf

Figure 13: Table 34-14 & 34-15 defining LOWER and HIGHER WORD Field Descriptors

Results

In addition to viewing the results from the GUI, you can also view in detail of the PRBS transmitted from the TX to the RX receiving end as shown in figure 14.

Figure 14: SignalTap of transmitted data and received data at every stage within Qsys

Conclusion

The design example provides a simple BIST test that can be implemented with a HSMC Loopback card to test the data transmission capability of the OpenLDI_TX and OpenLDI_RX IP.

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Revision History

Revision # Comments / Updates Date

V0.8 Initial draft Sept 2016

V0.9 Auto BU review and formatting Dec 4, 2016

V0.91 2nd review and formatting Dec 5, 2016

V1.0 Initial Release Dec 5,2016

References

IP Component - OpenLDI / FPD-Link / Camera Link VIP Component for Qsyshttp://www.alterawiki.com/wiki/IP_Component_-_OpenLDI_/_FPD-Link_/_Camera_Link_VIP_Component_for_Qsys

Embedded Peripherals IP User Guidehttps://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf

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