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Lecture 2
Introduction to VHDL
Why a HDL, VHDL Introduction,all the intermediate steps
BTF4220 - Digital Electronics 2Feb. 27, 2015
Andreas HabeggerBern University of Applied Sciences
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.2
Agenda
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming The Naming in our Research-Unit
Designing with VHDLDesign Scope VHDL File OverviewDesigne Units
Home Work
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.3
Circuit Descriptions in the 70ies
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.3
Circuit Descriptions in the 70ies
My Example IC
The system has four states. When instate Off, the system outputs 0 andstays in state Off until the inputbecomes 1. In that case, the systementers state On1 followed by On2, andthen On3, in which the system outputs1. The system then returns to state Off.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.3
Circuit Descriptions in the 70ies
My Example IC
The system has four states. When instate Off, the system outputs 0 andstays in state Off until the inputbecomes 1. In that case, the systementers state On1 followed by On2, andthen On3, in which the system outputs1. The system then returns to state Off.
Off
On1
x = 1
x = 0
On2
x = 1
On3
x = 1
b’
b
Figure: State Event diagram of circuitexample
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.3
Circuit Descriptions in the 70ies
My Example IC
The system has four states. When instate Off, the system outputs 0 andstays in state Off until the inputbecomes 1. In that case, the systementers state On1 followed by On2, andthen On3, in which the system outputs1. The system then returns to state Off.
Off
On1
x = 1
x = 0
On2
x = 1
On3
x = 1
b’
b
Figure: State Event diagram of circuitexample
Figure: Block diagram of circuit example
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.4
How to Describe Hardware
Is there only one language
There are lots of different HDLs out there. But there are standards used byindustry and there are leading-edge companies behind new technologieshence they provide tool-chain and libraries. The most important languages willbe described next.
VHDL Very High Speed Integrated Circuit Hardware DescriptionLanguage → developed by a group of U.S. DoD → becamean IEEE standard in 1987 (IEEE 1076). Last updated on April2011 → VHDL-2008
Verilog Has been developed by a particular company in the 1980sand is C oriented. Verilog became an IEEE standard in theyear 1995 (IEEE 1364)
SystemC Has recently evolved - 2000s. Its purpose is manly for SoCs.The language is more like a framework for C/C++ → becamean IEEE standard in 2005 (IEEE 1666)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.4
How to Describe Hardware
Is there only one language
There are lots of different HDLs out there. But there are standards used byindustry and there are leading-edge companies behind new technologieshence they provide tool-chain and libraries. The most important languages willbe described next.
VHDL Very High Speed Integrated Circuit Hardware DescriptionLanguage → developed by a group of U.S. DoD → becamean IEEE standard in 1987 (IEEE 1076). Last updated on April2011 → VHDL-2008
Verilog Has been developed by a particular company in the 1980sand is C oriented. Verilog became an IEEE standard in theyear 1995 (IEEE 1364)
SystemC Has recently evolved - 2000s. Its purpose is manly for SoCs.The language is more like a framework for C/C++ → becamean IEEE standard in 2005 (IEEE 1666)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.4
How to Describe Hardware
Is there only one language
There are lots of different HDLs out there. But there are standards used byindustry and there are leading-edge companies behind new technologieshence they provide tool-chain and libraries. The most important languages willbe described next.
VHDL Very High Speed Integrated Circuit Hardware DescriptionLanguage → developed by a group of U.S. DoD → becamean IEEE standard in 1987 (IEEE 1076). Last updated on April2011 → VHDL-2008
Verilog Has been developed by a particular company in the 1980sand is C oriented. Verilog became an IEEE standard in theyear 1995 (IEEE 1364)
SystemC Has recently evolved - 2000s. Its purpose is manly for SoCs.The language is more like a framework for C/C++ → becamean IEEE standard in 2005 (IEEE 1666)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.4
How to Describe Hardware
Is there only one language
There are lots of different HDLs out there. But there are standards used byindustry and there are leading-edge companies behind new technologieshence they provide tool-chain and libraries. The most important languages willbe described next.
VHDL Very High Speed Integrated Circuit Hardware DescriptionLanguage → developed by a group of U.S. DoD → becamean IEEE standard in 1987 (IEEE 1076). Last updated on April2011 → VHDL-2008
Verilog Has been developed by a particular company in the 1980sand is C oriented. Verilog became an IEEE standard in theyear 1995 (IEEE 1364)
SystemC Has recently evolved - 2000s. Its purpose is manly for SoCs.The language is more like a framework for C/C++ → becamean IEEE standard in 2005 (IEEE 1666)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.5
Some Information around VHDL
It can be used across all programmable logic and ASIC technologies
It is well used in European industry hence well supported
It can be used for simulation and implementation
It is an object oriented language
A specification language (descriptive)
Hierarchical
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.5
Some Information around VHDL
It can be used across all programmable logic and ASIC technologies
It is well used in European industry hence well supported
It can be used for simulation and implementation
It is an object oriented language
A specification language (descriptive)
Hierarchical
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.5
Some Information around VHDL
It can be used across all programmable logic and ASIC technologies
It is well used in European industry hence well supported
It can be used for simulation and implementation
It is an object oriented language
A specification language (descriptive)
Hierarchical
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.5
Some Information around VHDL
It can be used across all programmable logic and ASIC technologies
It is well used in European industry hence well supported
It can be used for simulation and implementation
It is an object oriented language
A specification language (descriptive)
Hierarchical
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.5
Some Information around VHDL
It can be used across all programmable logic and ASIC technologies
It is well used in European industry hence well supported
It can be used for simulation and implementation
It is an object oriented language
A specification language (descriptive)
Hierarchical
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.6
Some Terms and Facts around HW Description
What is SynthesisThis is the process where your VHDL description istranslated into gates. Of course, s synthesis tool will producea netlist on place of gates. A subsequent process will targetan ASIC, CPLD, FPGA etc. architecture.
What is the difference between VHDL and VerilogThere are not a lot of differences. However, VHDL intendedas a specification language whereas Verilog intended as asimulation language – more C like. When a VHDL describedcircuits builds you have a big chance to get the function youwant due to its strictness.
Can I use VHDL for the analog part of a designYes and No! There is a VHDL Analogue and Mixed Signalspecific language add-on – VHDL-AMS. However, the idea ofanalogue synthesis is still in its early days.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.6
Some Terms and Facts around HW Description
What is SynthesisThis is the process where your VHDL description istranslated into gates. Of course, s synthesis tool will producea netlist on place of gates. A subsequent process will targetan ASIC, CPLD, FPGA etc. architecture.
What is the difference between VHDL and VerilogThere are not a lot of differences. However, VHDL intendedas a specification language whereas Verilog intended as asimulation language – more C like. When a VHDL describedcircuits builds you have a big chance to get the function youwant due to its strictness.
Can I use VHDL for the analog part of a designYes and No! There is a VHDL Analogue and Mixed Signalspecific language add-on – VHDL-AMS. However, the idea ofanalogue synthesis is still in its early days.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.6
Some Terms and Facts around HW Description
What is SynthesisThis is the process where your VHDL description istranslated into gates. Of course, s synthesis tool will producea netlist on place of gates. A subsequent process will targetan ASIC, CPLD, FPGA etc. architecture.
What is the difference between VHDL and VerilogThere are not a lot of differences. However, VHDL intendedas a specification language whereas Verilog intended as asimulation language – more C like. When a VHDL describedcircuits builds you have a big chance to get the function youwant due to its strictness.
Can I use VHDL for the analog part of a designYes and No! There is a VHDL Analogue and Mixed Signalspecific language add-on – VHDL-AMS. However, the idea ofanalogue synthesis is still in its early days.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.7
Some Terms and Facts around HW Description
How must I write VHDL to make it synthesisableThe big thing! VHDL provides a big set of languageconstructs, which are not synthesisable. There is only a smallsubset that works on hardware and you must stick to thatsubset. You must know how the synthesizer is going totranslate your VHDL circuit description. For FPGA inparticular you must develop a strong understanding of yourhardware structure. Keep in mind that you are describinghardware rather than programming. Forgetting this simplybut important fact will lead to pain later.
Are there tools to automatically generate VHDL test benchesThe most suitable answer is no. Writing test scenarios isalways a complex task, requiring strong know-how of thetargeted system behavior.
Are there source code libraries availableYes, of course there are! The IEEE library available containsvery low-level type and function packages. Thestd_logic_1164 package is an industry standard. Forarithmetic we use an other IEEE industry standard, thenumeric_std library.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.7
Some Terms and Facts around HW Description
How must I write VHDL to make it synthesisableThe big thing! VHDL provides a big set of languageconstructs, which are not synthesisable. There is only a smallsubset that works on hardware and you must stick to thatsubset. You must know how the synthesizer is going totranslate your VHDL circuit description. For FPGA inparticular you must develop a strong understanding of yourhardware structure. Keep in mind that you are describinghardware rather than programming. Forgetting this simplybut important fact will lead to pain later.
Are there tools to automatically generate VHDL test benchesThe most suitable answer is no. Writing test scenarios isalways a complex task, requiring strong know-how of thetargeted system behavior.
Are there source code libraries availableYes, of course there are! The IEEE library available containsvery low-level type and function packages. Thestd_logic_1164 package is an industry standard. Forarithmetic we use an other IEEE industry standard, thenumeric_std library.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.7
Some Terms and Facts around HW Description
How must I write VHDL to make it synthesisableThe big thing! VHDL provides a big set of languageconstructs, which are not synthesisable. There is only a smallsubset that works on hardware and you must stick to thatsubset. You must know how the synthesizer is going totranslate your VHDL circuit description. For FPGA inparticular you must develop a strong understanding of yourhardware structure. Keep in mind that you are describinghardware rather than programming. Forgetting this simplybut important fact will lead to pain later.
Are there tools to automatically generate VHDL test benchesThe most suitable answer is no. Writing test scenarios isalways a complex task, requiring strong know-how of thetargeted system behavior.
Are there source code libraries availableYes, of course there are! The IEEE library available containsvery low-level type and function packages. Thestd_logic_1164 package is an industry standard. Forarithmetic we use an other IEEE industry standard, thenumeric_std library.
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.8
VHDL Naming Convention
Use meaningful names for identifiers. (Use the same names as in theblock diagrams! Never use inputA, inputB etc.)
Names should indicate the purpose (e.g., AdrCounter), not the type (e.g.,UpCounter8) of an object.
Use camel-case writing and less than 15 characters for identifiers.
Indicate special properties or types of names by a suffix.
Use the same name for a signal throughout all levels, or attach a prefix tothe name at higher levels which indicates the source/destinationsubcomponent of the signal (e.g., IdlexDO -> CtrlIdlexD).
Rename signals only where necessary (e.g. by mode chances).
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.8
VHDL Naming Convention
Use meaningful names for identifiers. (Use the same names as in theblock diagrams! Never use inputA, inputB etc.)
Names should indicate the purpose (e.g., AdrCounter), not the type (e.g.,UpCounter8) of an object.
Use camel-case writing and less than 15 characters for identifiers.
Indicate special properties or types of names by a suffix.
Use the same name for a signal throughout all levels, or attach a prefix tothe name at higher levels which indicates the source/destinationsubcomponent of the signal (e.g., IdlexDO -> CtrlIdlexD).
Rename signals only where necessary (e.g. by mode chances).
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.8
VHDL Naming Convention
Use meaningful names for identifiers. (Use the same names as in theblock diagrams! Never use inputA, inputB etc.)
Names should indicate the purpose (e.g., AdrCounter), not the type (e.g.,UpCounter8) of an object.
Use camel-case writing and less than 15 characters for identifiers.
Indicate special properties or types of names by a suffix.
Use the same name for a signal throughout all levels, or attach a prefix tothe name at higher levels which indicates the source/destinationsubcomponent of the signal (e.g., IdlexDO -> CtrlIdlexD).
Rename signals only where necessary (e.g. by mode chances).
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.8
VHDL Naming Convention
Use meaningful names for identifiers. (Use the same names as in theblock diagrams! Never use inputA, inputB etc.)
Names should indicate the purpose (e.g., AdrCounter), not the type (e.g.,UpCounter8) of an object.
Use camel-case writing and less than 15 characters for identifiers.
Indicate special properties or types of names by a suffix.
Use the same name for a signal throughout all levels, or attach a prefix tothe name at higher levels which indicates the source/destinationsubcomponent of the signal (e.g., IdlexDO -> CtrlIdlexD).
Rename signals only where necessary (e.g. by mode chances).
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.8
VHDL Naming Convention
Use meaningful names for identifiers. (Use the same names as in theblock diagrams! Never use inputA, inputB etc.)
Names should indicate the purpose (e.g., AdrCounter), not the type (e.g.,UpCounter8) of an object.
Use camel-case writing and less than 15 characters for identifiers.
Indicate special properties or types of names by a suffix.
Use the same name for a signal throughout all levels, or attach a prefix tothe name at higher levels which indicates the source/destinationsubcomponent of the signal (e.g., IdlexDO -> CtrlIdlexD).
Rename signals only where necessary (e.g. by mode chances).
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.9
Our Proposal
Names are composed of several 2-6 character sub-strings
The sub-strings have the first letter in upper case and the remainingletters in lower caseUse camel-case naming instead of underscoresThe sub-strings should be meaningful abbreviations of actions(e.g., Sel, Inc, Add, Load) and objects (e.g., Reg, Mux, Data)
The names should give an appropriate description of the purpose of theobject
Names of objects with a hardware equivalent (e.g., signals,entities/architectures, components) start with an upper-case letter.
Names of objects with no hardware equivalent (e.g., variables, types) andlabels start with a lower-case letter
Our naming proposal is related to the one used at ETHZ
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.9
Our Proposal
Names are composed of several 2-6 character sub-stringsThe sub-strings have the first letter in upper case and the remainingletters in lower caseUse camel-case naming instead of underscoresThe sub-strings should be meaningful abbreviations of actions(e.g., Sel, Inc, Add, Load) and objects (e.g., Reg, Mux, Data)
The names should give an appropriate description of the purpose of theobject
Names of objects with a hardware equivalent (e.g., signals,entities/architectures, components) start with an upper-case letter.
Names of objects with no hardware equivalent (e.g., variables, types) andlabels start with a lower-case letter
Our naming proposal is related to the one used at ETHZ
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.9
Our Proposal
Names are composed of several 2-6 character sub-stringsThe sub-strings have the first letter in upper case and the remainingletters in lower caseUse camel-case naming instead of underscoresThe sub-strings should be meaningful abbreviations of actions(e.g., Sel, Inc, Add, Load) and objects (e.g., Reg, Mux, Data)
The names should give an appropriate description of the purpose of theobject
Names of objects with a hardware equivalent (e.g., signals,entities/architectures, components) start with an upper-case letter.
Names of objects with no hardware equivalent (e.g., variables, types) andlabels start with a lower-case letter
Our naming proposal is related to the one used at ETHZ
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.9
Our Proposal
Names are composed of several 2-6 character sub-stringsThe sub-strings have the first letter in upper case and the remainingletters in lower caseUse camel-case naming instead of underscoresThe sub-strings should be meaningful abbreviations of actions(e.g., Sel, Inc, Add, Load) and objects (e.g., Reg, Mux, Data)
The names should give an appropriate description of the purpose of theobject
Names of objects with a hardware equivalent (e.g., signals,entities/architectures, components) start with an upper-case letter.
Names of objects with no hardware equivalent (e.g., variables, types) andlabels start with a lower-case letter
Our naming proposal is related to the one used at ETHZ
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.9
Our Proposal
Names are composed of several 2-6 character sub-stringsThe sub-strings have the first letter in upper case and the remainingletters in lower caseUse camel-case naming instead of underscoresThe sub-strings should be meaningful abbreviations of actions(e.g., Sel, Inc, Add, Load) and objects (e.g., Reg, Mux, Data)
The names should give an appropriate description of the purpose of theobject
Names of objects with a hardware equivalent (e.g., signals,entities/architectures, components) start with an upper-case letter.
Names of objects with no hardware equivalent (e.g., variables, types) andlabels start with a lower-case letter
Our naming proposal is related to the one used at ETHZ
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.10
Constant, Variable, Type Names
Constant Names
Use upper-case letters and “_” for indicating a space (e.g. WIDTH,RAM_DEPTH, LFSR_INIT)
Avoid “_” in generics (synthesis attaches generic names to other nameswith “_” as delimiter)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.10
Constant, Variable, Type Names
Constant Names
Use upper-case letters and “_” for indicating a space (e.g. WIDTH,RAM_DEPTH, LFSR_INIT)
Avoid “_” in generics (synthesis attaches generic names to other nameswith “_” as delimiter)
Variable Names
Start with a lower-case letter (e.g. temp, item, currentState)
Have no suffix (as opposed to signal names)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.10
Constant, Variable, Type Names
Constant Names
Use upper-case letters and “_” for indicating a space (e.g. WIDTH,RAM_DEPTH, LFSR_INIT)
Avoid “_” in generics (synthesis attaches generic names to other nameswith “_” as delimiter)
Variable Names
Start with a lower-case letter (e.g. temp, item, currentState)
Have no suffix (as opposed to signal names)
Type Names
Have a suffix “Type” or a name that implies a type (e.g. stateType (here“Type”), stdLogicArray (here “Array”))
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.11
Signal Names
Start with an upper-case letter
Have a suffix with syntax “x[CRSDTA][NP]?Z?L?[IO]?” (“[...]” denotes achoice, “?” means optional)
[CRSDTA] Indicates the class of signal. Some examples:clock
A clock ends with C e.g. ClkxCreset
A reset ends with R e.g. RstxRLcontrol/status
A control or status signal ends with S e.g. SelInputxS orFullxS
data/addressAn address or data ends with D e.g. SamplexD orRamAdrxD
testTest signals end with a T e.g. ScanEnxT RamWriteEnxT
asyncAn asynchronous signal ends with A e.g. StrobexA
[NP]? Indicates next (N) and present (P) state for a signal (e.g.StatexDN → StatexDP, AddrCntxDN → AddrCntxDP)
Z? Indicates a three-state signalL? Indicates an active low signal
[IO]? Indicates an input/output signal and its direction (e.g.CoeffxDI, FullxSO, ExtRamxDZIO)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow
1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
Circuit Implementation Work-flow
1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
Circuit Implementation Work-flow1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
Circuit Implementation Work-flow1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
Circuit Implementation Work-flow1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
Circuit Implementation Work-flow1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.12
Design Flow with Xilinx
Circuit Test Work-flow1. Circuit description in VHDL
2. VHDL test-bench for testing
3. Simulation with ModelSim
Circuit Implementation Work-flow1. Circuit description in VHDL
2. Synthesis (XST) → syntax-check, stateminimization, state encoding
3. Translation → Netlist
4. Mapping : translate an expression intotechnology specific gates
5. CPLD/FPGA configuration
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.13
File Names and Sections
The source code file name has the same name as the design unitdescribed by a specific file – start with a lower-case and use camel-casewriting.
The delimiter “-” and succeeding characters are going to be ignored in filenames (e.g. edgeDetector-entity or edgeDetector-behavior).
This provide the option of splitting a description in several source codefiles.
There is no need for splitting entity and behavior files but it is a properdesign method
VHDL files end with a file suffix of “.vhd” or “.vhdl” (we use “.vhdl”)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.13
File Names and SectionsThe source code file name has the same name as the design unitdescribed by a specific file – start with a lower-case and use camel-casewriting.
The delimiter “-” and succeeding characters are going to be ignored in filenames (e.g. edgeDetector-entity or edgeDetector-behavior).
This provide the option of splitting a description in several source codefiles.
There is no need for splitting entity and behavior files but it is a properdesign method
VHDL files end with a file suffix of “.vhd” or “.vhdl” (we use “.vhdl”)
LIBRARY
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.13
File Names and SectionsThe source code file name has the same name as the design unitdescribed by a specific file – start with a lower-case and use camel-casewriting.
The delimiter “-” and succeeding characters are going to be ignored in filenames (e.g. edgeDetector-entity or edgeDetector-behavior).
This provide the option of splitting a description in several source codefiles.
There is no need for splitting entity and behavior files but it is a properdesign method
VHDL files end with a file suffix of “.vhd” or “.vhdl” (we use “.vhdl”)
ENTITY Cmp interface
LIBRARY
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.13
File Names and SectionsThe source code file name has the same name as the design unitdescribed by a specific file – start with a lower-case and use camel-casewriting.
The delimiter “-” and succeeding characters are going to be ignored in filenames (e.g. edgeDetector-entity or edgeDetector-behavior).
This provide the option of splitting a description in several source codefiles.
There is no need for splitting entity and behavior files but it is a properdesign method
VHDL files end with a file suffix of “.vhd” or “.vhdl” (we use “.vhdl”)
ARCHITECTURE Cmp functionality
ENTITY Cmp interface
LIBRARY
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.13
File Names and SectionsThe source code file name has the same name as the design unitdescribed by a specific file – start with a lower-case and use camel-casewriting.
The delimiter “-” and succeeding characters are going to be ignored in filenames (e.g. edgeDetector-entity or edgeDetector-behavior).
This provide the option of splitting a description in several source codefiles.
There is no need for splitting entity and behavior files but it is a properdesign method
VHDL files end with a file suffix of “.vhd” or “.vhdl” (we use “.vhdl”)
VHDL
ARCHITECTURE Cmp functionality
ENTITY Cmp interface
LIBRARY
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.14
Design Unit Names
Entity Meaningful name describing the purpose of the circuit (e.g.dff, adder4bit)
Architecture According to the modeling style used (i.e. behavioral,procedural, dataflow, or structural) or to some specificarchitecture property e.g. for test-bench use DUT (DeviceUnder Test)
Configuration Name of the corresponding entity with suffix "Cfg" (e.g.myAdderCfg)
Package Name of the design (i.e. top-level entity) with suffix "Pkg"(e.g. myAdderPkg)
Testbench Name of corresponding entity with suffix "Tb" (e.g.myAdderTb, myAdderTbPkg)
Library Library name with suffix "Lib" (e.g arithLib)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.14
Design Unit Names
Entity Meaningful name describing the purpose of the circuit (e.g.dff, adder4bit)
Architecture According to the modeling style used (i.e. behavioral,procedural, dataflow, or structural) or to some specificarchitecture property e.g. for test-bench use DUT (DeviceUnder Test)
Configuration Name of the corresponding entity with suffix "Cfg" (e.g.myAdderCfg)
Package Name of the design (i.e. top-level entity) with suffix "Pkg"(e.g. myAdderPkg)
Testbench Name of corresponding entity with suffix "Tb" (e.g.myAdderTb, myAdderTbPkg)
Library Library name with suffix "Lib" (e.g arithLib)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.14
Design Unit Names
Entity Meaningful name describing the purpose of the circuit (e.g.dff, adder4bit)
Architecture According to the modeling style used (i.e. behavioral,procedural, dataflow, or structural) or to some specificarchitecture property e.g. for test-bench use DUT (DeviceUnder Test)
Configuration Name of the corresponding entity with suffix "Cfg" (e.g.myAdderCfg)
Package Name of the design (i.e. top-level entity) with suffix "Pkg"(e.g. myAdderPkg)
Testbench Name of corresponding entity with suffix "Tb" (e.g.myAdderTb, myAdderTbPkg)
Library Library name with suffix "Lib" (e.g arithLib)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.14
Design Unit Names
Entity Meaningful name describing the purpose of the circuit (e.g.dff, adder4bit)
Architecture According to the modeling style used (i.e. behavioral,procedural, dataflow, or structural) or to some specificarchitecture property e.g. for test-bench use DUT (DeviceUnder Test)
Configuration Name of the corresponding entity with suffix "Cfg" (e.g.myAdderCfg)
Package Name of the design (i.e. top-level entity) with suffix "Pkg"(e.g. myAdderPkg)
Testbench Name of corresponding entity with suffix "Tb" (e.g.myAdderTb, myAdderTbPkg)
Library Library name with suffix "Lib" (e.g arithLib)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.14
Design Unit Names
Entity Meaningful name describing the purpose of the circuit (e.g.dff, adder4bit)
Architecture According to the modeling style used (i.e. behavioral,procedural, dataflow, or structural) or to some specificarchitecture property e.g. for test-bench use DUT (DeviceUnder Test)
Configuration Name of the corresponding entity with suffix "Cfg" (e.g.myAdderCfg)
Package Name of the design (i.e. top-level entity) with suffix "Pkg"(e.g. myAdderPkg)
Testbench Name of corresponding entity with suffix "Tb" (e.g.myAdderTb, myAdderTbPkg)
Library Library name with suffix "Lib" (e.g arithLib)
Introduction to VHDL
Andreas Habegger
VHDL IntroductionVHDL terms and thoughts
Naming ConventionAbout Naming
The Naming in ourResearch-Unit
Designing with VHDLDesign Scope
VHDL File Overview
Designe Units
Home Work
Rev. ec317bd – 2.15
Home Work
Draw the circuit diagram of a 1 bit full-adder (use meaningful signalnames)
Draw the block diagram of a 4 bits adder reusing the 1 bit full-adder (usemeaningful unit and signal names)
Think about a test for the 4 bit full-adder
Read chapter 1 and 2 in the book “Free Range VHDL”