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Introduction to the PXA-3xx Processor Family 1-4 PXA-3xx Processor Family

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Page 1: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Introduction to the PXA-3xx Processor Family

1-4

PXA-3xx Processor Family

Page 2: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

82H’08

2H’081H’08

Very High Tier

EntertainmentPhones

High/MidTier

SmartphonesFeature High

Low TierFeature

Phone Low

Tavor P65/U/PV / PV2624MHz MH-PV Gilon AFEMICCO PMIC

S/WPS:WEDGE/HSDPA 3.6HSuPA 5.76 GERAN EvoOS:MSFT Crossbow

TRI

CORE

Tavor L624Mhz APDigRF 3.0Marvell PMIC

2

C

O

R

E

SWPS:WEDGE/HSDPA 3.6OS:RTOS/Linux

1H’09

ES: 12’07HVM: 8’08

ES: 01’08HVM: Q1’09

2H’081H’08

Tavor L2624Mhz APDigRF 3.0Marvell PMIC

SWPS:WEDGE/HSDPA 3.6 +HSuPA 5.8 GERAN Evo.OS:RTOS/Linux

ES: TBD’08HVM: TBD’09

PXA3xx Family806Mhz MHLV V5 Super Scalar

S/WMSFT PPC/SP/CE/Linux

2

CHIP

HM-T or TPV 416Mhz Bulverde Gilon AFEMICCO PMIC

PS:EDGE/WCDMA

ES: NowHVM: Now

1H’08

2

C

O

R

E

Legend

Full Production

Entering Production

In Development

Reduced development cost due to AP/CP full SW compatibility

Two chip for high end or unique

comm interfaces (WiMax & EVDO)

Cost-optimized platform for

feature-tier handsets

SW Compatible 3 core-single chip for high end

mainstream & low end solutions MS/Linux/RTOS/Java

Two chip & Single chip product lines cover handset portfolio requirements

Marvell CHG Platform Roadmap

Content Updated: 11.05.07Dates, specifications, product descriptions, and plans are

subject to change at any time, without notice.

Page 3: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

99

PXA255PXA255

CotullaCotullaXscaleXscale®® CoreCore

Shipping in HVM since Shipping in HVM since 20022002

PXA270PXA270

BulverdeBulverdeXscaleXscale®® CoreCore

Shipping in HVM since Shipping in HVM since 20042004

High TierHigh Tier

APAP’’ss

Mid TierMid Tier

APAP’’ss

CostCost

SensitiveSensitive

APAP’’ss

1H1H’’0707 2H2H’’0707 2H2H’’09091H1H’’09092H2H’’08081H1H’’0808

PXA320PXA320

Monahans PMonahans PXscaleXscale®® CoreCore

WMMX2, L2 CacheWMMX2, L2 Cache

806MHz806MHz

PXA310PXA310

Monahans LVMonahans LVXscaleXscale®® CoreCore

WMMX2, VGA Video, WMMX2, VGA Video, SecuritySecurity

Bulverde T

TSMC Migration

Target HVM: 1H’08

PXA300PXA300

Monahans LMonahans LXscaleXscale®® CoreCore

WMMX2WMMX2

Cost SensitiveCost Sensitive

624MHz624MHz

624MHz624MHz

624MHz624MHz

400MHz400MHz

624MHz624MHz

Marvell PXA AP Roadmap

Monahans PVXScale® Core, WMMX2

Video, MLC NANDI/O Refresh

Target HVM: 2H’08

Future:

MMP

Family

Monahans GXXscale® Core, WMMX2

3D Graphics, Video, MLC NAND

Target HVM: Mid’09

624MHz624MHz

1GHz1GHz

Under Development

In Definition

High Volume Production

Left Edge = HVM Start

LEGEND

Content Updated: 11.05.07

Monahans LEMonahans LEXScaleXScale®® Core, WMMX2Core, WMMX2

Cost SensitiveCost Sensitive

Target HVM: 1HTarget HVM: 1H’’0909

624MHz624MHz

Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.

Page 4: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

10

PXA Application Processor Comparison

Indicates significant changeContent Updated: N/A Static

Function PXA270 PXA320 PXA300 PXA310

Core Frequency Up to 624 MHz Up to 806 MHz Up to 624 MHz Up to 624 MHz

System Bus Single shared internal system bus

Low-latency, fully-connected, memory switch

Low-latency, fully-connected, memory switch

Low-latency, fully-connected, memory switch

L2 CacheInternal SRAM

No L2 cache256KB SRAM

256KB L2 cache768KB SRAM

No L2 cache256KB SRAM

No L2 cache256KB SRAM

External memory interface

Shared external mem i/f for 104 MHz SDRAM x32 or x16, and NOR 52 MHz

Separate ext mem i/f for 260 MHz DDR x32 and NAND 13 MHz, NOR 52 MHz

Separate ext mem i/f for 260 MHz DDR x16 and NAND 33 MHz, NOR 52 MHz

Separate ext mem i/f for 260 MHz DDR x16 and NAND 33 MHz, NOR 52 MHz

Security Wireless Trusted Module None None Wireless Trusted Module 2

Power Mgmt Wireless Intel SpeedStep®Technology

Enhanced Wireless Intel SpeedStep® Technology

Enhanced Wireless Intel SpeedStep® Technology with standby states

Enhanced Wireless Intel SpeedStep® Technology with standby states

Multimedia acceleration

Intel® Wireless MMX™technology

Intel® Wireless MMX™ 2 technology. 2D graphics, scaling, rotation

Intel® Wireless MMX™ 2 technology w/ 2D

Intel® Wireless MMX™ 2 technology w/ 2D. Video/JPEG h/w acceleration. Chroma-key.

Movie Playback (video + AAC decode)

MPEG-4 up to 30 fps, VGAH.264 up to 15 fps, VGA

MPEG-4 up to 30 fps, VGAH.264 up to 15+ fps, VGA

MPEG-4 up to 30 fps, VGAH.264 up to 15 fps, VGA

MPEG-4 up to 30 fps, VGAH.264 up to 30 fps, VGA

Camcorder (video + AMR encode)

MPEG-4 up to 30 fps, QVGAH.264 up to 15 fps, QVGA

MPEG-4 up to 30 fps, CIFH.264 up to 15 fps, CIF

MPEG-4 up to 30 fps, CIFH.264 up to 15 fps, CIF

MPEG-4 up to 30 fps, VGAH.264 up to 15 fps, VGA

Video Telephony(video+AMR enc-dec)

MPEG-4 up to 30 fps, QVGAH.264 up to 15 fps, QVGA

MPEG-4 up to 30 fps, QVGAH.264 up to 15+ fps, QVGA

MPEG-4 up to 30 fps, QVGAH.264 up to 15+ fps, QVGA

MPEG-4 up to 30 fps, CIFH.264 up to 15+ fps, CIF

Camera interface sensor support

Intel® Quick Capture Technology, 1.3 Mp

Enhanced Intel® Quick Capture Technology, 2Mp

Enhanced Intel® Quick Capture Technology, 2Mp

Enhanced Intel® Quick Capture Technology + faster clocks, color conversion, JPEG sensors; 5Mp

USB 1 FS client, 1 FS OTG + 3 FS host ports

HS client UTMI and FS OTG + 2 FS ports

HS client UTMI and FS OTG + 2 FS ports

HS Client ULPI and FS OTG + 1 FS port

UARTsSSPs

Three, 921 kbpsThree, 13 MHz

Three, 921 kbps Four, 13 MHz

Three, 3.6 MbpsFour, 13 MHz

Three, 3.6 MbpsFour, 26 MHz

MMC/SD/SDIO One, 19.5 MHz Two, 19.5 MHz Two, 26 MHz Three, 26 MHz

Package Size 13x13mm discrete14x14mm stacked

14x14mm discrete 13x13mm discrete15x15mm stacked, PoP

13x13mm discrete15x15mm stacked, PoP

Page 5: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

11

2700G

Discontinued

DecDec

‘‘0909LTB = 6/30/09

PXA AP Migration Roadmap & Recommendations*

2009 2011

Mig

rate

To

Mig

rate

To

Mig

rate

Off

Mig

rate

Off

2008

65NM

180NM

150NM

90NM

DecDec

‘‘0909LTB = 6/30/09

Su

sta

inS

us

tain

2010

PXA270 Pb-Free

PXA255 Pb-Free

2700G3/5 Pb-Free

PXA270M Pb-Free

PXA320 Pb-Free

LTB = 3/1/08

130NM

PXA270 Pb-Free

Future

2014

PXA310 Pb-Free

PXA300 Pb-FreePXA255 Pb-Free

PXA300 Pb-Free

DecDec

‘‘0707PXA270 Pb

PXA255 Pb

2700G5 Pb

PXA271/2 Pb

& Pb-Free

DecDec

‘‘0909

Content Verified: 10.31.07

2011

2011

2011

2011

Monahans LV-T 65NM

2011

*Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.

Page 6: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

PXA-3xx Family Packaging Options

Memory Stack Package

PXA-320 Discrete part –external memory

14 x 14 x 1.0 mm456-pin, 0.5 mm pitch

Lead-free, max Tcase = 85°C

PXA-300 Discrete part –external memory

13 x 13 x 1.0 mm400-pin, 0.5 mm pitchLead-free, max Tcase = 85°C

PXA-300 1 Gb (128MBytes) NAND512 Mb (64MBytes) DDR

15 x 15 x 1.4 mm416-pin, 0.65 mm pitch

1-8Marvell Confidential

512 Mb (64MBytes) DDR Stack

416-pin, 0.65 mm pitch

Lead-free, max Tcase = 85°C

PXA-310 Discrete part –external memory

13 x 13 x 1.0 mm400-pin, 0.5 mm pitchLead-free, max Tcase = 85°C

PXA-310 2 Gb (256MBytes) NAND1 Gb (128MBytes) DDRStack

15 x 15 x 1.5 mm416-pin, 0.65 mm pitch

Lead-free, max Tcase = 85°C

PXA300 and PXA 310 are designed for HW Compatibility and SW scalability

Page 7: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Intel® Wireless

MMX™ 2

Intel XScale® Core

(32K I$, 32K D$)

Dynamic

Memory

Controller

Static

Memory

Controller

Data Flash

Controller

USB 1 1 Host

Intel® Quick

Capture

Camera

Interface

Mini-

LCD

Cntrlr

LCD

Controller

Memory Switch

Sensor LCD Panel

Internal

DDR

SDRAM

Real-

Time Timers Power

System Bus

#1

System Bus

#2

Data Flash Interface

PC-Card

/CompactFlash

VLIO / SRAM

E

M

P

I

32 Bits

Sync / Async

Flash

2D

Graphics

NAND

USB2.0

High Speed

Client 256 KB L2 Cache

XCVR

UTMI

Power JTAG

Same

New in PXA-320

Enhanced

Marvell PXA-320 vs. PXA-270 Processor

1-10Marvell Confidential

USB 1.1 Host Internal

SRAM

768 KB

Boot

ROM

MMC/SD #1

(4-Bit SDIO)USIM #1

UART / SIR x 3

SSP x 4

Interrupt

Controller

Coprocessor I/F

Intel® MSL Interface

IEEE

802.11

Cellular

Baseband

Keypad InterfacePulse Width

Modulators x 4

AC’97 I2C

Time

Clock

Timers

with Watchdog

DMA Controller Bridge

USIM #2

Power

Management

GPIO

MMC/SD #2

(4-Bit SDIO)

1-Wire

Peripheral Bus #1

Peripheral Bus #2

Consumer

Infrared

I2CJTAG

Security

USB1.1

Client

Touch Screen

OTG

Page 8: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

PXA-3xx Features

Feature PXA-300 PXA-310 PXA-320Frequency Up to 624MHz Up to 624MHz Up to 806MHz

DDR X16 @ 260MHz X16 @ 260MHz X32 @ 260MHz

L2 Cache n/a n/a 256kB

Internal SRAM 256kB 256kB 768kB

DFI Bus NOR Flash, x8 NAND, x16 NAND, VLIO (Variable Latency I/O)

Internal Buses 64-bit, High-Speed Crossbar Memory Switch for Concurrent Memory TransactionsMultiple Internal Buses for Improved Bandwidth

1-15Marvell Confidential

Multiple Internal Buses for Improved Bandwidth

Boot Device NOR Flash or NAND Flash

MMC/SD/SDIO 2 @ 19MHz 3 @ 26MHz 2 @ 19MHz

UARTs 3 @ 3.6Mbps 3 @ 3.6Mbps 3 @ 921kbps

SSPs 4 @ 13MHz 4 @ 26MHz 4 @ 13MHz

LCD 16 and 18 Bit Active Panels, 24 Bit Smart Panels

Mini-LCD (Standby Static Image refresh)

16 & 18 Bit panels 16 & 18 bit panels 16 bit panels

Page 9: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

PXA-3xx Features (continued)

Feature PXA-300 PXA-310 PXA-320USB 3 Full Speed Host

1 Full Speed Client / OTG1 High Speed Client (UTMI)

1 Full Speed Host1 OTG with ULPI interface(Full Speed Host + High Speed Client)

3 Full Speed Host1 Full Speed Client / OTG1 High Speed Client (UTMI)

Video Encode/Decode Acceleration

MMX2 Hardware Accelerator MMX2 instructions

Quick Capture Camera Interface

Up to 4 Mpixel Up to 5 Mpixel Up to 5 Mpixel

1-16Marvell Confidential

Camera Interface

Touchscreen Controller

n/a n/a 4-wire Resistive Panel

GPIO’s Up to 128 GPIO

Other 4 PWMs, 1 One-Wire, I2C, Keypad Interface, USIM, JTAG

Discrete Package 13mm x 13mm400 ball, 0.5mm pitch

13mm x 13mm400 ball, 0.5mm pitch

14mm x 14mm456 ball, 0.5mm pitch

MCP Package 15mm x 15mm416 ball, 0.65mm pitch1Gb NAND + 512Mb DDR

15mm x 15mm416 ball, 0.65mm pitch2Gb NAND + 1Gb DDR

n/a

Page 10: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

PXA-300, PXA-310, PXA-320 Block Diagrams and

1-9

and Feature Differences

Page 11: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

13

1-Source: Marvell Configuration: MHL: Measured video performance of codecs powered by Intel® IPP v5.1 under Linux PVK 2.6.9 alpha2 on Monahans P A1 on Zylonite DVK with L2$ disabled, core/XSI/HSIO/DMC: 416/208/156/260 MHz x16 DDR. Results are average of >3 trials. All cases assume audio processing based on measurements of ~60/80 MHz for MPEG-4 AAC+ decode for P/L,LV and ~30 MHz for AMR-NB encode, and assume ~40/30 MHz for P/L,LV and 15 MHz for A/V sync for AAC+ and AMR NB respectively based on different bit and sampling rates of audio and speech.

Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Marvell products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing.

2- See more details on slide titled “PXA300 Processor Series Battery Life Update”

PXA300 Processor Series OverviewPXA300 delivers excellent multimedia experiences in a low BOM configuration via leading video

performance (WMMX2) balanced with extended battery life (MSPM) & system cost reducing benefits

Key Benefits• Video Performance: Playback (video + AAC decode)1

• MPEG-4 up to 30 fps, VGA• H.264 up to 15 fps, VGA

• Video Performance: Record (video + AMR encode) 1

• MPEG-4 up to 30 fps, CIF• H.264 up to 15 fps, CIF

• Video Telephony video + AMR (enc-dec) 1

• MPEG-4 up to 30 fps, QVGA• H.264 up to 15+ fps, QVGA

• Passes Windows Mobile Smartphone LTK* today! 2

• Over 9 hours of video• Over 13 hours of audio• Over 280 hours of standby

• Packaging Options• Die Stack 1Gb/0.5Gb NAND/DDR• Discrete 13x13mm (0.5mm pitch) & 19x19mm

(0.8mm pitch)• Package on Package options

Great solution for PND with multimedia processing, 2D & 3D graphics capabilities and

routing/mapping performance very competitive with other cost efficient processors

Ideally Suited for:

Feature Phones

Smart phones, Data phones, MP3 phones, Imaging phones

Low-cost PDAs

Embedded Applications

Portable Navigation Devices (PND)

PXA300 Frequency Performance

416 MHz 475K Triangles/second (max. throughput)

11M pixel/second (max pixel rate)

3D Graphics Capabilities

624 MHz 598K Triangles/second (max. throughput)

14.9M pixel/second (max pixel rate)

Mapping in

GPS medium

route calculations

416 MHz

624MHz

147% faster than competing non-integrated solution

168% faster than competing non-integrated solution

Mapping in

GPS long

route calculations

416MHz

624 MHz

181% faster than competing non-integrated solution

209% faster than competing non-integrated solution

Hot Usage Model: PXA300 in PNDs

Content Verified: 10.31.07 *LTK Standby data does not include baseband.

Page 12: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

PXA-300 Processor

1-13Marvell Confidential

Page 13: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

15

PXA300 Processor Series Silicon & Platform Update

Content Updated: 11.05.07

• Memory bundling options to include PoP and die stack/MCP

• PXA300 Embedded samples come in a 19x19mm package with 0.8mm pitch for lower cost manufacturing

• For orders, PPQL material (if available) can be used for sampling

• PPQL is production-quality and production-marked with standard Marvell warranty

• All Platform Software releases

available on Marvell Extranet

Embedded

package

samples

available!!!

*Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.

Item Silicon

Target

Date Year

PXA300 discrete A1 PPQL (13mm) Available 2007

PXA301 (die stack) A1 PPQL (15mm) Available 2007

A1 ES (15mm) Available 2007

A1 PPQL (15mm) 21-Dec 2007

A1 ES for Embedded (19mm) Available 2007

A1 PPQL for Embedded (19mm) 1-Feb 2008

Item Zylonite Based Releases

Target

Date Year

A1 (Crossbow) Beta PPC Release Available 2007

A1 (Crossbow) Beta SP Release Available 2007

A1 Beta WinCE5.0 Release Available 2007

A1 Beta WinCE6.0 Beta Release 15-Jan 2008

A1 Beta WinCE6.0 Final Release 6-Mar 2008

A1 BSP Beta, VTune (Final), GST (Beta), IPP

(Final), OpenGL ES (final), App/UM (Alpha)

Release. Adds Toshiba NAND code to support

PoP . Available 2007

OpenMAX IL released within ww27 Linux MH LV

also available to MH L users Available 2007

Linux 2.6.21 Platform Final Release Available 2007

Item Littleton Based releases

Target

Date Year

A1 WM6 Initial BSP Release 21-Dec 2007

A1 WM6 Final Platform Release 18-Jan 2008

Platform Release

Linux A1 Platform Final Release Available 2007

WM6 Platform Release

Platform Release Linux

WinCE BSP-only Release

WM6 Pro/Std. Platform Release

PXA303

(embedded)

PXA302 (bottom)

Page 14: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

16

PXA300 Processor Series Battery Life

Based on measurements on Zylonite, PXA300 - based phones using Windows Mobile 6 for

Smartphone OS are expected to pass the battery life LTK! Assumption is 900 mAh battery for SmartPhone and 1200mAh for Linux and PPE PE, QVGA LCD, baseband <2.75 mA in standby

Measurements now available under Microsoft Operating Systems and on Linux (there is no official Linux LTK)

Configuration: L A1 “golden” Zylonite with WM6 for Smartphone OS. Measured current from battery supply running each workload, and projectedbattery life based on no baseband case and baseband ~0 mA. Results will vary depending on the actual baseband used.

Power consumption tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual power consumption.

Test Condition WM Smartphone

900 mAh battery

(WMA and WMV)

WM Pocket PC

1200 mAh

(WMA and WMV)

Linux

1200 mAh

Measured 282 hrs 238 hrs 312 hrsstandby

LTK requirement

150 hrs 150 hrs -

Measured 13 hrs 11.85 hrs 15 hrsAudio

LTK

requirement

12 hrs 12 hrs -

Measured 9 hrs 8.3 hrs 8.2 hrsVideo

LTK

requirement

8 hrs 8 hrs -

Content Verified: 10.31.07

Start WM6

Smartphone

designs!

*Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.

Page 15: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

17

PXA300 Processor Series Part Numbers

Important Note: Even parts ordered with the new booking numbers

will likely still have the Intel top-side mark on the package!! The top-side mark will change when the inventory of Intel-marked parts is depleted. We will inform you when that occurs.

Please contact your Sales Representative for more information

Content Updated: 11.5.07*Dates, specifications, product descriptions, and plans

are subject to change at any time, without notice.

New 208MHz

embedded

part numbers

Order Now!

Marvell Part Number Description

88AP300-A1-BGK1C624-T161 PXA300 Application Processor A1 stepping x16 NAND boot, discrete 13x13mm

88AP300-A1-BGK1C624-T162 PXA300 Application Processor A1 stepping x8 NAND boot, discrete 13x13mm88AP300-A1-BGK1C624-T163 PXA300 Application Processor A1 stepping x16 NOR boot, discrete 13x13mm

88AP300-A1-BGK1C208-T164 PXA300 Application Processor A1 stepping x8 NAND boot, discrete 13x13mm

88AP301-A1-BGS1C624

PXA300 Application Processor A1 stepping die stacked with 70nm 1Gb ST Micro NAND and Elpida 512Mb DDR

88AP302-A1-BGW2C624-TN02 PXA300 Application Processor A1 stepping, 624 MHz, auto-boot, PoP bottom 15x15mm88AP302-A1-BGW2C208-TN02 PXA300 Application Processor A1 stepping, 208MHz, auto-boot, PoP bottom 15x15mm

88AP303-A1-BGF2C624-TN12 PXA300 Application Processor A1 stepping x16 NAND boot, discrete 19x19mm

88AP303-A1-BGF2C624-TN22 PXA300 Application Processor A1 stepping x8 NAND boot, discrete 19x19mm88AP303-A1-BGF2C624-TN32 PXA300 Application Processor A1 stepping x16 NOR boot, discrete 19x19mm

88AP303-A1-BGF2C208-TN32 PXA300 Application Processor A1 stepping x16 NOR boot, discrete 19x19mm

PXA303 208MHz Embedded (19x19mm)

PXA300 624MHz Discrete

PXA303 624MHz Embedded (19x19mm)

PXA300 208MHz Discrete

PXA301 624MHz die stack

PXA302 package on package (PoP) bottom

New

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Marvell Confidential © 2007Marvell Confidential © 2007

18

PXA303: PXA300 for Embedded Designs

PXA300 functionality in a package and ball pitch that fits embedded market requirements! Part Number: 88AP303 (full part number on P/N Slide)

Silicon Details! 19x19 package with 0.8mm pitch, ball-out available in EMTS

! Samples available October, 2007

! PPQL material available December, 2007

DVK Details! No new DVK will be offered, customers can use current DVK with current parts for development

BSP Details! No special BSP needed for development on the embedded package, software transitions from non-

embedded to embedded without changes

Content Updated 10.31.07

Ball-out & details of the PXA303 device in the VF-BGA 19x19mm package can be found in the EMTS available on the Extranet

*Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.

Page 17: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

Marvell PXA310 Processor SeriesMonahans LV

Page 18: Introduction to the PXA -3xx Processor Familyread.pudn.com/downloads129/sourcecode/others/551052/PXA300 data... · Marvell PXA AP Roadmap ... Marvell Configuration : MHL: Measured

Marvell Confidential © 2007Marvell Confidential © 2007

2020

PXA310 Processor Series Overview

PXA310: The processor for Mobile Entertainment!!

Start your designs today!

Content Verified: 10.29.07

Product ROI & operator ARPU are driven by

key PXA310 enhancements:

• Up to 624MHz for general-purpose computing

• Hardware acceleration for video & JPEG,

supporting entertainment from all major video

content sources up to D1

• Improved power consumption, especially in

phone standby mode

• Ease of migration from the PXA27x processor

family and other members of the PXA3xx family

• Full security solution that solves the main

bottleneck behind slow adoption into enterprise

Ideally Suited for:

• Secure 3G Multimedia SmartPhones

• Ultra Mobile Devices (UMD) and wireless enterprise devices

• Portable Navigation Devices (PND) with DVB-T

• Embedded Applications

PXA310 differentiated user experiences:

• Digital TV: DVB-T (MPEG-2, D1 30 fps) & DVB-H

• Smooth browsing of rich web content & plug-ins

• MIPS headroom for speech recognition, virus

scanning, .NET CF & Java, plus games

• Playing and capturing movies in H.264 or MPEG-

4, VGA up to 30 fps

• H.264 video telephony

• Secure devices starting from boot-up through

accessing the corporate network

*Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.

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PXA-310 Processor

1-14Marvell Confidential

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Monahans LV H.264 Video Encode

Display

DDRSDRAM

Unified Memory Architecture uses system DDR SDRAM for core and video acceleration.

Intel® QuickCapture Camera Interface provides hardware based image preprocessing.

LCD controller provides hardware color space conversion for preview.

Marvell® Quick-

Capture

LCD Controller2D Graphics Accelerator

1-21Marvell Confidential

YCbCr 4:2:2Captured

Data

VLC(VariableLengthCoding)

MotionEstimation &

CompensationQ

(Quantization)

ZZ(Zig-Zag)

T(Integer

Transform)

ScalingStore

CompressedBitstream

PreviewColor SpaceConversion

Scaling Display

Marvell® IPP

Marvell® IPP

Video Hardware Accelerator

YCbCr 4:2:0Downsample

Camera Interface

Deblocking

Recurring Encode – Deblock Process

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Monahans LV H.264 Video Decode

Display

DDRSDRAM

Unified Memory Architecture uses system DDR SDRAM for core and video acceleration.

Marvell® IPP

1-22Marvell Confidential

CompressedVideo

10110101011101001111010100

VLD(VariableLength

Decode)

MotionCompensation

IQ(Inverse

Quantization)

IZZ(InverseZig-Zag)

IT(Inverse Transform)

ChromaUpsampling

Color SpaceTransformation Display

I-Frames P-Frames, B-Frames

De-Blocking

Video Hardware Accelerator LCD Controller

PLANAR

YUV420YUV444 RGB

MVD(MotionVector

Decode)

Recurring Decode – Deblock Process

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2222

PXA310 Processor Series Part Numbers

Customers: Due to high demand for parts, place orders now!

! The order number is the same for ES and PPQL parts – be sure to specify if PPQL is needed. Unless PPQL is required, customers should specify “ES” parts in their P.O. so orders are not held up for PPQL parts.

! By using ES parts, customers acknowledge that they have no issues with using pre-production material.

! Marvell standard lead-time is 16 weeks for production material. Sample quantities may take up to 8 weeks. Note: The Marvell order system initially assigns order date + 6 months as the default ship date!

Marvell Part Number Description Security

Module

PXA310 624 MHz discrete

88AP310-A2-BGK2C624-TN02PXA310 Application Processor, A2 stepping, discrete 13x13 mm Green package, auto-boot configuration

Regular part (no WTM)

88AP310-A2-BGK2C624-TS02PXA310 Application Processor, A2 stepping, discrete 13x13 mm Green package, trusted, auto-boot configuration

Yes, Trusted

PXA312 624 MHz package-on-package (PoP) bottom

88AP312-A2-BGW1C624-TN02PXA310 Application Processor, A2 stepping, PoP bottom 15x15 mm RoHS 6/6 package, auto-boot configuration

Regular part (no WTM)

88AP312-A2-BGW1C624-TS02PXA310 Application Processor, A2 stepping, PoP bottom 15x15 mm RoHS 6/6 package, trusted, auto-boot configuration

Yes, Trusted

88AP312-A2-BGW2C624-TN02PXA310 Application Processor, A2 stepping, PoP bottom 15x15 mm Green package (currently not for HVM), auto-boot configuration

Regular part (no WTM)

88AP312-A2-BGW2C624-TS02PXA310 Application Processor, A2 stepping, PoP bottom 15x15 mm Green package (currently not for HVM), trusted, auto-boot configuration

Yes, Trusted

88AP312-01-BGW1C000PXA300 & PXA310 Application Processor PoP bottom 15x15 mm daisy-chain part, LF35.

Regular part (no WTM)

Content Updated: 10.29.07

Ordering tipPlease be

sure to specify

ES or PPQL!

Ordering tipPlease be

sure to specify

ES or PPQL!

Dates, specifications, product descriptions, and plans aresubject to change at any time, without notice.

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232323

PXA310 Processor Series Platform Update

Development platforms and reference designs available! PXA311 A1 Development Kit (DVK) (“Zylonite”) available. Note that the order part #

shows up as DB-(PC)PXA310 due to legacy reasons.

! PXA310 A1 Handheld Platform Development Kit (PDK) (“Littleton”) available

! Hardware platforms are A1 now; A2 revs expected in November

Platform software releases

! Package of BSP, multimedia framework, Marvell® IPP, OpenGL-ES library released periodically for WM6 Professional and Standard (PPC and SP), and Linux

! Update! The November 6 LV A2 platform release did not meet quality criteria after upgrading to WM6.1 (build #19145) and was pulled from release. This release included an early MPEG-2 HW decoder – customers may request it from their FAE. The Nov 20 release will revert to the WM6 adaptation kit, with target of December to switch back to WM6.1 after bug fixes.

! New! WinCE6.0 BSP available for Zylonite, with H.264 & MPEG-2 decode available at final release

! New! Hardware accelerated MPEG-2 Dshow now available under Windows Mobile 6.

! New! WTPTP support for trusted boot using LV parts with WTM available – contact your FAE for details

Ecosystem update! WinCE: For WinCE5.0 support, please contact your local sales representative

! ISVs: See list of several ISVs that have started optimized solutions around the PXA310 h/w video & JPEG acceleration

! IHVs: Please refer to Marvell’s extensive list of pre-enabled solutions, including Digital TV

Documentation update

! New releases: L/LV EMTS v0.98, Specification Update v0.77

! Secure/trusted software documentation available now

Littleton and Zylonite not shown to scale. Littleton

main unit is approximately 116 x 52 x 12.6 (mm)

WinCE6.0 BSP release for LV available now!

LV A2 platform releases to be released in November

WinCE6.0 BSP release for LV available now!

LV A2 platform releases to be released in November

Content Updated: 11.1.07Dates, specifications, product descriptions, and plans are

subject to change at any time, without notice.

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242424

LV A2 reaches

productionmilestone!

PXA310 Processor Series: Silicon & Platform Schedules

Final Platform Release Contents:

Final BSP, WTPTP

Final IPP Primitive and Codec Release

Beta Multimedia Framework (DirectShow Filter 1.1)

Final OpenGL-ES

Alpha Usage Model (Linux only)

Item Silicon Target Date

PXA310 (13mm discrete)

A2 PPQL Avail now

A2 PPQL (not for HVM production) Avail now

A2 ES/PPQL (RoHS 6/6 for HVM) Dec 16/Jan 31

A2 ES/PPQL (green for HVM) Feb 26/Mar 31

PXA312 (15mm PoP bottom)

PXA302/PXA312 PoP daisy-chain, LF35 Avail now

• For part orders, be sure to specify “ES” or “PPQL” quality

• PPQL is production-quality and production-marked with standard Marvell warranty

• Software releases are for regular parts only unless WTM noted

• BSP releases for A2 validated on Zylonite with LV A2 discrete, QVGA and VGA

• BSP was previously validated on PoP using a Toshiba top memory pkg

• All Platform Software releases

available on Marvell Extranet

Item Zylonite Software Release Target WW

WM6Pro/Std Release

A1 final (pass functional LTK tests) Avail now -

A2 platform (WM6.1, MPEG-2 HWA)FAE

request-

A2 platform (WM6.0, NAND lock, OMX IL, MPEG-2 HWA, WMV9 MP)

Nov 20 47.2

A2 final platform (WM6.1, zero bug bounce; full/limited val for no WTM/WTM; pass beta perf target, battery LTK)

Dec 4 49.2

WinCE6.0 Release

A1 alpha BSP candidate Avail now -

A2 alpha BSP (95% feature complete) Nov 20 47.2

A2 beta BSP (A2DP, full IPM, H.264/MPEG-2, VTune) Dec 18 51.2

A2 final BSP (reach ZBB, CETK) Feb 12’08 7.2 ‘08

Linux Release

A1 final release, 2.6.14 and .21 Avail now -

Item Littleton Software Release Target WW

WM6Pro/Std Release

A1 WM6 alpha BSP candidate, v1.1 H/W Avail now -

A2 WM6 alpha BSP (WM6.1, NAND lock on v1.2 H/W) Nov 6 45.2

A2 WM6.1 platform release (WM6.1, incl. WTM) Dec 11 50.2

Linux Release

A1 release, 2.6.14 and .21 Avail now -

A2 alpha BSP release incl. WTM Nov 13 46.2

A2 platform release incl. WTM Dec 18 51.2

Content Updated: 11.1.07Dates, specifications, product descriptions, and plans are

subject to change at any time, without notice.

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PXA AP Packaging & Memory InfoPoP / Memory & Green PXA255, PXA27x + PXA3xx Info

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PoP Technology

Top Memory Module, Supplied by Memory Supplier

1-39Marvell Confidential

Bottom Logic Package Supplied by CHG

Top / Bottom Assembly by Handset Manufacturer during PCB assembly

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3131

PXA3XX NOR-Interface Managed NAND Solutions

Samsung OneNAND

Drivers for PXA32x completed

– PXA320 boot from OneNAND confirmed

PXA31x drivers targeted in October

– PXA310, PXA312 boot from OneNAND confirmed

– Driver port from PXA32x to PXA31x in progress

15x15mm JEDEC PoP available now

– 2Gbit OneNAND/512Mb DDR and 2Gb OneNAND/1Gb DDR

14x14mm JEDEC PoP development started NEW!

– Availability in late January

Sandisk mDOC

Drivers available now from Sandisk

PXA32x and PXA31x boot from mDOC confirmed

– Littleton add-on board showing mDOC boot available from Sandisk (contact [email protected] or +1-425-748-5167)

Benchmarks available from Sandisk

Sandisk asking for volume customer before they will produce 15x15 PoP

– Will take 8 weeks once approved for start

Have plans to support 14x14 PoP for Monahans

Content Verified: 11.1.07Dates, specifications, product descriptions, and plans are

subject to change at any time, without notice.

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3232

PXA3xx Stacking Technology Comparison

This table compares the stacking technologies in the PXA3xx family

MCP (Die stack) PoP Comments

Package size 15mm x 15mm 15mm x 15mm Pin Compatible

ThicknessPXA300: 1.4mm

PXA310: 1.5mm

<=1.5mm total height (assumes top pkg has 2-die stack)

PoP varies depending on Supplier / Density / litho

Memory Density

(NAND / DDR)

PXA300: 1Gb/512Mb

PXA310: 2Gb/1Gb

1G/512, 2G/512, and 2G/1G are currently available at multiple suppliers.

Expect additional PoP combo’s as driven by demand. No plans for additional die stack density

Schedule-L: ES-now, Prod-now -L: ES-now, Prod-Feb

-LV: ES-now, Prod-Q1’08

Some flexibility on PoP schedule based on demand.

Ease of usePre-validated memory. Toshiba PoP pre-validated on LV A1.

Other validation as needed for customer.

More flexibility for architecture and density for PoP.

ManufacturingRobustness

Well understood technology. Newer technology, need top/bottom attach at PCB assembly

Changing PoP material to improve warpage characteristics for HVM.

Software Porting

BSPs for L/LV Zylonite currently validated for die stack

BSP for LV Zylonite validated on LV PoP (using Toshiba memory package) available. NOR-interface NAND drivers from vendors.

BSP porting effort for LV PoP should be minor – same as using LV discrete + NAND vendor

CustomerConsiderations

Can be used for pre-enabling for PoP. NOT for channel customers. LV customers should use PoP.

Good for phone customers who need reduced board footprint. Recommended for ease of migration to next-generation AP/memory.

MCP not for channel customers due to shorter lifespan of memory. LV customers should use PoP if a stacked part is needed.

Content Updated: 10.30.07Dates, specifications, product descriptions, and plans are

subject to change at any time, without notice.

Red = change from Oct’07

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3232

PXA3xx Stacking Technology Comparison

This table compares the stacking technologies in the PXA3xx family

MCP (Die stack) PoP Comments

Package size 15mm x 15mm 15mm x 15mm Pin Compatible

ThicknessPXA300: 1.4mm

PXA310: 1.5mm

<=1.5mm total height (assumes top pkg has 2-die stack)

PoP varies depending on Supplier / Density / litho

Memory Density

(NAND / DDR)

PXA300: 1Gb/512Mb

PXA310: 2Gb/1Gb

1G/512, 2G/512, and 2G/1G are currently available at multiple suppliers.

Expect additional PoP combo’s as driven by demand. No plans for additional die stack density

Schedule-L: ES-now, Prod-now -L: ES-now, Prod-Feb

-LV: ES-now, Prod-Q1’08

Some flexibility on PoP schedule based on demand.

Ease of usePre-validated memory. Toshiba PoP pre-validated on LV A1.

Other validation as needed for customer.

More flexibility for architecture and density for PoP.

ManufacturingRobustness

Well understood technology. Newer technology, need top/bottom attach at PCB assembly

Changing PoP material to improve warpage characteristics for HVM.

Software Porting

BSPs for L/LV Zylonite currently validated for die stack

BSP for LV Zylonite validated on LV PoP (using Toshiba memory package) available. NOR-interface NAND drivers from vendors.

BSP porting effort for LV PoP should be minor – same as using LV discrete + NAND vendor

CustomerConsiderations

Can be used for pre-enabling for PoP. NOT for channel customers. LV customers should use PoP.

Good for phone customers who need reduced board footprint. Recommended for ease of migration to next-generation AP/memory.

MCP not for channel customers due to shorter lifespan of memory. LV customers should use PoP if a stacked part is needed.

Content Updated: 10.30.07Dates, specifications, product descriptions, and plans are

subject to change at any time, without notice.

Red = change from Oct’07

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33

NAND/DDR PoP: 15x15 JEDEC Status PXA300 & 310

Supplier15x15 JEDEC

(NAND/DDR)

ES MassProd

z-ht(max)

Comments

Toshiba(Note changes to reflect new litho and monolithic 1Gb DRAM)

2Gb / 512MbTY9000B000CHHL

2Gb / 1GbTYA000B000AHHL

Now

Now

Now

Now

0.96mmFunctional in system.

Board level reliability study underway with Toshiba DC.

Samsung(OneNAND / LP DDR)

2Gb / 512MbK5W2G12ACM-DL75000

2G / 1GK5W2G1HACM-DL75000

Now Q4’07 1.0mmNeed discussions with Samsung Semi on software schedule. Driver currently in porting phase from MH-P to MH-LV.

ST Micro

2Gb / 512MbNANDB9R4N2AZPB5E

2Gb / 1GbNANDBAR4N2AZNB5E

4Gb / 1GbNANDCAR4N2AZPB5E

Now

Dec’07

Q4‘07

N/A

Q2’08

Q1‘08

1.2mm

1.0mm

1.0mm

Functional in system.

1.0mm body is needed for compatibility to our product

Hynix

2Gb / 512MbHYD0SSG0MF5P-5L60E

2Gb / 1GbH8KCS0SI0MAP-56M

NowNow

Nov’081.0mm

PoP is functional in system. DC available now.

FOR REFERENCE ONLY: Please check with

Memory supplier for latest updates

Content Updated: 11.1..07

Red = change from Oct’07

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Marvell PXA320 Processor SeriesMonahans P

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3737

PXA320 Processor Overview

Dates, specifications, product descriptions, and plans are subject to change at any time, without notice.Content Verified: 10.30.07

Key Benefits:

• 624 & 806 MHz

• 32-Bit DDR Support

• 256 KB L2 Cache

• 768 KB SRAM

• WinCE, Windows Mobile &

Linux BSPs available

• Development Systems

available

• In Production Now!

PXA320 is the ideal choice for the highest performing segments

in Handheld Point-of-Sale, Mobile Computing and Military Devices

PXA320 is the highest performing solution in its class, scaling up to 806

MHz with power-efficient computing performance, including 32-Bit DDR

Support and 256 KB L2 Cache for today’s handheld mobile devices.

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PXA-320 Processor

1-12Marvell Confidential

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3838

PXA320 Silicon Part Numbers

Content Verified: 10.30.07.

Discrete (14x14mm, vfBGA)

Order Part Number Frequency Temp Power Core Vcc Config Boot Config

RTPXA320B2C624-641 624 MHz Commercial Low 1.375 VDC CFG4A x16 NOR

RTPXA320B2C806-337 806 MHz Commercial Standard 1.400 VDC CFG4B x16 NOR

RTPXA320B2C624-640 624 MHz Commercial Low 1.375 VDC CFG1A x16 NAND

RTPXA320B2C806-646 806 MHz Commercial Standard 1.400 VDC CFG1B x16 NAND

RTPXA320B2C624-642 624 MHz Commercial Low 1.375 VDC CFG2A x8 NAND

RTPXA320B2C624-696 624 MHz Commercial Standard 1.375 VDC CFG2B x8 NAND

RTPXA320B2C806-643 806 MHz Commercial Standard 1.400 VDC CFG2B x8 NAND

RTPXA320B2E806-644 806 MHz Extended Standard 1.400 VDC CFG2B x8 NAND

Please contact your Marvell Sales Representative for more information

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3939

PXA320 Platform Information

Development Platform available … PXA320 Development Kit (DVK - “Zylonite”) & Processor Cards

– System – Order #DB-PXA320B2

– Processor Card – Order #DB-PCPXA320B2

Due to high demand, place your orders as soon as possible

Current lead time is ~ 2 weeks

Platform Software Releases … Windows Mobile® 6.0 Classic (PPC, without phone support)

– BSP available only from Microsoft; it is not distributed by Marvell

Windows Mobile® 5.0 – Available on the Marvell Extranet

– PXA320_B1 Platform DVK WM5.0, PPC BSP Beta Patch (V4.3.2.1.1)

– PXA320_B2 WM5.0 PPC Bring-Up Guide

WinCE 6.0 – Target Availability = Q1 CY’08

– For earlier solutions, BSquare solution is available (see slide later in this presentation for more information)

Linux – Available on the Marvell Extranet

– PXA320_B2 Platform DVK Linux Preview Kit (Kernel 2.6.14) Beta Patch (V4.5.4)

Documentation available on the Marvell Extranet … https://www.marvell.com/login/index.jsp

Content Verified: 10.30.07