introduction to fpgas · 2019-03-05 · •fpga architecture: survey and challenges –ian kuon,...
TRANSCRIPT
![Page 1: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/1.jpg)
Introduction to FPGAs
Madhura Purnaprajna
![Page 2: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/2.jpg)
Outline
• What’s different about FPGAs
• Architecture
– Logic
– Routing
– I/O
• State-of-the-art: Xilinx Virtex 7
![Page 3: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/3.jpg)
The Applications ...
3
Medical
Consumer
High Performance Computing
Communications
![Page 4: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/4.jpg)
The Industry ...
4
![Page 5: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/5.jpg)
The two domains ...
5
![Page 6: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/6.jpg)
Processors
• Sequential computing
• Instruction-level parallelism
6
ALU
Registers
Instruction Memory
Decoder
Data Memory
Registers
![Page 7: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/7.jpg)
FPGAs
• User configurable
• User-defined parallelism
7
00 0 01 1 10 1 11 1
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
![Page 8: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/8.jpg)
Application Mapping
8
Processor FPGA
N
< N
![Page 9: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/9.jpg)
Temporal vs Spatial Computing
9
ALU
Registers
Instruction Memory
Decoder
Data Memory
Registers
Processor FPGA
User-defined parallelism Flexibility Performance per Watt
x Limited parallelism x Fixed architecture x Scalability?
00 0 01 1 10 1 11 1
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
FU
FFs
![Page 10: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/10.jpg)
Performance vs Adaptability
10
ASIC
Ease
of
Ad
apta
bili
ty
Performance
FPGA
Processors
~35x Area
~5x Speed
~15x Power
Measuring the gap between FPGAs and ASICs, Ian Kuon and Jonathan Rose, FPGA 2006
![Page 11: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/11.jpg)
FPGA Architecture
11
Programmable Logic
Programmable Routing
![Page 12: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/12.jpg)
Logic: Lookup Tables
12
LUT FF
LUT FF
LUT FF
LUT FF
2K:1
MUX
2K
SRAM
K
Slice/Cluster
![Page 13: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/13.jpg)
Look-up Table
• 2K SRAM Cells
• 22K different functions
• 2K:1 MUX
– K-levels of 2:1 muxes
13
2K:1
MUX
2K
SRAM
K
![Page 14: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/14.jpg)
Look-up Table: 2-inputs
• 22 SRAM Cells
• 222 different functions
• 22:1 MUX
– 2-levels of 2:1 muxes
14
22:1
MUX
22
SRAM
2
![Page 15: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/15.jpg)
Look-up Table: 2-input NAND
• 4 SRAM Cells
– 6 transistors each
• 4:1 MUX
– ~12 transistors
• ~40 Transistors
15
4:1
MUX
1 1 1 0
2
![Page 16: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/16.jpg)
Look-up Table: 2-input NAND
16
4:1
MUX
1 1 1 0
2
4 Transistors
HUGE!
40 Transistors
![Page 17: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/17.jpg)
Design Flow: FPGA
17
HDL
Logic Synthesis
Technology Mapping
Pack, Place & Route
FPGA
Benchmark Circuits
FPGA Architecture
Area, Power, Speed
![Page 18: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/18.jpg)
LOGIC BLOCK ARCHITECTURE
![Page 19: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/19.jpg)
Logic: Soft
19
Programmable Logic Blocks
![Page 20: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/20.jpg)
Logic: Hard Blocks
20
Memory Blocks
![Page 21: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/21.jpg)
Logic: Hard Blocks
21
DSP Blocks
![Page 22: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/22.jpg)
Logic: Lookup Tables
22
LUT FF
LUT FF
LUT FF
LUT FF
2K:1
MUX
2K
SRAM
K
Slice/ Cluster
![Page 23: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/23.jpg)
Design decisions
• LUT size
• Number of LUTs per cluster
• Inputs/Outputs to/from each cluster
• Area and Speed
![Page 24: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/24.jpg)
No. of Logic Blocks vs. Logic Block Functionality
• LUT size increases exponentially with K • Routing tracks surrounding logic increases with the number of input pins
![Page 25: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/25.jpg)
Total FPGA area vs. LUT size
![Page 26: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/26.jpg)
Terminology
• Basic logic element (BLE)
• Cluster
– Size grows quadratically
– Local interconnect
– Fewer inputs (shared)
LUT FF
LUT FF
LUT FF
LUT FF
![Page 27: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/27.jpg)
LUTs on critical path & LUT delay vs LUT size
Functionality increases=> fewer logic blocks on critical path => internal delay increases
![Page 28: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/28.jpg)
Critical path: Function of LUT and Cluster size
Diminishing returns beyond LUT6 and cluster size 3,4
![Page 29: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/29.jpg)
HETEROGENEOUS BLOCKS
![Page 30: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/30.jpg)
Choice of functions
• Which function?
• Ratio of special function to generic logic?
• What to do with special function blocks when they are not used?
![Page 31: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/31.jpg)
Hard blocks
• FFs (set, reset, enable, load,…)
• Add, sub, carry logic, …
• Use LUTs as memories
• Block RAMs/ ROMs, FIFOs
• Multipliers (fracturable)
• Processors
![Page 32: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/32.jpg)
Challenge
• Performance, power, area
– As compared to ASICs
• Introduce other hard blocks
– Floating point units, etc.
• Shadow logic
![Page 33: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/33.jpg)
ROUTING ARCHITECTURE
![Page 34: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/34.jpg)
Routing in FPGAs
• Connect logic blocks and I/O
– To define a user circuit
• Flexible
– Support local and distant routing demands
• Locality
– Short, Fast, with intermediate long wires
• Global clocks and resets
![Page 35: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/35.jpg)
Routing details
• Global routing
– Macroscopic allocation of wires
– Relative position of routing channels to logic blocks
– Wires in each channel
• Detailed routing
– Microscopic
– Length of wires
– Switching quantity
![Page 36: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/36.jpg)
Routing Architectures
• Hierarchical
• Island style
![Page 37: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/37.jpg)
Hierarchical Routing
• Groups of logic blocks
• Interconnected levels
• Used in:
– Altera FLEX, APEX
![Page 38: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/38.jpg)
Hierarchical Routing
• Advantages:
– Predictable inter-logic block delay
– Superior performance for some designs
• Disadvantages:
– Over use of logic blocks (mismatch in design and FPGA hierarchy)
– Large variation in inter-block delay
![Page 39: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/39.jpg)
Island style
• 2-D mesh: evenly distributed routing resources
• routing channels on four sides
• Each channel has W wires • Wire segments of
different lengths in each channel
• Used in present day commercial FPGAs
![Page 40: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/40.jpg)
Island style
• Advantages:
– Efficient connection for varying net lengths
– Staggering start/end points, optimise for a tile
– Regular, min delay can be estimated
![Page 41: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/41.jpg)
Details
Connection blocks
Switch blocks
![Page 42: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/42.jpg)
Channel segmentation distribution
• Short wires: 1 block • Long wires: Multiple blocks
![Page 43: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/43.jpg)
Routing hops
![Page 44: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/44.jpg)
Switch block: disjoint
• Numerical designation of wire entering = wire exiting
• 0-0
• 1-1
• …
• Limits flexibility
• Distinct routing domains
![Page 45: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/45.jpg)
Switch block: Wilton
• Allows change in domains for turns
• 0(left)-3(bottom)
• 0(left)-0(top)
![Page 46: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/46.jpg)
I/O STANDARDS
![Page 47: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/47.jpg)
I/O Architecture
• Sets external interface rates
• Occupies significant area
– ~40%
• Choice of I/O standard
– Performance (Pin capacitance)
– Area
![Page 48: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/48.jpg)
Common I/O Standards
![Page 49: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/49.jpg)
Selection
• I/O banks
– Groups of I/O cells
– Share supply/reference voltage
– Each bank has different I/O standard
![Page 50: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/50.jpg)
Highspeed I/O
• High speed inter-chip signaling
– SERDES (serialiser/deserialiser)
• Source sync clocking
• Dynamic clock phase adjustment
• High-bandwidth memory interface
– Ethernet MAC
– DLLs/PLLs
![Page 51: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/51.jpg)
PROGRAMMING TECH
![Page 52: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/52.jpg)
Programming Technology
• SRAM Cells
– Reusability
– Standard CMOS
![Page 53: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/53.jpg)
Programming Technologies
![Page 54: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/54.jpg)
Improving FPGAs
• Reducing the gap: Area, Speed, Power
• Alternatives to FPGAs
– CGRAs
– Structured ASICs
![Page 55: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/55.jpg)
References
• FPGA Architecture: Survey and Challenges
– Ian Kuon, Russell Tessier, Jonathan Rose
![Page 56: Introduction to FPGAs · 2019-03-05 · •FPGA Architecture: Survey and Challenges –Ian Kuon, Russell Tessier, Jonathan Rose . Questions? Title: PowerPoint Presentation Author:](https://reader034.vdocuments.site/reader034/viewer/2022050103/5f41d31af638ec4a246efa4d/html5/thumbnails/56.jpg)
Questions?