introduction to digital logic - missouri university of...

© Egemen K. Çetinkaya

Introduction to Digital Logic Missouri S&T University CPE 2210

Multipliers/Dividers

Egemen K. Çetinkaya

Department of Electrical & Computer Engineering

Missouri University of Science and Technology

[email protected]

http://web.mst.edu/~cetinkayae/teaching/CPE2210Fall2016

11 November 2016 rev. 16.0 © 2014–2016 Egemen K. Çetinkaya


Multipliers/Dividers Outline

• Introduction

• Multipliers

• Dividers

• ALUs

• Summary

MST CPE2210 – Multipliers/Dividers 11 November 2016 2


Digital Logic Systems Overview

• Combinatorial logic circuits for no memory systems

– Boolean algebra to mathematically design/analyze

– logic gates are building blocks

• Sequential logic circuits for memory systems

– Finite State Machines to mathematically design/analyze

– flip-flops and latches store memory

• flip-flops and latches are building blocks of sequential logic

• Sequential logic circuits (aka controllers) combine

– combinatorial circuits

– storage elements (e.g. registers)



Digital Systems Components

• Transducer: sensor + actuator

• Not all sensors/actuators require A2D/D2A conversion

• Digital system can be implemented:

– microprocessor

• readily available, cheap, easy to program, easy to reprogram

– custom circuit

• smaller, faster, consume less power

11 November 2016 MST CPE2210 – Multipliers/Dividers 4

sensors and other inputs

Digital System

actuators and other outputs

A2D

D2A

analog phenomena

electric signal

digital data

digital data

electric signal

digital data

digital data


Digital Systems Paths

• Digital systems have two paths:

– datapath circuit

– control circuit

• Datapath circuit

– store data

– manipulate data

– transfer data from one part to another

• Control circuit

– controls the operation of datapath circuit



Datapath Components Building Block examples

• Registers

• Shifters

• Counters/timers

• Multiplexer/demultiplexers

• Decoders/encoders

• Adders

• Comparators

• Subtractors

• Multipliers/dividers

• ALUs: Arithmetic Logic Units



Adders Half-Adder

• Adds two bits, generates sum bit and carry-out bit

• Lets try to design the circuit:

• Next steps?

• Implement as a circuit

co = ab, s = a b


b

c o s

0

a ci

A:

B: + 0

1 1 1 1

1

1

b

c o s

1

a ci

1

1

b

c o s

0

a ci

1

0

b

c o s

1 SUM

a

0

a b

co s

co s

a b

Half-adder

(HA)


Adders Full-Adder

• Adds three bits, generates sum bit and carry-out bit

• Lets try to design the circuit:

• Next steps?

• Implement as a circuit

• co = ab + ac + bc

• s = a b c


c o

ci b a

s

Full

adder

(FA)

co s

a b

Full-adder

(FA)

ci


Adders Carry-Ripple Adder

• Carry-ripple adder: Uses half- and full-adders

• E.g.: 4-bit carry-ripple adder

– can build any size adder based on full- and half-adders


a3

c o s

F A

c o

b3 a2 b2

s3 s2 s1

ci b a

c o s

F A

ci b a

a1 b1

c o s

F A

ci b a

s0

a0 b0

c o s

HA

b a

a3 a2 a1 a0 b3

s3 s2 s1 s0 c o

b2 b1 b0

4-bit adder


Adders Carry-Ripple Adder

• Carry-ripple adder: Can also use only full-adders

• E.g.: 4-bit carry-ripple adder


a3

c o s

F A

c o

b3 a2 b2

s3 s2 s1

ci b a

c o s

F A

ci b a

a1 b1

c o s

F A

ci b a

s0

a0 b0 ci

c o s

F A

ci b a a3 a2 a1 a0 b3

s3 s2 s1 s0 c o

ci

b2 b1 b0

4-bit adder


Comparison Half-Adder vs. Half-Subtractor

• HA operation: a+b

• s = a b

• co = ab


a b

co s

co s

a b

Half-adder

(HA)

• HS operation: b−a

• D = a b

• B = b’a

a b

B D

B D

a b

Half-

subtractor


Comparison Full-Adder vs. Full-Subtractor

• FA operation: a+b+c

• s = a b c

• co = ab + ac + bc


• FS operation: b−a−Bi

• D = b a Bi

• Bo = b’ (a Bi) + aBi

c o

ci b a

s

Full

adder

(FA)

B o

Bi b a

D

(FS)


Subtractors Subtraction via 2’s Complements

• Subtraction via adding 2’s complement

• A B = A + (B)

• A B = A + (2’s complement of B)

• A B = A + (inverted B + 1)


1 cin

B A Adder

S

B A

N-bit


Shift Register Shift Left Operation Example

• Lets shift left one


0 1 1 0 1 1 0 1




• After moving one bit to left?


0 1 1 0 1 1 0 1




• After moving one bit to left

• dropped the MSB added 0 for LSB


0 1 1 0 1 1 0 1

1 1 0 1 1 0 1 0



• Lets shift left 2-bits

• After first shift left

• After second shift left


0 1 1 0 1 1 0 1







0 1 1 0 1 1 0 1

1 1 0 1 1 0 1 0







0 1 1 0 1 1 0 1

1 1 0 1 1 0 1 0

1 0 1 1 0 1 0 0



• What was the arithmetic operation we just did?




• Shift left n-bits will multiply by 2n



Shift Register Shift Right Operation Example

• Lets shift right one


0 1 1 0 1 1 0 1




• After moving one bit to right?


0 1 1 0 1 1 0 1




• After moving one bit to right

• Added 0 for MSB dropped the LSB


0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 0



• Lets shift right 2-bits

• After first shift right

• After second shift right


0 1 1 0 1 1 0 1







0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 0







0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 0

0 0 0 1 1 0 1 1



• What was the arithmetic operation we just did?




• Shift right n-bits will divide by 2n



Division via Shift Signed Number Example

• Previous examples were unsigned numbers

• Need to preserve the sign for signed numbers

• Consider A = 24 = 011000

• A/2 = 24/2 = 12 = 001100

• A/4 = 24/4 = 6 = 000110

• Consider A = −24 = 101000

• A/2 = −24/2 = −12 = 110100

• A/4 = −24/4 = −6 = 111010



Multipliers Multiplication Operation

• Multiplication product via multiplicand and multiplier


1 1 1 0

1 1 1 0

1 0 1 1

1 1 1 0

0 0 0 0

1 1 1 0

1 0 0 1 1 0 1 0

Multiplicand M

Multiplier Q

Product P

(14)

(11)

(154)


Multipliers Multiplication Operation

• Multiplication results in partial products


1 1 1 0

1 1 1 0

1 0 1 1

1 1 1 0

1 0 0 1 1 0 1 0

Multiplicand M

Multiplier Q

Product P

(14)

(11)

(154)

+

1 0 1 0 1

0 0 0 0 +

0 1 0 1 0

1 1 1 0 +

Partial product 1

Partial product 2

Partial product 3


Multiplier Circuit Array Style Multiplier

• Multiplication by hand can be mimicked




• Generalized representation of multiplication by hand





A B

P ×

Block symbol

+ (5-bit)

+ (6-bit)

+ (7-bit)

0 0

0 0 0

0

a0 a1 a2 a3

b0

b1

b2

b3

0

p7..p0 pp1

pp2

pp3

pp4


Dividers Division Operation

• Dividend divided by divisor resulting in Q and R


9 140 9

50 45

5

15 100

10 10

01100 1001

00001111

1001

001 01

10000 1001

1110 1001

101

Quotient

Dividend Divisor

Remainder


• A/B produces Q and R

Divider Circuit Array Style Divider


The most significant bit of the

dividend A then becomes the

least significant bit of R. The

divisor B is repeatedly

subtracted from this partial

remainder to determine

whether it fits.

More info [HH2013] [EL2004]


ALUs Arithmetic Logic Units

• Arithmetic Logic Unit (ALU)

• ALUs performs Boolean and arithmetic functions

• Performs operations on n-bit operands

– e.g. 4-bit addition, subtraction

– e.g. 8-bit addition, subtraction

• Functions include on TI 74S381 ALU chip:

– Clear, A−B, A+B, XOR, OR, AND, Preset



Multipliers/Dividers Summary

• Many multipliers design exists

• Division is a slow and expensive operation

• Need to preserve the sign for signed numbers

– when doing multiplication/division via shifting

• ALUs performs Boolean and arithmetic functions



References and Further Reading

• [V2011] Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd edition, Wiley, 2011.

• [BV2009] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd edition, McGraw-Hill, 2009.

• [G2003] Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003.

• [HH2013] David Harris and Sarah Harris, Digital Design and Computer Architecture, 2nd edition, Morgan Kaufmann, 2013.

• [EL2004] Miloš D. Ercegovac and Tomás Lang, Digital Arithmetic, 1st edition, Morgan Kaufmann, 2004.



End of Foils


introduction to digital logic - missouri university of...

Documents