Introduction to Computer

Organization•What is inside a computer?•How does it execute my

program?

?

I/O Bus

Memory Bus

Processor

Cache

MainMemory

DiskController

Disk Disk

GraphicsController

NetworkInterface

Graphics Network

interrupts

System Organization

I/O Bridge

Core Chip Set

What is Computer Architecture?• Coordination of levels of abstraction

I/O systemCPU

Compiler

OperatingSystem

Application

Digital Design

Circuit Design

• Under a set of rapidly changing Forces

Instruction SetArchitecture, Memory, I/O

Firmware

Memory

Software

Hardware

Interface BetweenHW and SW

I/O systemProcessor

CompilerOperatingSystem

(Windows 98)

Application (Netscape)

Digital DesignCircuit Design

Instruction Set Architecture

• Coordination of many levels of abstraction

Datapath & Control

transistors

MemoryHardware

Software Assembler

Computer System: Layers of Abstraction

SoftwareHardware

Application Program

Language

Instruction Set Architecture (and I/O Interfaces)

Microarchitecture

Circuits

Devices

Algorithms

Levels of RepresentationHigh Level Language

Program

Assembly Language Program

Machine Language Program

Control Signal Specification

Compiler

Assembler

Machine Interpretation

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw $15,0($2)

lw $16,4($2)

sw $16,0($2)

sw $15,4($2)

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

5 5 5

Rw Ra Rb

32 32-bitRegisters

Rs

Rt

Don’t Care(Rt)

Rd

RegDst

Extender

Mux

Mux

3216

imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data InWrEn

32

Adr

DataMemory

32

AL

U

MemWr

Universal Computing Device•All computers, given enough

time and memory,are capable of computing exactly the same things.

= =PDA

WorkstationSupercomputer

PDA (Personal Digital Assistant)

Evolution of Multilevel Machines• Bare hardware

• Microprogramming• Operating system• Compilers• Hardware / software

interface– Simple ISA– CISC– RISC– EPIC (Explicitly Parallel

Instruction Computing)

• RISC and CISC designs– Reduced Instruction Set Computer

(RISC)• Uses simple instructions• Operands are assumed to be in

processor registers– Not in memory– Simplifies design

» Example : Fixed instruction size– Complex Instruction Set Computer

(CISC)• Uses complex instruction• Operands can be in registers or

memory– Instruction size varies

• Typically uses a microprogram

Computer Organization

Processor

Von Neumann Machine

Accumulator หน่�วยความจำ�าส่�วน่ที่��ใช้�เก็�บผลที่��ได้�จำาก็ก็าร ค�าน่วณ โด้ยเก็�บเอาไว�ใน่ตำ�าแหน่�ง ของ register

Processor Module

External Cache

DatapathRegisters

InternalCache

Control

Processor

Processor and Caches

To main memory

Datapath

Memory

I/O

Bus-Based Computer

Anatomy of a Modern PC

(Peripheral Component Interconnet)

(Industry Standard Architecture)

Multiprocessors

Forces on Computer Architecture

ComputerArchitecture

TechnologyProgrammingLanguages

OperatingSystems

History

Applications

(A = F / M)

Applications and Languages•CAD, CAM, CAE, . . .•Lotus, DOS, . . . •Multimedia, . . .•The Web, . . .•JAVA, . . .•The Net => ubiquitous

computing•???

Where are We Going??

מבנהמחשבים

µProc60%/yr.(2X/1.5yr)

DRAM9%/yr.(2X/10 yrs)1

10

100

1000

19

80

19

81

19

83

19

84

19

85

19

86

19

87

19

88

19

89

19

90

19

91

19

92

19

93

19

94

19

95

19

96

19

97

19

98

19

99

20

00

DRAM

CPU

19

82

Processor-MemoryPerformance Gap:(grows 50% / year)

Per

form

anc

e

Time

“Moore’s Law”

34-b it A LU

LO register(16x2 bits)

Load

HI

Cle

arH

I

Load

LO

M ultiplicandRegister

S h iftA ll

LoadM p

Extra

2 bits

3 232

LO [1 :0 ]

Result[H I] Result[LO]

32 32

Prev

LO[1]

Booth

Encoder E N C [0 ]

E N C [2 ]

"LO

[0]"

Con trolLog ic

InputM ultiplier

32

S ub /A dd

2

34

34

32

InputM ultiplicand

32=>34sig nEx

34

34x2 M U X

32=>34sig nEx

<<13 4

E N C [1 ]

M ulti x2 /x1

2

2HI register(16x2 bits)

2

01

3 4 ArithmeticSingle/multicycle

Datapaths

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

Pipelining

Memory Systems

I/O