introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/cad/introduction.pdf · cs&rsoc...
TRANSCRIPT
![Page 1: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/1.jpg)
Introduction
Sungho Kang
Yonsei University
![Page 2: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/2.jpg)
2CS&RSOC YONSEI UNIVERSITY
Outline
VLSIDesign StylesOverview of Optimal Logic SynthesisModelGraph Algorithm and ComplexityAsymptotic ComplexityBrief Summary of MOS Device Behavior
![Page 3: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/3.jpg)
3CS&RSOC YONSEI UNIVERSITY
VLSIVLSI
Manufacturing TechnologyMinimum length of MOS channelsThe number of interconnection layers
Design TechnologyCAD tools
Why VLSINew marketsOperation speedProtection investments in design
![Page 4: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/4.jpg)
4CS&RSOC YONSEI UNIVERSITY
Design StyleDesign Style - Decomposition
Behavioral SynthesisResource allocation; Pipelining; Control flow parallelization; Communicating Sequential Processes; Partitioning
Sequential SynthesisRegister Movement and Retiming; State Minimization; State Assignment; Synthesis for Testable FSM’s; State Machine Verification
Logic SynthesisExtraction of combinational logic to HDL; Two-level minimization; Algebraic Decomposition; Multilevel Logic Minimization; Synthesis for Multi-fault Testability; Test Generation via Minimization; Technology mapping; Timing optimization
Technology MappingMapping to Library of Logic Gates; Timing Optimization
Physical Design SynthesisCell Placement; Routing; Fabrication; Engineering Changes
![Page 5: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/5.jpg)
5CS&RSOC YONSEI UNIVERSITY
Design StyleLogic Design Styles
Full custom designEvery circuit part is especially optimized for the purpose it must serve in the design
Semi-custom designThe circuit is designed by assembling pre-designed and pre-characterized sub-circuitsManufacturing may use a pre-diffused substrate
Programmed designThe design is obtained by programming a standard partSome circuits may be programmed only once while others may be programmed an unlimited number of times
![Page 6: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/6.jpg)
6CS&RSOC YONSEI UNIVERSITY
Design StyleDesign Methodology
CELL-BASED ARRAY-BASED
SEMICUSTOM
MACRO CELLS
Generatiors: Memory PLA Sparse logic Gate matrix
PREDIFFUSED
Gate arrays Sea of gates Compacted arrays
STANDARDCELLS
Hierarchical cells
PREWIRED
Anti-fuse based Memory-based
![Page 7: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/7.jpg)
7CS&RSOC YONSEI UNIVERSITY
SOC DesignSOC Design Paradigm
Emergence of Very large transistor counts on a single chipMixed technologies on the same chip
Logic, Analog, Memory, ProcessorCreation of Intellectual Property (IP)Reusable core-based design
Cores replacing standard parts, such as DSP, DRAM, MCU, Flash, and FPGA
![Page 8: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/8.jpg)
8CS&RSOC YONSEI UNIVERSITY
SOC DesignSOC Evolution
OriginalDesignBlock
OriginalDesignBlock
UserDefinedLogic(UDL)
SRAM
ROM
OriginalDesignBlock
uP(IP Core)
UserDefinedLogic(UDL)
DRAM
Analog
ROM
ATM(IP Core)
MPEG(IP Core)
ASIC
Block-Based SOC
Core-Based SOC
![Page 9: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/9.jpg)
9CS&RSOC YONSEI UNIVERSITY
SOC DesignIP Core types
Hard Core(Technology dependent layout)Predictable area and performanceLack flexibility
Soft Core(RTL)leave much of the implementation to the designerFlexible and process-independent
Firm Core(Netlist)
Each type of core has different modeling and test requirements
![Page 10: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/10.jpg)
10CS&RSOC YONSEI UNIVERSITY
Logic SynthesisDesign Tradeoffs
Factors to be optimized in chip design:AreaDelayPowerTestability
These competing objectives require Tradeoffs
Synthesis tools automate tradeoffAccording to the commands used by the designer, area or delay (or power, or testability) is reduced
![Page 11: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/11.jpg)
11CS&RSOC YONSEI UNIVERSITY
Logic SynthesisArea vs Delay:The Bit-Serial Adder
A typical tradeoff is area versus delayWith just one full adder, this circuit can do 32-bit additionBut, it is 32x slower than a parallel adder (32 full adders, 1 bit output per clock cycle)
![Page 12: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/12.jpg)
12CS&RSOC YONSEI UNIVERSITY
Logic SynthesisDesign Tradeoff Curve
Holding other factors constant, the Area vs Delay tradeoff curve is typically parabolicThe first design requirement is meet Constraints on Chip Area and Critical Path Delay (0 to 1)
![Page 13: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/13.jpg)
13CS&RSOC YONSEI UNIVERSITY
Logic SynthesisDesign Tradeoffs
The next priority is to optimize a feasible designDesign 2 is optimal, in the sense that area and delay cannot both be decreased from this pointTradeoff is now necessary, according to policy
![Page 14: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/14.jpg)
14CS&RSOC YONSEI UNIVERSITY
Logic SynthesisDesign Tradeoffs
A typical design policy is to optimize area subject to a delay constraint (2 to 3)Often a preferred policy is to optimize delay subject to an area constraint (2 to 4)
4
![Page 15: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/15.jpg)
15CS&RSOC YONSEI UNIVERSITY
Logic SynthesisPrioritizing Testability
Sometimes other factors, such as testability or power, take priorityTypically this moves the area-delay tradeoff curve up and to the rightThus designs 1 and 2 are optimal
![Page 16: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/16.jpg)
16CS&RSOC YONSEI UNIVERSITY
Logic SynthesisArea Optimization
Typically performed in a technology independent view of the circuitIn this view gates are regarded as logic functionsThese functions are converted to physical gates by Technology Mapping
![Page 17: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/17.jpg)
17CS&RSOC YONSEI UNIVERSITY
Logic SynthesisTechnology Independent View
In this view the gates of the full adder circuit are just logic equations
a = xi yib = xi’ yi’e = a’ b’zi = eci-1‘ +e’ci-1c = xi yid = xi + y + i f = dci-1ci = c + f
![Page 18: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/18.jpg)
18CS&RSOC YONSEI UNIVERSITY
Logic SynthesisOptimization and Technology Mapping
Common subfunctions sharedFunctions “Technology Mapped” to negative gates
![Page 19: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/19.jpg)
19CS&RSOC YONSEI UNIVERSITY
Logic SynthesisTesting
Faults ModelsStuck-at faultsDelay faults
Test vectorsFault simulationAutomatic test pattern generation
DiagnosisTestable Design
![Page 20: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/20.jpg)
20CS&RSOC YONSEI UNIVERSITY
Logic SynthesisDelay Optimization
First step is to identify the Critical PathSimplest delay model: “number of logic levels”
![Page 21: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/21.jpg)
21CS&RSOC YONSEI UNIVERSITY
Logic SynthesisCritical Path Analyzers
Static Delay Models:Levels of LogicDelay function of size, load Worst, best case models
Dynamic Delay ModelsSimplified device modelsFull Spice analysis
![Page 22: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/22.jpg)
22CS&RSOC YONSEI UNIVERSITY
Model GenerationModel
BehavioralRepresents the behavior of the systemBehavior can be specified as a mapping of logic values or of data words, etc.Functional model is a representation of its logic functionBehavioral model consists of a function model with a representation associated with timing relationsAdvantages from the separation between function and timing
Circuits with the same function but different timingFunction and timing can be dealt in design verification
Structural Collection of interconnected elementsPrimitive elementsBlock diagram : CPU, RAM, etcSchematic diagram : AND, OR etc
![Page 23: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/23.jpg)
23CS&RSOC YONSEI UNIVERSITY
Model GenerationModel
ExternalModel viewed by the userGraphic or text-basedHDL (Hardware Description Language)RTL (Register Transfer Level)
InternalData structures and programs inside
![Page 24: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/24.jpg)
24CS&RSOC YONSEI UNIVERSITY
Model GenerationTruth Tables
Simplest wayn variables requires 2n entry
X1 X2 Y0 0 00 1 01 0 01 1 1
![Page 25: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/25.jpg)
25CS&RSOC YONSEI UNIVERSITY
Model GenerationCube
A cube of Z(x1,x2,x3) has the form (v1,v2,v3|vz) where vz=(v1,v2,v3) An implicant of g of Z can be represented by a cube constructed
Set vi=1(0) if xi(xi’) appears in g Set vi=x if neither xi nor xi’ appears in g Set vz=1
If the cube q can be obtained from the cube p by replacing one or more x values in p by 0 or 1 then p covers q Primitive cube
Cube representing a prime implicantPrimitive cubes provide a compact representation of a function
![Page 26: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/26.jpg)
26CS&RSOC YONSEI UNIVERSITY
Model GenerationIntersection Operator
Inconsistency : ∅Consistency : Except ∅
Compatible Values whose intersection is consistentIntersection of 2 cubes is compatible iff all corresponding values are compatible
To determine ZForm the cube (v1,v2, … vn|x) Intersect this cube with the primitive cube of Z until a consistent intersection is obtainedThe value of z is obtained in the rightmost position
∩ 0 1 X0 0 ∅ 01 ∅ 1 1X 0 1 X
![Page 27: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/27.jpg)
27CS&RSOC YONSEI UNIVERSITY
Model GenerationState Tables
Represents synchronous sequential circuitsRow corresponding to every internal stateColumn corresponding to every possible inputN(qi,Im), Z(qi, Im)
Entry in row qi and column Im represents the next state and the output produced if Im is applied when the machine is in state qi N : next state Z : output function
x0 1
1 2,1 3,0q 2 2,1 4,0
3 1.0 4,04 3,1 3,0
![Page 28: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/28.jpg)
28CS&RSOC YONSEI UNIVERSITY
Model GenerationState Tables
Canonical Structure
F/F
combinationalcircuit C
F/F
x
CLOCK
z
y Y
![Page 29: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/29.jpg)
29CS&RSOC YONSEI UNIVERSITY
Model GenerationFlow Tables
Represents a behavior of asynchronousState transition may involve a sequence of state changes caused by a single input change to Ij until a stable configuration is reached, denoted by N(qi, Ij)=qi
combinationalcircuit C
x z
y
x1 x2
00 01 11 101 1,0 5,1 2,0 1,02 1,0 2,0 2,0 5,13 3,1 2,0 4,0 3,04 3,1 5,1 4,0 4,05 3,1 5,1 4,0 5,1
![Page 30: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/30.jpg)
30CS&RSOC YONSEI UNIVERSITY
Model GenerationIterative Array
C(0) pseudoF/F C(0) pseudo
F/Fpseudo
F/FC( i )Y(1) y(1) Y(2) y(2) y(i) Y(i+1) y(i+1)
Y(0)
x(0)
z(0)
x(1)
z(1)
x( i )
z( i )
time frame 0cell 0
time frame 1cell 1
time frame icell i
![Page 31: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/31.jpg)
31CS&RSOC YONSEI UNIVERSITY
Model GenerationPrograms as Functional Models
CE = A & B & CF = ~DZ = E \ F
AssemblyLDA A /* load accumulator with value of A*/AND B /* compute A.B */AND C /* compute A.B.C */STA E /* store partial result */LDA D /* load accumulator with value of D */INV /* compute DOR E /* compute A.B.C + D */STA Z /* store result */
ABC
D F
E
Z
![Page 32: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/32.jpg)
32CS&RSOC YONSEI UNIVERSITY
Model GenerationRTL Constructs
8-bit register IR register IR[0→ 7]
256-word memory ABC with 16-bit/word memory ABC[0 → 255; 0 → 15]
When control is 1, C=A+Bif X then C=A+B
Decodertest (IR[0 → 3])case 0 : operation0case 1 : operation1
case 15 : operation15testend
![Page 33: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/33.jpg)
33CS&RSOC YONSEI UNIVERSITY
Model GenerationTiming Models in RTL
Procedural LanguagesSimilar to conventional programming language where statements are sequentially executed such that the result of a statement isimmediately availableC = B
A = BC = A
Describes a system at the instruction set level of abstractionNonprocedural Languages
Statements are conceptually executed in parallelExchange A and B
A = BB = A
ExamplesC=A+B, delay = 100 delay C 100
![Page 34: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/34.jpg)
34CS&RSOC YONSEI UNIVERSITY
Model GenerationStructural Models
FanoutFanout-freeReconvergent fanputInversion Parity
![Page 35: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/35.jpg)
35CS&RSOC YONSEI UNIVERSITY
Logic SynthesisGraph Models and FSM
GraphEdgeVertexUndirected graphDigraph (directed graph)
All edges are directedMixed graph
Directed and undirectedDAG (directed acyclic graph)
If digraph has no cycles
![Page 36: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/36.jpg)
36CS&RSOC YONSEI UNIVERSITY
Logic Synthesis
Graph: ordered set of two sets G= (V,E)V : a set of vertices or nodesE : a set of edges or arcs->4 : the successors (fanouts) of node 4 4->=1,3->4 : the predecessors (fanins) of node 4 ->4=1,2
Graph Terminology
![Page 37: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/37.jpg)
37CS&RSOC YONSEI UNIVERSITY
Logic SynthesisGraph Models
Transitive closureThe extended edge relation E*(u,v) derived from a given edge relation E(u,v) is called transitive closure of E
fanoutfaninSource
v has no predecessorsSink
v has no successors
![Page 38: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/38.jpg)
38CS&RSOC YONSEI UNIVERSITY
Graph AlgorithmsProducts of Sets of Sets
Intersecting 2 sets of setsTakes as inputs the sets G and H and computes the product P=GXH of sets G and H
Procedure SET_CARTESIAN_PRODUCT(G,H) Ops Times/callBest Worst
m =G; n=H; c1 1 1P = NULL c2 1 1for (i = 1, 2, …, m) c3m 1 1
for (j = 1, 2, …, n) c4n m mP = P ∪ (Gi ∩ Hj) c5 mn mnq
return(P) c6 1 1
![Page 39: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/39.jpg)
39CS&RSOC YONSEI UNIVERSITY
Graph AlgorithmsComputing Critical Path Length
This problem is modeled as that of finding the longest path in a DAG (Directed Acyclic Graph)
The Key point is that every edge is traversed exactly once
T(m,n,q) = O(m)
![Page 40: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/40.jpg)
40CS&RSOC YONSEI UNIVERSITY
Graph AlgorithmsLongest Paths
![Page 41: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/41.jpg)
41CS&RSOC YONSEI UNIVERSITY
Graph AlgorithmsBacktracing
The slack of an edge(a,v) is the slack of v plus the difference between the length of the longest path to v and the longest path to v through (a,v)In formula, slacka,v = slackv + (λv - (λ a + La,v ))Here λv is the length of the longest path to v, and (λ a + La,v ) is the length of the longest path to v that passes through the edge (a,v)The slack of a node u is defined as the minimum of its fanout edge slacks, so
slacka = min slackv
An edge (a,v) is critical if it connects two nodes a and v with slack value 0
![Page 42: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/42.jpg)
42CS&RSOC YONSEI UNIVERSITY
Asymptotic ComplexityAsymptotic Complexity
A function F(n) is in the set O(g(n)) if and only if there exist positive constants co and no such that
F(n) ≤cog(n) for all n ≥ no
This means that F(n) is asymptotically bounded from above by a linear function of g(n)
A function F(n) is in the set Ω(g(n)) if and only if there exist positive constants cΩ and nΩ such that
F(n) ≥ cΩ g(n) for all n ≥ nΩ
This means that F(n) is asymptotically bounded from below by a linear function of g(n)
![Page 43: Introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/CAD/Introduction.pdf · CS&RSOC YONSEI UNIVERSITY 5 Logic Design Styles Design Style zFull custom design Every circuit](https://reader033.vdocuments.site/reader033/viewer/2022042312/5edafe6009ac2c67fa68a349/html5/thumbnails/43.jpg)
43CS&RSOC YONSEI UNIVERSITY
ConlcusionConclusion
Design time spent in each design phase
Verification : 39% RTL design and synthesis : 17%IC layout : 13%System design and integration : 11%Test vector creation : 11%Evaluation and Procurement : 6%Other : 3%