Section IIBasic PLD Architecture

Foundation and Alliance Series Software

Version 2.1i

Xilinx M1-Based Software

Libraries and Interfaces for Leading EDA Vendors

Complete, Ready-to-Use

Includes Schematic, Simulation, VHDL and Verilog Synthesis

Foundation Series

ALLIANCE Series

Software Backplane

Core Implementation Software - Map, Place, Route, Bitstreamgeneration, and analysis

Xilinx Tool FlowDesign Entry

HDL or Schematic

Implementation

Configure Device Timing Simulation

Netlist

BIT File Reports SimulationNetlist

FunctionalSimulation

Synthesis or Schematic Netlister

Design Toolsw Standard CAE entry and verification toolsw Xilinx Implementation software implements the

design— The design is optimized for best performance and

minimal size— Graphical User Interface and Command Line Interface— Easy access to other Xilinx programs— Manages and tracks design revisions— ~ Functional Simulation

Back AnnotationSchematic, State Mach., HDL Code, LogiBLOX, CORE Gen

Design Implementation

Verification

Static Timing Analysis,In-Circuit Testing

Design Entry

Simulator

M1 Design Manager

Xilinx

Foundationor Alliance

3rd Party Support & Libraries

w Xilinx 3rd Party Design Entry & Simulation Support— Synopsys, Cadence, Mentor Graphics, Aldec (Foundation)— Viewlogic, Synplicity, OrCad, Model Technologies, Synario,

Exemplar and others supply libs & interfaces— Industry standard file formats:

– VHDL, Verilog, and EDIF netlist formats– SDF Standard Delay files– VITAL library support

w Xilinx Libraries— Optimized components for use in any Xilinx FPGA or CPLD— Wide range of functions

– Comparators, Arithmetic functions, memory– DSP and PCI interfaces

— Easy to use with ABEL, VHDL, Verilog, schematic entry

Libraries, Macros & Attributesw Libraries are common design sets for all design entry tools (eg. text,

schematic, Foundation, Synopsys, Viewlogic, etc.)

w Library “interfaces” are specific to each front endw Attributes are library element propertiesw Online “Libraries Guide” has full listings and descriptions

— Unified Libraries: – Boolean functions, TTL,

Flip-Flops, Adders, RAM, small functions

— LogiBlox Libraries: – Variable size blocks of

adders, registers, RAM, ROM, etc.

– Properties defined as attributes

Core Design TechnologyOptimal Core Creation & Flexible Core Delivery

Data sheets

CoreLINX:

SystemLINX:

Web Mechanism to Download New Cores

Third Party System Tools Directly Linked With Core Generator

Parameterizable Cores

Foundation Series Express Overvieww Easy to use, yet powerful

w Based on Industry Standards, not proprietary languages

w Features:— Schematic (partnership with Aldec)— IEEE VHDL, Verilog, ABEL— State Diagram Editor— Interactive Simulation— Exclusive partnership with Synopsys, the synthesis leader

AldecSynopsys

Xilinx

Foundation Project Managerw Integrates all tools into one environment

Schematic Entry

ABEL and VHDL Text Entryw From schematic menu

(or via HDL Editor), select Hierarchy -> New Symbol Wizard… to create symbol.

w Select HDL Editor & Language Assistant to learn by example, then define block.

w Synthesize to EDIF.

54

3

1

2

Design Entry - State Editorw Draw finite state

machines in “bubble-diagram” form

w State diagram is synthesized to VHDL or ABEL

w Code easily viewed with HDL Editor

w Symbol automatically created for placement on schematicüEasy to LearnüEasy to UseüSaves Time

Simulation - Easy to Use and Learn• Generate stimulus

easily and quickly– Keyboard toggling– Simple clock stimulus– Custom formulas

• Easy debugging– Waveform viewer– Signals easily added and

removed– Simulator access from

schematic– Color-coded values on

schematic• Script Editor

Foundation Express 2.1i Features

w Express Technology— Optimizes the design for Xilinx Architectures — Optimized arithmetic functions— Automatic Global Signal Mapping— Automatic I/O Pad Mapping— Resource Sharing— Hierarchy Control— Source Code Compatible With Synopsys Design Compiler

and FPGA Compiler— Verilog (IEEE 1364) and VHDL (IEEE 1076-1987) Support — Easy, graphical constraint entry— F2.1i is integrated in Project Manager

Express Input and Output

— Mixed Verilog/VHDL modules are accepted

— Schematics may also be used, but should not be input into Express

— Schematic files in XNF or EDIF format will be merged into the design in Xilinx Design Manager

w Output netlists are in XNF format

w Timing Specifications may be specified in Express

Reports

TimingRequirements

VHDLVerilog

Express

.XNF

w Input files may be VHDL or Verilog format

— Timing Specifications are not used during Synthesis— Timing Specifications can be included in the output

netlist

Express Design Process

1. Analyze - Syntax check2. Implement - Create generic logic design (Elaborate)3. Enter constraints and options4. Synthesize - Optimize the design for specific device5. Export XNF Netlist6. Implement layout with Xilinx Design Manager

1

3

2

2

{4

Implementation - M1 Design Manager

w Manages design data

w Access reports

w Supports CPLDs, FPGAs

Flow EngineTiming Analyzer

PROM File FormatterHardware DebuggerEPIC Design Editor

What is Implementation?

w More than just “Place & Route”

w Implementation includes many phases— Translate: Merge multiple design files into a

single netlist— Map: Group logical symbols from the netlist

(gates) into physical components (CLBs and IOBs)

— Place & Route: Place components onto the chip, connect them, and extract timing data into reports

— Timing (Sim): Generate a back-annotatednetlist for timing simulation tools

— Configure: Generate a bitstream for device configuration

Terminology

w Project— Source file; has a defined working directory and family

w Version— A Xilinx netlist translation of the schematic— Multiple Versions result from iterative schematic changes

w Revision— An implementation of a Xilinx netlist— Multiple revisions typically result from different options

w Part type— Specified at translation; can be changed in a new revision

Toolbox Programs

w Flow Engine— Controls start/stop points and

custom options

w Timing Analyzer— Report on net and path delays

w PROM File Formatter— Create file to program

configuration file into PROM

w Hardware Debugger— Download configuration file with

XChecker, Serial or JTAG Cable

w EPIC Design Editor— Device-level view of routing

What is the Flow Engine?w A graphical interface to the

Xilinx implementation tools— Implement your design with

just one click OR— Fine-tune the

implementation process with easy-to-access software options

w Integrated with the Foundation Project Manager and the Alliance Design Manager— Both tools provide project

management functions such as version control

— Foundation Project Manager also provides access to design entry and simulation tools

Foundation Project Manager orAlliance Design Manager

Flow Engine

Translate

Map

Timing (Sim)

Place & Route

Configure

Starting the Flow EngineFoundation Project Manager

The Flow EngineImplementation phases

Implementation status

Message area

Flow control buttons