interrupts, buses

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Interrupts, Buses. Chapter 6.2.5, 8.2-8.3. Introduction to Interrupts. Interrupts are a mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Four general classes of interrupts Terms: Traps when initiated by system, Interrupt when initiated by programmer - PowerPoint PPT Presentation

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  • Interrupts, BusesChapter 6.2.5, 8.2-8.3

  • Introduction to InterruptsInterrupts are a mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processingFour general classes of interruptsTerms: Traps when initiated by system, Interrupt when initiated by programmerProgram - e.g. overflow, division by zeroTimer, internal timer, used in pre-emptive multi-taskingI/O - from I/O controllerHardware failure, e.g. memory parity errorParticularly useful when one module is much slower than another, e.g. disk access (milliseconds) vs. CPU (microseconds or faster)

  • Interrupt Examples4 = code for pre-write, 5 = code for post-write, * = interrupt

  • Interrupt CycleAdded to instruction cycleProcessor checks for interruptIndicated by an interrupt signalIf no interrupt, fetch next instructionIf interrupt pending:Suspend execution of current program Save context (what does this mean?)Set PC to start address of interrupt handler routineProcess interrupt, i.e. execute interrupt handler codeRestore context and continue interrupted program

  • Branch Table for HandlersHow do we know where to go to execute the interrupt handler?Lookup in a branch table, also called the interrupt vector

  • Instruction Cycle (with Interrupts) - State Diagram

  • Multiple InterruptsDisable interrupts Sequential ProcessingProcessor will ignore further interrupts whilst processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occurDefine priorities Nested ProcessingLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed, processor returns to previous interrupt

  • Multiple Interrupts - SequentialDisabled Interrupts Nice and Simple

  • Multiple Interrupts - NestedHow to handle state with an arbitrary number of interrupts?

  • Sample Time Sequence of Multiple InterruptsUser ProgramPrinter ISR Comm ISR Disk ISRt=10t=40t=15t=25t=25t=35t=0Priority 2 Priority 5 Priority 4Disk cant interrupt higher priority CommNote: Often low numbers are higher priority

  • BusesThere are a number of possible interconnection systems. The most common structure is the bus

    Single and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)

  • What is a Bus?A communication pathway connecting two or more devicesUsually broadcastEveryone listens, must share the mediumMaster can read/write exclusively, only one masterSlave everyone else. Can monitor data but not produceOften groupedA number of channels in one buse.g. 32 bit data bus is 32 separate single bit channelsPower lines may not be shownThree major buses: data, address, control

  • Bus Interconnection Scheme

  • Data BusCarries dataRemember that there is no difference between data and instruction at this levelWidth is a key determinant of performance8, 16, 32, 64, 128 bitGenerally we like the data bus width to match the register word sizeFamous non-examples include 8088, 386SX

  • Address busIdentify the source or destination of dataIn general, the address specifies a specific memory address or a specific I/O porte.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of system8086 has 20 bit address bus but 16 bit word size for 64k directly addressable address spaceBut it could address up to 1MB using a segmented memory model

  • Control BusControl and timing informationDetermines what modules can use the data and address linesIf a module wants to send data, it must (1) obtain permission to use the bus, and (2) transfer data which might be a request for another module to send dataWe will skip how arbitration for control is performedTypical control linesMemory read - Memory writeI/O read- I/O writeInterrupt request- Interrupt ACKBus Request- Bus GrantClock signals

  • Big and Yellow?What do buses look like?Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boardse.g. PCISets of wiresLimited by physical proximity time delays, fan out, attenuation are all factors for long buses

  • Single Bus ProblemsLots of devices on one bus leads to:Propagation delaysLong data paths mean that co-ordination of bus use can adversely affect performance bus skew, data arrives at slightly different timesIf aggregate data transfer approaches bus capacity. Could increase bus width, but expensiveDevice speedBus cant transmit data faster than the slowest deviceSlowest device may determine bus speed!Consider a high-speed network module and a slow serial port on the same bus; must run at slow serial port speed so it can process data directed for itPower problemsMost systems use multiple buses to overcome these problems

  • Traditional (ISA) with cacheBuffers data transfers between system, expansion busThis approach breaks down as I/O devices need higher performance

  • High Performance Bus Mezzanine ArchitectureAddresses higher speed I/O devices by moving up in the hierarchy

  • Direct Memory AccessTying together buses with interrupts!

  • AGP = 32 bit bus, 66Mhz speed 4 bytes, so 66*4 = 264MB/sAGP 2x doubles bandwidth by sending data on rising and falling edge for 528MB/s

    SDRAM: bandwidth of 8 bytes, for 800MB

    SCSI: Bandwidth of 4 bytes, for 133MB/sec

    IDE: 8 bit (16 possible), 33Mhz, 33MBps possibleEnhanced IDE: 16 bit, 33Mhz, 66Mbps possible

    ISA bus: 8 bit originally, 4.77Mhz on IBM PCUpped to 16 bits and 8 Mhz for about 16MB/s