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Inter Partes review United States Patent 7,126,174
1
UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
GlobalFoundries, Inc.
Petitioner
v.
Godo Kaisha IP Bridge 1
Patent Owner
Patent No. 7,126,174 Filing Date: November 24, 2004
Issue Date: October 24, 2006
Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
____________
Inter Partes Review No.: To be assigned
___________________________________________________________________________
PETITION FOR INTER PARTES REVIEW UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
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Table of Contents
I. Preliminary Statement .......................................................................................................1
II. Technological Background ................................................................................................1
A. Integrated Circuits ....................................................................................................1
B. Isolation Structures ..................................................................................................3
LOCOS ....................................................................................................... 3 1.
Shallow Trench Isolation ............................................................................ 4 2.
C. Insulating Sidewalls .................................................................................................6
III. The ’174 Patent ..................................................................................................................8
A. Admitted Prior Art ...................................................................................................8
B. Challenged Claims .................................................................................................10
C. Representative Embodiment ..................................................................................10
D. The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority Before December 19, 1995 ................................................................................................11
IV. Statement of Precise Relief Requested for Each Claim Challenged ...........................13
A. Claims for Which Review is Requested ................................................................13
B. Statutory Grounds of Challenge .............................................................................13
C. Level of Ordinary Skill ..........................................................................................13
D. Claim Construction ................................................................................................13
V. Claims 1, 4, 5, 8–12, 14, and 16 of the ’174 Patent Are Unpatentable ........................14
A. Disclosures of the Prior Art ...................................................................................14
Lowrey (U.S. Patent No. 5,021,353) ......................................................... 14 1.
Noble (U.S. Patent No. 5,539,229) ........................................................... 15 2.
Ogawa (U.S. Patent No. 4,506,434) ......................................................... 16 3.
B. The Lowrey-Noble combination renders claims 1, 4, 5, 8–12, 14, and 16 obvious ...................................................................................................................17
A POSITA would have found it obvious and even desirable to have 1.combined the teachings of Lowrey and Noble .......................................... 18
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Claim 1 is obvious over Lowrey and Noble .............................................. 24 2.
Claim 4 is obvious over Lowrey and Noble .............................................. 36 3.
Claim 5 is obvious over Lowrey and Noble .............................................. 37 4.
Claim 8 is obvious over Lowrey and Noble .............................................. 39 5.
Claim 9 is obvious over Lowrey and Noble .............................................. 40 6.
Claim 10 is obvious over Lowrey and Noble ............................................ 42 7.
Claim 11 is obvious over Lowrey and Noble ............................................ 45 8.
Claim 12 is obvious over Lowrey and Noble ............................................ 46 9.
Claim 14 is obvious over Lowrey and Noble ............................................ 47 10.
Claim 16 is obvious over Lowrey and Noble ............................................ 49 11.
C. The Lowrey-Ogawa combination renders claims 1, 4, 5, 8–12, 14, and 16 obvious ...................................................................................................................51
A POSITA would have combined the teachings of Lowrey and Ogawa .. 52 1.
Claim 1 is obvious over Lowrey and Ogawa ............................................ 56 2.
Claim 4 is obvious over Lowrey and Ogawa ............................................ 59 3.
Claim 5 is obvious over Lowrey and Ogawa ............................................ 59 4.
Claim 8 is obvious over Lowrey and Ogawa ............................................ 59 5.
Claim 9 is obvious over Lowrey and Ogawa ............................................ 59 6.
Claim 10 is obvious over Lowrey and Ogawa .......................................... 60 7.
Claim 11 is obvious over Lowrey and Ogawa .......................................... 61 8.
Claim 12 is obvious over Lowrey and Ogawa .......................................... 61 9.
Claim 14 is obvious over Lowrey and Ogawa .......................................... 62 10.
Claim 16 is obvious over Lowrey and Ogawa .......................................... 62 11.
VI. Trial Should Be Instituted on Both Grounds ................................................................62
VII. Mandatory Notices Under 37 C.F.R. §42.8 ....................................................................62
A. Real Parties-In-Interest ..........................................................................................62
B. Related Matters ......................................................................................................63
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C. Lead and Back-Up Counsel ...................................................................................64
D. Service Information ...............................................................................................64
VIII. Certification Under 37 C.F.R. §42.24(d) ........................................................................64
IX. Payment of Fees................................................................................................................64
X. Time for Filing Petition ...................................................................................................65
XI. Grounds for Standing ......................................................................................................65
XII. Conclusion ........................................................................................................................65
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TABLE OF AUTHORITIES
Page(s)
CASES
Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) ......................................... 13
STATUTES AND RULES
35 U.S.C. .................................................................................................................................. 12
35 U.S.C. § 103 ........................................................................................................................ 12
35 U.S.C. §§ 311–319 ................................................................................................................ 1
35 U.S.C. § 311(c) ................................................................................................................... 60
MISCELLANEOUS
37 C.F.R. § 42.1(b) .................................................................................................................. 58
37 C.F.R. § 42.8 ................................................................................................................. 59, 60
37 C.F.R. § 42.24 ..................................................................................................................... 60
37 C.F.R. § 42.24(D) ............................................................................................................... 60
37 C.F.R. § 42.100(b) .............................................................................................................. 13
37 C.F.R. § 42.100 et seq. .......................................................................................................... 1
37 C.F.R. § 42.101(b) .............................................................................................................. 60
37 C.F.R. § 42.102(a)............................................................................................................... 60
37 C.F.R. §§ 42.103(a) and 42.15(a) ....................................................................................... 60
37 C.F.R. § 42.104(a)............................................................................................................... 60
V.B.3, Lowrey .......................................................................................................................... 55
V.B.5, Lowrey .......................................................................................................................... 56
V.B.6, Lowrey .......................................................................................................................... 56
V.B.7, Lowrey .......................................................................................................................... 57
V.B.8, Lowrey .......................................................................................................................... 58
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V.B.9, Lowrey .......................................................................................................................... 58
V.B.10, Lowrey ........................................................................................................................ 58
V.B.11, Lowrey ........................................................................................................................ 58
2:10-cv-01668-JLL-CCC (D.N.J. Apr. 1, 2010) ...................................................................... 59
Although Lowrey ..................................................................................................................... 24
Besides Schuegraf .................................................................................................................... 19
Both Lowrey ....................................................................................................................... 20, 50
Figure 5 Iyer (Ex. 1018) ........................................................................................................... 27
LOCOS, Ogawa ....................................................................................................................... 52
Section V.B, Lowrey ................................................................................................................ 48
U.S. Patent No. 3,617,824...................................................................................................... 1, 2
U.S. Patent No. 3,787,251.......................................................................................................... 1
U.S. Patent No. 4,110,899.......................................................................................................... 1
U.S. Patent No. 4,506,434................................................................................................ 1, 4, 15
U.S. Patent No. 4,638,347.......................................................................................................... 1
U.S. Patent No. 4,957,590.......................................................................................................... 1
U.S. Patent No. 5,021,353.................................................................................................... 1, 14
U.S. Patent No. 5,153,145...................................................................................................... 1, 6
U.S. Patent No. 5,521,422.......................................................................................................... 1
U.S. Patent No. 5,539,229.................................................................................................... 1, 14
U.S. Patent No. 5,702,976.......................................................................................................... 1
U.S. Patent No. 5,733,812.......................................................................................................... 1
U.S. Patent No. 5,976,939.......................................................................................................... 1
U.S. Patent No. 6,165,826.......................................................................................................... 1
U.S. Patent No. 7,126,174................................................................................................. passim
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LIST OF EXHIBITS
Petition Exhibit 1001: U.S. Patent No. 7,126,174 to Segawa et al.
Petition Exhibit 1002: U.S. Patent No. 5,153,145 to Lee et al.
Petition Exhibit 1003: U.S. Patent No. 3,617,824 to Shinoda et al.
Petition Exhibit 1004: Expert Declaration of Dr. Sanjay Banerjee, Ph.D.
Petition Exhibit 1005: J.A. Appels et al., “Some Problems of MOS Technology,” Philips Tech. Rev. vol. 31 nos. 7–9, pp. 225–36, 276 (1970).
Petition Exhibit 1006: U.S. Patent No. 4,110,899 to Nagasawa et al.
Petition Exhibit 1007: U.S. Patent No. 3,787,251 to Brand et al.
Petition Exhibit 1008: B.B.M. Brandt et al., “LOCMOS, a New Technology for Complementary MOS Circuits,” Philips Tech. Rev. vol. 34 no. 1, pp. 19–23 (1974).
Petition Exhibit 1009: U.S. Patent No. 5,702,976 to Schuegraf et al.
Petition Exhibit 1010: U.S. Patent No. 4,506,434 to Ogawa et al.
Petition Exhibit 1011: U.S. Patent No. 4,957,590 to Douglas
Petition Exhibit 1012: U.S. Patent No. 5,976,939 to Thompson et al.
Petition Exhibit 1013: U.S. Patent No. 6,165,826 to Chau et al.
Petition Exhibit 1014: U.S. Patent No. 5,733,812 to Ueda et al.
Petition Exhibit 1015: U.S. Patent No. 5,539,229 to Noble, Jr. et al.
Petition Exhibit 1016: U.S. Patent No. 5,521,422 to Mandelman et al.
Petition Exhibit 1017: U.S. Patent No. 5,021,353 to Lowrey et al.
Petition Exhibit 1018: U.S. Patent No. 4,638,347 to Iyer
Petition Exhibit 1019: Japanese Patent Application No. 7-192181 to Segawa et al.
Petition Exhibit 1020: Certified Translation of Japanese Patent Application No. 7-192181 to Segawa et al.
Petition Exhibit 1021: File History of U.S. Patent No. 7,126,174 to Segawa et al.
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Petition Exhibit 1022: File History of Japanese Patent Application No. 7-330112 to Segawa et al.
Petition Exhibit 1023: Certified Translation of Portions of the File History of Japanese Patent Application No. 7-330112 to Segawa et al.
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PRELIMINARY STATEMENT I.
U.S. Patent No. 7,126,174 to Segawa et al. (Ex. 1001) is directed to certain structures for
metal-oxide-semiconductor field-effect transistors (“MOSFETs”) and their interconnections.
MOSFETs, which can act as switches in integrated circuits, are linked by interconnections, which
connect parts of an integrated circuit to one another.
MOSFET integrated circuits debuted as early as 1965 (see Ex. 1003). By the mid-1990s,
MOSFET/interconnection structures were ubiquitous. Virtually all of the limitations in the
challenged claims were known and constitute admitted prior art. (See Ex. 1001, 1:52–5:51, Figs.
17, 20(e).) The only feature of the sole independent claim in the ’174 patent, claim 1, that is not
admitted prior art is the feature of “L-shaped” sidewalls over the MOSFET and interconnection.
But this feature had been known for over a decade before the ’174 patent was filed.
This Petition, supported by the Expert Declaration of Sanjay Banerjee, Ph.D., (Ex. 1004),
establishes that the challenged claims are unpatentable over the prior art. GlobalFoundries, Inc.
(“Global”) respectfully requests inter partes review under 35 U.S.C. §§311–319 and 37 C.F.R.
§42.100 et seq. and cancellation of all challenged claims.
TECHNOLOGICAL BACKGROUND II.
A. Integrated Circuits
A MOSFET includes a “source,” an inlet to receive current, and a “drain” as an outlet to
output current. (Ex. 1004, ¶44.) Electrodes on the source and drain allow current to flow into
and out of the transistor. (Id.) Another basic MOSFET element is a “gate,” which controls
current flow between the source and drain through a “channel” beneath the gate. (Id.) The gate
includes a gate insulator (“gate oxide” or “gate dielectric”) and a gate electrode (“gate”). (Id.,
¶45.) The gate electrode can receive a control voltage to switch the MOSFET on and off, and the
gate insulator generates an associated electric field that controls the channel. (Id.) “ON” and
2
“OFF” states of a MOSFET are depicted below. (Id.; Ex. 1003, Fig. 5 (below with color
annotation).)
ON OFF
To form circuits, MOSFETs are connected by interconnections, which are electrical
conductors that provide pathways for electrical signals. (Ex. 1004, ¶46.) They can be made from
a variety of conducting materials, including metals, metal alloys, metal compounds,
polycrystalline silicon (polysilicon), and combinations of these (e.g., metal-silicon compounds,
called “silicides”). (Id.)
Integrated circuits having multiple MOSFETs and interconnections have existed for over
50 years. For example, a patent filed in 1965 discloses multilevel interconnections formed
between MOSFETs in an integrated circuit. (U.S. Patent No. 3,617,824 to Shinoda et al., Ex.
1003, 4:30–73, Figs. 6–7 (below with color and annotation).)
3
B. Isolation Structures
The semiconductor industry has steadily moved towards packing more MOSFETs onto
each chip. (Ex. 1004, ¶48.) As device densities increase, the distance between devices shrinks,
and by the early 1970s, decreasing inter-device distances started to cause undesirable interactions
between circuit elements. (See Ex. 1005, 10–12; Ex. 1006, 1:40–2:26; Ex. 1007, 1:6–2:32; Ex.
1004, ¶49.) The industry’s solution to this problem was to include insulating “isolation” regions
between the devices to shield them from one another. (Ex. 1005, 10–12; Ex. 1006, 1:7–2:66; Ex.
1007, 1:6–2:32; Ex. 1008, 2–5; Ex. 1004, ¶49.) Use of such isolation regions has continued
through the present time. (Ex. 1004, ¶49.)
LOCOS 1.
Reported as early as 1970, LOCOS (LOCal Oxidation of Silicon) was one of the first
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isolation techniques. (Ex. 1005, 2, 13; Ex. 1008, 2 & n.4; Ex. 1006, 1:8– 14, 1:63–68; Ex. 1004,
¶50.) In LOCOS, selected regions of a silicon substrate are exposed to oxygen at a high
temperature to convert the silicon in those regions into silicon dioxide. (Ex. 1005, 4, 6, 10; Ex.
1006, 3:18–20, 4:18–34; Ex. 1008, 2–3; Ex. 1004, ¶50.)
LOCOS has drawbacks. Silicon dioxide grows laterally as the substrate is oxidized,
resulting in unintentional silicon dioxide projections into MOSFET regions, called “overhang” or
“bird’s beaks.” (Ex. 1006, 6:1:10; Ex. 1009, 1:47–59; Ex. 1004, ¶51; Ex. 1008, Fig. 2a; Ex.
1010, 1:33–42, Fig. 1 (below with color and annotation).) By the mid-1990s, this bird’s beak
“pose[d] a limitation to device density” that could be addressed by new isolation techniques.
(Ex. 1009, 1:47–59; see also Ex. 1001, 1:29–43 (admitted prior art); Ex. 1004, ¶51.) The bird’s
beak (see annotated Fig. 1 below from U.S. Patent No. 4,506,434 to Ogawa et al.) also causes
undesirable strain. (Ex. 1010, Fig. 1, 1:42–50).
Shallow Trench Isolation 2.
Shallow trench isolation (STI) was developed to replace LOCOS for small-device
processes. (Ex. 1001, 1:29–43; Ex. 1009, 2:20–24; Ex. 1004, ¶52.) In STI, trenches are etched
into the substrate and filled with insulating material. (Ex. 1004, ¶52.) Although more expensive
and complex than LOCOS, STI resolves the problems of LOCOS. (Ex. 1009, 2:20–24; Ex. 1010,
5
1:60–68; Ex. 1004, ¶52.) Because they are so similar otherwise, STI and LOCOS are
interchangeable and functionally equivalent. (See Ex. 1009, 1:31–2:24; Ex. 1011, 4:8–16; Ex.
1012, 3:1–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1004, ¶53.) Despite the added
expense and complexity, the industry adopted STI to increase device density. (Ex. 1004, ¶53;
see also Ex. 1002, 1:10–14.)
In some STI processes, the top of the isolation structure is level with the substrate
surface. The industry recognized, however, that such an arrangement can interfere with
MOSFET operation if the transistors are packed too closely, as sharp corners of the STI structure
enhance local electric fields that degrade device performance. (Ex. 1016, 1:16–37, Abstract,
1:6–35, Figs. 6a, 6b; Ex. 1004, ¶54.) These problems become worse if the isolation trench
recesses below the substrate surface during subsequent etches because the gate can then “wrap
around” the trench corner. (Ex. 1016, 1:30–37, 3:27–48, 4:58–62, Fig. 2; Ex. 1004, ¶54.)
To mitigate the wrap-around problem, a raised STI structure can extend above the
substrate surface. (See Ex. 1015, 5:49–55, 6:32–50, Fig. 12; Ex. 1016, Abstract, 3:33–34, Fig. 5;
Ex. 1004, ¶55.) Raised STI also helps localize source/drain regions by providing a barrier during
the ion implantation or diffusion processes used to make them. (Ex. 1015, Abstract, 4:62–65,
5:5–8; Ex. 1004, ¶55.) Raised STI structures from the prior art appear below in red. (Ex. 1010,
Fig. 5(b); Ex. 1015, Fig. 11; Ex. 1016, Fig. 5.)
6
C. Insulating Sidewalls
The ’174 patent acknowledges that a “conventional semiconductor device” had
MOSFETs, interconnections, and STI regions with sidewalls. (Ex. 1001, 1:52–2:21, Figs. 17
(below with color annotation), 20(e); Ex. 1004, ¶56.) Sidewalls 7a and 7b of features 4a and 4b,
respectively, appear below.
Sidewalls can (1) prevent damage during etching, (2) insulate electrodes and
interconnections to eliminate short-circuits, (3) control the shape of the source/drain regions by
creating a barrier against the migration of impurities, and (4) reduce parasitic leakage current.
(Ex. 1015, 5:5–9, 6:6–8, 6:32–50; Ex. 1002, 1:44–54, 1:64–2:20, 3:22–30, 5:51–6:4, 6:62–7:7,
7
7:44–8:5, Fig. 15; Ex. 1016, 1:6–10, 3:49–53, 4:5–17, 4:30–32, 4:58–5:2, Fig. 5; Ex. 1017, 8:58–
9:2; Ex. 1004, ¶57.)
U.S. Patent No. 5,153,145 to Lee et al. (Ex. 1002), provides sidewalls on gates and gate
runners (interconnections) to avoid short-circuits. (Id., 1:47–54.) In response to “increasingly
complex interconnection schemes” (Ex. 1002, 1:44– 47), Lee provided insulating sidewalls on
the gates and gate runners (Id., 6:62–7:7, Figs. 13, 15). These “prevent[] electrical contact
between patterned layer 170 and the conductive polysilicon heart 117′ of runner 203” and
“facilitate[] the formation of a sub-gate level interconnection between junction regions of
different transistors . . . without the possibility of shorting to a gate runner.” (Id., 7:44–8:5.)
Figure 15 of Lee appears below with color.
The process for creating a silicon-metal “silicide” may damage the gate (id., 1:40–43), so
Lee discloses insulating gate sidewall spacers between the gate and source/drain to address this.
(Id., 4:41–5:4, 5:51–60, 7:16–25, Fig. 9 (shown below with color).) Lee explains that sidewalls
“prevent the migration of other types or particles into the gate stack” to avoid “shorting of the
gate to the source/drain.” (Id., 5:61–6:30; Ex. 1004, ¶59).
8
As Lee and other references show, L-shaped sidewalls were known in the semiconductor
processing art. (Ex. 1004, ¶60; Ex. 1002, 3:8–21, Figs. 9, 15; Ex. 1018, 3:61–68, Fig. 5 (shown
below on left with color); Ex. 1012, 3:1–10, 4:1–10, Fig. 7 (shown below on right with color).)
THE ’174 PATENT III.
A. Admitted Prior Art
The ’174 patent describes a semiconductor device “with high integration and a decreased
area.” (Ex. 1001, 1:13–16.) The ’174 patent explains that “there [we]re increasing demands for
more refinement of the semiconductor device.” (Id., 1:17–20.) Although “the LOCOS isolation
method [had been] conventionally adopted in view of its simpleness [sic] and low cost,” the ’174
patent admits that others already recognized that trench isolation was “more advantageous for
manufacturing a refined semiconductor device.” (Id., 1:17–28.) This was because the bird’s
beak of LOCOS “invades a transistor region against the actually designed mask dimension,”
which was “unallowable” for scaling beyond 0.5 μm. (Id., 1:29–36.) The ’174 patent further
admits, “even in the mass-production techniques, the isolation forming method ha[d] started to
9
be changed to the trench isolation method.” (Id., 1:36–43.) The ’174 patent also describes
“conventional semiconductor device[s]” with “the conventional trench isolation,” shown below
in color-annotated Figures 17 and 20(e). (Id., 1:44–2:22, 3:53–5:11.) The ’174 patent further
shows that trench isolation with a top surface higher than the surface of the semiconductor
substrate is part of a “conventional trench isolation and a MOSFET.” (Id., 3:53–55, 3:64–4:8,
4:45–58, 4:16–19, Figs. 19, 20(a)–20(e) (Fig. 20(e) shown below with color annotations).)
10
B. Challenged Claims1
The only independent claim of the ’174 patent recites:
1. A semiconductor device, comprising:
a trench isolation surrounding an active area of a semiconductor substrate;
a gate insulating film formed over the active area;
a gate electrode formed over the gate insulating film;
first L-shaped sidewalls formed over the side surfaces of the gate electrode;
first silicide layers formed on regions located on the sides of the first L-shaped
sidewalls within the active area;
an interconnection formed on the trench isolation; and
second L-shaped sidewalls formed over the side surfaces of the interconnection.
(Ex. 1001, 29:39–50.) Claims 4, 5, 8–12, 14, and 16 depend from claim 1.
C. Representative Embodiment
As shown below in color-annotated Figure 15(f) of the ’174 patent, one embodiment of
the claimed structure has a trench isolation region (2b), a gate electrode (4a), an interconnection
(4b), a gate electrode sidewall (32a), and an interconnection sidewall (32b). (Ex. 1001, 21:39–
65, 26:40–54, 27:4–8, Figs. 15(a)–15(f).) Isolation region 2b may have a top surface higher in a
stepwise manner than the surface of an active area. (Ex. 1001, 13:49–64, 15:34–36.). Further,
the gate and interconnection sidewalls (32a and 32b) are “L-shaped.” (Id., 27:4–8.)
1 The challenged claims are claims 1, 4, 5, 8–12, 14, and 16.
11
For comparison, “a semiconductor device including the conventional trench isolation and
a MOSFET having the salicide structure,” as the ’174 patent characterizes it, is shown below.
(Ex. 1001, 3:53–5:11, Fig. 20(e) (below with color annotations).) The only difference relevant to
the claim limitations is the “L-shaped” sidewall feature.
D. The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority Before December 19, 1995
The ’174 patent, filed on November 24, 2004,2 claims priority to Japanese Patent
Application No. 7-192181 (“the ’181 application”) (Ex. 1019; Ex. 1020), filed on July 27, 1995,
and Japanese Patent Application No. 7-330112 (“the ‘112 application”)(Ex. 1022; Ex. 1023),
2 The ’174 patent claims priority through a line of intervening applications to parent U.S. Application No.
08/685,726, filed on Jul. 24, 1996. (Ex. 1021, 137.)
12
filed on December 19, 1995.3 The challenged claims are not entitled to the July 1995 priority
date.
The ’181 application does not disclose the claimed “first silicide layers” or even mention
silicide. The local interconnection (13) is polysilicon, as is the interconnection (4b). (Ex. 1020,
¶¶0004, 0009, 0057, 0066, 0072, 0078–0081, 0086, 0094, p. 28.)
The ’181 application also does not provide support for the required “first L-shaped
sidewalls formed over the side surfaces of the gate electrode” or “second L-shaped sidewalls
formed over the side surfaces of the interconnection.” The term “L-shaped” does not appear in
the ’181 application, and the structures shown in the ’181 application lack the claimed “L” shape.
(See Ex. 1019, 38–45; Ex. 1004, ¶¶66–69.) The “sidewalls” in the ’181 application, labeled 7a
and 7b, are not even remotely L-shaped. (See Ex. 1020, Fig. 4(a) (below with color
annotations).)
The “insulating film” of the ’181 application, labeled 12, does not constitute L-shaped
sidewalls either. A POSITA (“person of ordinary skill in the art”) would not have considered a
unitary layer that extends over the entire gate or interconnection to be a “sidewall” or to have
“sidewalls.” (Ex. 1004,¶¶67–68.)
3 The Japanese Patent Office rejected these applications over the prior art and never issued a patent. (Ex. 1023,
187–93.)
13
Due to these deficiencies, the ’174 patent is not entitled to the July 27, 1995, priority date
of the ’181 application. Because the ’174 patent does not claim the benefit of foreign priority to
any other document other that the ‘112 application filed December 19, 1995, the ’174 patent is
not entitled to a benefit of foreign priority earlier than December 19, 1995.
STATEMENT OF PRECISE RELIEF REQUESTED FOR EACH CLAIM IV.CHALLENGED
A. Claims for Which Review is Requested
Global requests review under 35 U.S.C. §311 of claims 1, 4, 5, 8–12, 14, and 16 and the
cancellation of those claims as unpatentable.
B. Statutory Grounds of Challenge
Claims 1, 4, 5, 8–12, 14, and 16 are unpatentable under 35 U.S.C. §103.
C. Level of Ordinary Skill
A POSITA would possess (1) the equivalent of a Master of Science degree from an
accredited institution in electrical engineering, materials science, physics, or the equivalent; (2) a
working knowledge of semiconductor processing technologies for integrated circuits; and (3) at
least two years of experience in related semiconductor processing analysis, design, and
development. Additional graduate education could substitute for professional experience, and
significant work experience could substitute for formal education. (Ex. 1004, ¶72.)
D. Claim Construction
Claim terms are given their ordinary and accustomed meaning as understood by a
POSITA. Phillips v. AWH Corp., 415 F.3d 1303, 1312–13 (Fed. Cir. 2005) (en banc). Although a
claim in an unexpired patent in inter partes review receives the “broadest reasonable construction
in light of the specification of the patent in which it appears,” 37 C.F.R. §42.100(b), the ’174
patent will expire on July 24, 2016, so the Phillips standard for claim construction should govern
14
this petition, see id. The plain and ordinary meaning as understood by a POSITA should be
applied to all claim terms of the ’174 patent.
CLAIMS 1, 4, 5, 8–12, 14, AND 16 OF THE ’174 PATENT ARE UNPATENTABLE V.
Lowrey (Ex. 1017) teaches every limitation of the challenged claims except trench
isolation. It uses LOCOS isolation instead. Noble (Ex. 1015) and Ogawa (Ex. 1010) each
disclose devices very similar to Lowrey but that use trench isolation. Therefore, the Lowrey-
Noble and Lowrey-Ogawa combinations disclose every limitation of the challenged claims.
A POSITA would have been motivated to make the Lowrey-Noble and Lowrey-Ogawa
combinations for many reasons. The admitted prior art of the ’174 patent, and other
contemporary references, describe the transition in the 1990s away from LOCOS toward trench
isolation. A POSITA would have understood that replacing Lowrey’s LOCOS with Noble’s STI
or Ogawa’s buried trench isolation would have just been a simple substitution of one element for
a known equivalent according to known methods to achieve predictable results. A POSITA
would have further understood that making such combinations would have provided numerous
benefits.
A. Disclosures of the Prior Art
The structures claimed by the ’174 patent were well-known in the art. The discussion
below represents a sampling of the knowledge available to a POSITA years before the
application for the ’174 patent.
Lowrey (U.S. Patent No. 5,021,353) 1.
Lowrey (Ex. 1017) teaches every element of the challenged claims except for trench
isolation. Lowrey was filed February 26, 1990, and issued June 4, 1991. It therefore qualifies as
prior art under §102(b). Lowrey was neither considered nor cited during prosecution of the ’174
patent.
15
Lowrey discloses a MOSFET/interconnection structure. Referring to the illustration of
the Lowrey structure below (color-annotated Fig. 12 of Lowrey), Lowrey discloses a silicon
substrate (12) (Ex. 1017, 7:57–64), a field oxide (51) (id., 1:64–2:32, 8:31–35), source/drain
regions (61, 63, 82, 121) (id., 8:53–9:2, 9:18–22, 10:3–15), a gate oxide (31 or 52) (id., 8:37–
52), a gate electrode (56) (id., 8:44–47, 10:3–15), sidewall spacers (62, 71) (id., 8:61–9:12),
silicide regions (122) (id., 10:3–15), and an interconnection (57) (id., 7:14–20, 8:44–47, 9:6–
12, 10:3–15).
Noble (U.S. Patent No. 5,539,229) 2.
Noble (Ex. 1015) teaches trench isolation. Noble was filed on December 28, 1994, and
issued on July 23, 1996. It therefore qualifies as prior art at least under §102(e).
Noble “relates to shallow trench isolation (STI) in which the insulating material is raised
above the surface of the semiconductor.” (Ex. 1015, 1:7–10, Fig. 13 (below).) Noble discloses a
silicon substrate (10) (id., 3:59–62), a raised STI region (30) (id., 4:14–19, 4:40–45, 4:63–65),
substrate source/drain regions (138, 156) (id., 6:13–31), a gate dielectric (14) (id., 3:64–4:1,
4:11–14), a gate conductor (116) (id., 5:67–6:6), dielectric spacers (152) (id., 6:6–8), silicide
regions (158) (id., 6:24–26), and conductive wiring level (140) (id., 5:53–61, 5:67–6:6). A
16
representative illustration appears below.
Ogawa (U.S. Patent No. 4,506,434) 3.
Ogawa (Ex. 1010) also teaches trench isolation. Ogawa was filed on September 3, 1982,
and issued on March 26, 1985. It therefore qualifies as prior art under §102(b). Ogawa was
neither considered nor cited during prosecution of the ’174 patent.
Ogawa teaches “a method wherein each element is isolated from one another by buried
insulating layers which are grown to fill grooves produced along the surface of a silicon (Si)
substrate to surround each element.” (Ex. 1010, 1:61–66; see also 1:8–15, Fig. 5(c) (below).)
Ogawa discloses a silicon substrate (51) (id., 7:43–47), a buried silicon dioxide layer (52) that
extends above the active region of the substrate (id., 7:43–47, Fig. 5(c)), a silicon dioxide layer
(54) as a gate oxide (id.), a polycrystalline silicon layer (55) and molybdenum silicide layer
(56) double-layer gate electrode (id., 7:51–56, 8:35–38, Fig. 5(c)), a molybdenum silicide layer
17
(57[sic])4 as a wiring/interconnect level (id., 7:51–56, 8:67–9:5, Fig. 5 (c)), and sources and
drains (58) (id., 8:3–7, Fig. 5(c)). A representative illustration appears below.
B. The Lowrey-Noble combination renders claims 1, 4, 5, 8–12, 14, and 16 obvious
Lowrey teaches every limitation of the challenged claims except trench isolation. A
POSITA would have understood that Noble’s trench isolation was a known substitute for
Lowrey’s LOCOS isolation. (Ex. 1004, ¶80; see also Ex. 1009, 1:31–2:24; Ex. 1011, 4:8–16;
Ex. 1012, 3:3–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1015, Title, 1:7–10, 2:53–57,
4:14–23, Figs. 12, 13.) The combined teachings discussed in this section refer to the teachings of
Lowrey, with its LOCOS isolation replaced by Noble’s STI.
4 The label 57 is erroneous in Figure 5(c). (Ex. 1004, ¶80 n.1.) It should read “56.” (Id.) Layer 57 is a
photoresist layer not shown in Figure 5(c). Element 57 in Figure 5(c) corresponds to layer 56 of Figures 5(a) and
5(b). (Ex. 1010, 7:53–56, Figs. 5(a)–5(c).)
18
A POSITA would have found it obvious and even desirable to have 1.combined the teachings of Lowrey and Noble
Many reasons would have compelled a POSITA to replace Lowrey’s LOCOS with
Noble’s STI. (Ex. 1004, ¶¶80–94.) LOCOS was cheaper and simpler at the time of Lowrey
(February 1990), and the bird’s beak was not a major detriment to device density yet. (Ex. 1004,
¶81.) But by the mid-1990s, as the ’174 patent admits, the industry was adopting STI to replace
LOCOS and was mass-producing trench isolation devices. (Ex. 1001, 1:29–53.) A POSITA
would have understood that combining the teachings of Lowrey and Noble would have been a
simple matter of replacing Lowrey’s LOCOS with Noble’s STI. (Ex. 1004,
¶81).
a. The ’174 patent teaches replacing LOCOS with known trench isolation
The ’174 patent acknowledges trench isolation as prior art. It observes that “in the
LOCOS isolation method, . . . the dimension of a transistor is changed because an insulating film
of the isolation invades a transistor region.” (Ex. 1001, 1:29–34.) According to the ’174 patent,
this “is unallowable in the refinement of a semiconductor device after the 0.5 μm generation.”
(Id., 1:34–36.)
By the mid-1990s, LOCOS encountered significant roadblocks for further device
miniaturization. (Ex. 1004, ¶¶82–83.) According to the ’174 patent, “even in the mass-
production techniques, the isolation forming method ha[d] started to be changed to the trench
isolation method in which the dimensional change is very small.” (Ex. 1001, 1:36–39.) Others
in the field of this patent “ha[d] introduced the trench isolation structure as a 0.5 μm CMOS
process for the mass-production of an MPU.” (Id., 1:40–43.) The ’174 patent even references “a
conventional semiconductor device” having trench isolation. (Id., 1:52–53, Fig. 17.)
19
The ’174 patent further shows that trench isolation with a top surface higher than the
surface of the semiconductor substrate is part of a “conventional trench isolation and a
MOSFET.” (Id., 3:53–55, 3:64–4:8, 4:45–58, 4:16–19, Figs. 19, 20(a)–20(e).)
b. Contemporary references teach replacing LOCOS with a known trench isolation
Like the admitted prior art, other contemporary references describe the transition away
from Lowrey’s LOCOS toward trench isolation, such as Noble describes. Schuegraf (Ex. 1009)
explains, “The most widely used isolation technology for MOS circuits ha[d] been that of
LOCOS isolation,” popular because of its “inherent simplicity in MOS process integration, cost
effectiveness and adaptability.” (Ex. 1009, 1:35–40, 1:43–46.) “In spite of its success, several
limitations of LOCOS technology ha[d] driven the development of alternative isolation
structures.” (Id., 1:27–29.) Referring to the bird’s beak, Schuegraf states, “A well-known
limitation in LOCOS isolation [wa]s that of oxide undergrowth at the edge of the mask which
defines the active regions of the substrate.” (Id., 1:49–51; see also Ex. 1010, 1:41–42.) This
20
encroachment “pose[d] a limitation to device density, since that portion of the oxide adversely
influences device performance.” (Ex. 1009, 1:51–55.) To avoid this problem, Schuegraf
explains STI “is often considered an alternative to LOCOS.” (Id., 2:20–22.)
c. Additional references teach that LOCOS and trench isolation were interchangeable
Besides Schuegraf, other references demonstrate that replacing Lowrey’s LOCOS with
Noble’s STI would have constituted a simple substitution of one element for an equivalent
element, according to known methods, to achieve predictable results. (Ex. 1011, 4:8–16; Ex.
1012, 3:1–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1004, ¶¶53, 80, 87–88, 93, 173.) A
POSITA also would have understood that replacing Lowrey’s LOCOS with a trench isolation
would have been entirely compatible and not affected gate formation, source/drain formation, L-
shaped sidewall formation, silicide formation, or any other aspect relevant to the challenged
claims. (Ex. 1004, ¶¶80, 93, 173.)
Ueda (Ex. 1014) describes numerous structures, most of which use LOCOS. (Ex. 1014;
see also 1:46–53, 3:35–37, 8:13–17, 11:28–31, 12:3–6, 14:27–28, 14:53–60, 16:20–23, 16:63–
65, 20:1–3, 21:15–18, Figs. 1(a), 7(a), 10(a), 14(a), 18(a), 19(a), 23(a), 29(a).) An example
appears below (element 2).
Ueda also teaches, “Although the isolation is composed of the LOCOS film in the above
embodiments, . . . [t]he present invention is also applicable to an isolation of trench structure or
the like.” (Id., 22:49–52.) Ueda even discloses how to make a trench isolation. (See id., 13:14–
21
63.) Figures 12(a) through 12(f) of Ueda show an embodiment in which “a trench 9 with a depth
of 500 nm” is used as “an isolation for the silicon substrate 1.” (Id., 13:20–24.) This is “an
isolation composed of the buried oxide film 14 which is 300 nm higher in level than the surface
of the silicon substrate 1.” (Id., 13:33–36.)
d. Lowrey and Noble are in the same field of endeavor and have similar structures
Lowrey and Noble are very similar device structures, and both disclose structures having
MOSFETs in an active region and interconnections on a raised isolation. (Ex. 1017, Abstract,
1:7–9, 1:17–21, 2:18–20, 2:41–47, 3:8–11, 4:51–52, 7:4–25, 8:17–52, 9:6–12, 9:23–43, 10:3–42,
Figs. 5, 12, 13; Ex. 1015, Title, 1:16–19, 3:25–26, 4:53–55, 5:49–52, 6:1–6, Figs. 12, 13.)
Both Lowrey and Noble disclose many elements of the challenged claims: a silicon
substrate (Ex. 1017, 7:57–64; Ex. 1015, 3:59–62), a raised isolation region (Ex. 1017, 1:64–
2:32, 8:31–35; Ex. 1015, 4:14–19, 4:40–45, 4:63–65, Figs. 12, 13), gate dielectric (Ex. 1017,
8:37–52; Ex. 1015, 3:64–4:1, 4:11–14), gate electrode (Ex. 1017, 8:44–47, 10:3–15; Ex. 1015,
5:67–6:6), source/drain regions (Ex. 1017, 8:53–9:2, 9:18–22, 10:3–15; Ex. 1015, 6:13–31),
sidewall spacers (Ex. 1017, 8:61–9:12; Ex. 1015, 6:6–8), silicide regions (Ex. 1017, 10:3–15;
Ex. 1015, 6:24–26), and interconnections (Ex. 1017, 7:14–20, 8:44–47, 9:6–12, 10:3–15; Ex.
22
1015, 5:53–61, 5:67–6:6).
The illustrated embodiments of Lowrey (Figure 12) and Noble (Figure 13) appear below
with annotations, demonstrating their similarities.
e. Combining Lowrey and Noble had known benefits
The combined disclosures of Lowrey and Noble provide numerous advantages. Lowrey’s
spacers mask the substrate during junction formation to more precisely control doping profiles in
the source/drain regions. Lowrey discloses L-shaped “mini-spacer oxide layer 62,” which may
be used “to coat the sides of transistor gates 56, so that when the wafer is subjected to a low-
dosage phosphorus implant, . . . source/drain regions 63 [are] offset from the vertical boundaries
23
of punch-through implant regions 61 by the vertical segments of mini-spacer oxide layer 62.”
(Ex. 1017, 8:62–9:2.) These mini-spacers similarly facilitate the formation of a self-aligned
silicide contact to lower interconnection resistivity and simplify processing. (Id., 9:68–10:42,
Fig. 12.)
Many benefits taught by Noble’s disclosures further complement Lowrey’s device
structures. Noble discloses structures with “shallow trench isolation (STI) in which the
insulating material is raised above the surface of the semiconductor.” (Ex. 1015, 1:7–10, Figs.
12, 13.) In particular, “the gate is bounded by a raised trench on two opposite sides.” (Id., 4:14–
23.) This is beneficial because “a single masking step defines the edge between the trench and
gate stack and provides perfect alignment therebetween.” (Id., 4:19–21.) The “STI is self-
aligned to the gate conductor” (id., 3:27–28), which simplifies device processing and reduces
mask alignment errors. (Ex. 1004, ¶93.) Noble’s raised STI confines impurity ions to
source/drain regions during ion implantation or impurity diffusion to control the associated
doping profiles more precisely during source/drain formation. As Noble explains, “The diffusion
or implant is self-aligned to spacers 36 formed along edges of gate stack 32 and is bounded by
raised STI 30 or raised storage trench 20.” (Ex. 1015, 4:59–65, 5:7–9, Fig. 6.) Noble’s raised
STI structure also enables device density to increase beyond what Lowrey’s LOCOS would
allow by eliminating the bird’s beak.5 (Ex. 1004, ¶93; supra §§II.B, V.B.1.a, V.B.1.b.)
A POSITA would have looked to the teachings of Lowrey and Noble to improve known
device structures by using Noble’s raised STI to substitute for Lowrey’s LOCOS. (Ex. 1004,
¶94.) This would have taught how to mask the substrate to better tailor source/drain doping
5 Schuegraf and Ogawa, for example, show this. (Ex. 1009, 1:47–55, 2:22– 24; Ex. 1010, 1:17–21, 1:40–42,
1:58–60, Fig. 1.)
24
profiles, facilitate silicide contact formation to reduce interconnection resistivity, insulate
electrodes and interconnections to eliminate short-circuits, and increase device density. (Id.) The
combined disclosures of Lowrey and Noble would have allowed improved manufacturability,
durability, scalability, and performance of the associated devices. (Id.) A POSITA also would
have understood that replacing Lowrey’s LOCOS with Noble’s STI would have been entirely
compatible and not affected gate formation, source/drain formation, L-shaped sidewall
formation, silicide formation, or any other aspect relevant to the challenged claims. (Ex. 1004,
¶¶80, 93, 173.) A POSITA would have been motivated to combine these teachings. (Id., ¶94.)
Claim 1 is obvious over Lowrey and Noble 2.
a. [1.1] Lowrey teaches the preamble
The preamble of claim 1 recites “a semiconductor device,” which Lowrey teaches. (Ex.
1017, 1:7–9; 1:17–21, Fig. 12; see also §V.B.1.)
b. [1.2] the Lowrey-Noble combination teaches the “trench isolation” limitation
Claim 1 recites “a trench isolation surrounding an active area of a semiconductor
substrate.” The ’174 patent acknowledges trench isolation as prior art. It observes, “in the
LOCOS isolation method, . . . the dimension of a transistor is changed because an insulating film
of the isolation invades a transistor region.” (Ex. 1001, 1:29–34.) This “is unallowable in the
refinement of a semiconductor device after the 0.5 μm generation.” (Id., 1:34–36.) “[E]ven in
the mass-production techniques, the isolation forming method ha[d] started to be changed to the
trench isolation method in which the dimensional change is very small.” (Id., 1:36–39.) Others
“ha[d] introduced the trench isolation structure as a 0.5 μm CMOS process for the mass-
production of an MPU.” (Id., 1:40–43.) The ’174 patent even discloses “a conventional
semiconductor device” having a trench isolation 2b. (Id., 1:52–53, 3:53–55, Figs. 17 (colored,
25
below), 20(e).)
Noble also discloses “a trench isolation surrounding an active area of a semiconductor
substrate.” Noble describes “shallow trench isolation (STI) in which the insulating material is
raised above the surface of the semiconductor.” (Ex. 1015, 1:7–10.) Noble teaches that trench
isolation surrounds the active area of a MOSFET, stating, “The gate conductor is confined to the
active device area” (id., 3:25–28), and “Raised isolation bounds the first and second edges of the
gate conductor” (id., 2:53–54). (See also id., 4:14–23, 4:52–55, Figs. 12, 13 (colored, below).)
Although Lowrey does not disclose “a trench isolation surrounding an active area of a
semiconductor substrate,” it discloses a LOCOS isolation surrounding an active area of a
semiconductor substrate. (Ex. 1017, 8:31–35, 8:53–9:2, 10:3–15, Figs. 5, 12.) Lowrey discloses
“field oxide regions 51 using the conventional LOCOS oxidation process” that surround active
areas (121, 122) of a semiconductor substrate. (Id., 8:31–35, 10:3–15, Figs. 5, 12 (colored,
26
below).) Lowrey further notes that “[a]lternatively, an oxide deposition or oxide growth step
could replace the first LOCOS step,” recognizing that LOCOS is not limiting and that several
options were available for forming the isolation region. (See id., 2:8– 11.)
A POSITA would have understood that the Lowrey-Noble combination teaches “a trench
isolation surrounding an active area of a semiconductor substrate.” (Ex. 1004, ¶¶96–99; see also
supra §V.B.1.)
c. [1.3] Lowrey teaches the “gate insulator” limitation
Claim 1 recites “a gate insulating film formed over the active area.” This is an essential
element of a MOSFET. (Ex. 1004, ¶100.) The ’174 patent acknowledges it was “known as a
very common structure” to include “an insulating film . . . deposited on the active area.” (Ex.
1001, 1:44–53, 2:55–60, Figs. 17 (element 3, colored below), 20(e).)
27
Lowrey also discloses “a gate insulating film formed over the active area.” “A layer of
gate oxide is then grown on all active areas.” (Ex. 1017, 2:41–44.) Specifically, “a gate oxide
layer 52 is grown,” or, “[a]lternatively, second pad oxide layer 31 may be left intact in order to
serve as transistor gate oxide.” (Id., 8:37–52, Fig. 12 (elements 52).) Figure 12 (colored and
annotated) demonstrates that the gate oxide layer is formed over the active area.
A POSITA would have understood that the Lowrey-Noble combination teaches “a gate
insulating film formed over the active area.” (Ex. 1004, ¶¶100–01; see also supra §V.B.1.)
d. [1.4] Lowrey teaches the “gate electrode” limitation
Claim 1 recites “a gate electrode formed over the gate insulating film.”
This is an essential element of a MOSFET. (Ex. 1004, ¶102.) The ’174 patent
acknowledges it was “known as a very common structure” to include “a gate electrode.” (Ex.
1001, 1:44–53, 2:55–60, Figs. 17 (element 4a, colored below), 20(e).)
28
Lowrey also discloses “a gate electrode formed over the gate insulating film.” It states
“polysilicon layer 53 . . . define[s] N-channel transistor gates 56.” (Ex. 1017, 8:40–47, 8:61–63,
9:6–12, 10:3–15; Fig. 12 (below).) A POSITA would have understood that, by definition, the
polysilicon transistor gates 56 are gate electrodes because they are the conductive regions located
over the gate dielectric. (Ex. 1004, ¶103; Ex. 1017, 8:40–44.)
A POSITA would have understood that the Lowrey-Noble combination teaches “a gate
electrode formed over the gate insulating film.” (Ex. 1004, ¶¶102–04; see also supra §V.B.1.)
e. [1.5] Lowrey teaches the “first L-shaped sidewall” limitation
Claim 1 recites “first L-shaped sidewalls formed over the side surfaces of the gate
electrode.” The ’174 patent acknowledges “a conventional semiconductor device” included
29
sidewalls 7a. (Ex. 1001 (colored below), 1:52–2:6, Fig. 17.)
“L-shaped” sidewalls were also well known. (Ex. 1004, ¶¶106, 117.) This is illustrated
by colored Figure 5 Iyer (Ex. 1018) and colored Figure 7 of Thompson (Ex. 1012), shown below
on the left and right, respectively.
Lowrey discloses “first L-shaped sidewalls formed over the side surfaces of the gate
electrode.” Lowrey states “mini-spacer oxide layer 62 are [sic] etched with a first anisotropic etch,
then optionally etched once again with a first isotropic etch to form a first set of sidewall spacers
81 for N-channel transistor gates 56.” (Ex. 1017, 9:6–12, Fig. 8.) “The purpose of mini-spacer
oxide layer 62 is to coat the sides of transistor gates 56, so that when the wafer is subjected to a
low-dosage phosphorus implant, . . . source/drain regions 63 [are] offset from the vertical
boundaries of punch-through implant regions 61.” (Id., 8:58–9:2; see also 7:21– 25, Fig. 12
(below); compare also Ex. 1001, 27:1–8, 27:40–47, Figs. 15(a)–15(f) (elements 32a).) Figure 12
30
below shows the “L” shape of the mini-spacer oxide, which results from anisotropically etching
the conformal layers 62 and 71 of Lowrey. (Ex. 1004, ¶107; see also Ex. 1017, 9:6–12, Figs. 7
(colored, below), 8, 12 (colored and annotated, below).)
A POSITA would have understood that the Lowrey-Noble combination teaches “first L-
shaped sidewalls formed over the side surfaces of the gate electrode.” (Ex. 1004, ¶¶105–08; see
also supra §V.B.1.)
f. [1.6] Lowrey teaches the “silicide layers” limitation
Claim 1 recites “first silicide layers formed on regions located on the sides of the first L-
shaped sidewalls within the active area.” The ’174 patent acknowledges that first silicide layers
formed on regions on the sides of the first sidewalls within the active area is part of a
“conventional trench isolation and a MOSFET having the salicide structure.”6 (Ex. 1001, 3:53–
55, 4:3–19, 5:1–11, Figs. 19, 20(a)–20(e) (elements 109c).)
6 “Salicide” means “self-aligned silicide.” (Ex. 1004, ¶110 n.2.)
31
Lowrey also discloses “first silicide layers formed on regions on the sides of the first L-
shaped sidewalls within the active area.” Lowrey teaches that “all exposed conductive regions
(i.e., . . . active areas 121 for both N and P-channel devices) have been silicided with titanium in
a conventional self-aligned process.” (Ex. 1017, 10:3–22, Fig. 12 (colored and annotated
below); compare also Ex. 1001, 27:18–33, Fig. 15(a)–(f) (element 9c).) In this process, “[a] layer
or titanium metal is sputter deposited . . . on top of all the circuitry.” (Ex. 1017, 5:61–63.) Then,
“[a] sintering step causes the titanium to react with all unoxidized silicon (i.e., all gates and
source/drain regions for both N-channel and P-channel transistors) to form titanium silicide.”
(Id., 5:63–66.) A chemical treatment “remove[s] all unreacted titanium.” (Id., 5:66–6:1.)
A POSITA would have understood that the Lowrey-Noble combination teaches “first
silicide layers formed on regions located on the sides of the first L-shaped sidewalls within the
active area.” (Ex. 1004, ¶¶109–11; see also supra §V.B.1.)
32
g. [1.7] the Lowrey-Noble combination teaches the “interconnection” limitation
Claim 1 recites “an interconnection formed on the trench isolation.” The ’174 patent
acknowledges that “a conventional semiconductor device” included “an isolation with a trench
isolation structure which is made of a silicon oxide film.” (Ex. 1001, 1:52–2:6.) It further
acknowledges, “On the isolation 2b are [sic] disposed a polysilicon interconnection 4b.” (Id.,
2:60–62, Figs. 17, 20(e).) This is shown below by element 4b in Figure 17 (colored, below) of
the ’174 patent.
As explained in section V.B.1, the Lowrey-Noble combination teaches a trench isolation.
Lowrey further discloses “an interconnection formed on the [LOCOS] isolation.” Lowrey states
that polysilicon layer 53 defines “N-channel interconnects 57,” which are on the LOCOS region.
(Ex. 1017, 8:44–47; see also 3:12–15, 7:14–20, 10:3–22, Figs. 5, 12 (colored and annotated
below).) “FIG. 5 shows the semiconductor device of FIG. 4 following the growth of field oxide
using the LOCOS process, stripping of the second nitride layer, deposition of a polysilicon layer,
masking of the poly layer with a fourth photomask, and a first etch of the poly layer to create
gates and interconnects for N-channel devices.” (Id., 7:14–20, Fig. 5.)
33
In addition, Noble discloses “an interconnection formed on the trench isolation.” Noble
states that “conductive wiring level 140 interconnects gate segments 132 of transistor 139 that is
isolated by raised STI 30.” (Ex. 1015, 5:49– 52.) “[T]he two layers of conductor (gate conductor
116 and conductive wiring level 140) are etched such that gate conductor 116 is substantially
confined to the active area of each transistor and conductive wiring level 140 extends over STI
30 to interconnect transistors or cells, as shown in FIG. 11.” (Id., 6:1–6, Figs. 11–13 (colored
and annotated below).)
34
A POSITA would have understood that the Lowrey-Noble combination teaches “an
interconnection formed on the trench isolation.” (Ex. 1004, ¶¶112–15; see also supra §V.B.1.)
h. [1.8] Lowrey teaches the “second L-shaped sidewall” limitation
Claim 1 recites “second L-shaped sidewalls formed over the side surfaces of the
interconnection.” The ’174 patent acknowledges that “a conventional semiconductor device”
included sidewalls 7b. (Ex. 1001, 1:52–2:6, Figs. 17 (colored below), 20(e).)
“L-shaped” sidewalls were also well known. (Ex. 1004, ¶¶56, 106, 117.) This is
illustrated by Figure 5 (colored) of Iyer (Ex. 1018) and Figure 7 (colored) of Thompson (Ex.
1012), shown below on the left and right, respectively.
35
In addition, Lowrey discloses “second L-shaped sidewalls formed over the side surfaces
of the interconnection.” Lowrey teaches that “mini-spacer oxide layer 62 are [sic] etched with a
first anisotropic etch . . . to form a first set of sidewall spacers 81 for . . . N-channel interconnects
57.” (Ex. 1017, 9:6–12, Figs. 8, 12 (colored, below); compare also Ex. 1001, 27:1–8, 27:40–47,
Figs. 15(a)– 15(f) (elements 32b).)
36
A POSITA would have understood that the Lowrey-Noble combination teaches “second
L-shaped sidewalls formed over the side surfaces of the interconnection.” (Ex. 1004, ¶¶116–19;
see also supra §V.B.1.)
Claim 4 is obvious over Lowrey and Noble 3.
Claim 4 depends from claim 1 (see §V.B.2) and further recites “a second silicide layer
formed on the gate electrode.” The ’174 patent acknowledges a second silicide layer formed on
the gate electrode is part of a “conventional trench isolation and a MOSFET having the salicide
structure.” (Ex. 1001, 3:53–55, 4:3– 19, 5:1–11, Figs. 19, 20(a)–20(e) (element 109a, colored
below).)
Lowrey also discloses “a second silicide layer formed on the gate electrode.” Lowrey
states that “all exposed conductive regions (i.e., N-channel transistor gates 56, . . .) have been
37
silicided with titanium in a conventional self-aligned process.” (Ex. 1017, 10:3–22, Fig. 12
(colored below); compare also Ex. 1001, 27:18–33, Fig. 15(a)–(f) (element 9a).) In this process,
“[a] layer or titanium metal is sputter deposited . . . on top of all the circuitry.” (Ex. 1017, 5:61–
63.) Then, “[a] sintering step causes the titanium to react with all unoxidized silicon (i.e., all
gates and source/drain regions for both N-channel and P-channel transistors) to form titanium
silicide.” (Id., 5:63–66.) A chemical treatment “remove[s] all unreacted titanium.” (Id., 5:66–
6:1.)
A POSITA would have understood that the Lowrey-Noble combination teaches “a second
silicide layer formed on the gate electrode.” (Ex. 1004, ¶¶120–23; see also supra §V.B.1.)
Claim 5 is obvious over Lowrey and Noble 4.
Claim 5 depends from claim 1 (see §V.B.2) and recites (1) “source/drain regions formed
on both sides of the gate electrode within the active area,” and (2) “wherein the first silicide
layers are formed on the source/drain regions.”
a. The “source/drain” limitation
Source/drain regions formed on both sides of the gate electrode within the active area are
essential elements of a MOSFET. (Ex. 1004, ¶126.) The ’174 patent acknowledges that
38
“source/drain regions formed on both sides of the gate electrode within the active area” were
“known as a very common structure.” (Ex. 1001, 1:44–2:6, 2:55–60, Figs. 17 (elements 4, 6,
colored below), 20(e) (elements 106a, 106b, colored below).)
Lowrey also discloses “source/drain regions formed on both sides of the gate electrode
within the active area.” For example, “when the wafer is subjected to a low-dosage phosphorus
implant, lightly-doped n-type source/drain regions 63 are created for N-channel devices.” (Ex.
1017, 8:53–9:2, Figs. 6, 8.) Lowrey further explains that “lightly-doped n-type source/drain
regions 63 [are] offset from the vertical boundaries of punch-through implant regions 61 by the
vertical segments of mini-spacer oxide layer 62 on the edges of the N-channel transistor gates
56.” (Id.; see also 1:7–15, 4:63–5:16, 10:3–15, Figs. 8, 12 (colored below).) A POSITA would
have understood that elements 61 and 63 in Lowrey make up source/drain regions. (Ex. 1004,
¶127; compare also Ex. 1001, 26:40–45, 27:7–11, 27:19–21, Fig. 15(a)–(f) (elements 6, 8).)
39
A POSITA would have understood that the Lowrey-Noble combination teaches
“source/drain regions formed on both sides of the gate electrode within the active area.” (Ex.
1004, ¶¶124–29, see also §V.B.1.)
b. The “silicide layers” limitation
A POSITA would have understood that the Lowrey-Noble combination teaches that “the
first silicide layers are formed on the source/drain regions.” (Ex. 1004, ¶¶109–11, 124–29; see
also supra §V.B.1.) This is explained in sections V.B.2.f and V.B.4.a above.
Claim 8 is obvious over Lowrey and Noble 5.
Claim 8 depends from claim 1 (see §V.B.2) and further recites “a third silicide layer
formed on the interconnection.” The ’174 patent acknowledges a third silicide layer formed on
the interconnection is part of a “conventional trench isolation and a MOSFET having the salicide
structure.” (Ex. 1001, 3:53–55, 4:3–19, 5:1–11, Figs. 19, 20(a)–20(e) (elements 109b, colored).)
40
Lowrey also discloses “a third silicide layer formed on the interconnection.” For
example, “all exposed conductive regions (i.e., . . . N-channel interconnects 57, . . .) have been
silicided with titanium in a conventional self-aligned process.” (Ex. 1017, 10:3–22, Fig. 12
(colored and annotated below); compare also Ex. 1001, 27:18–33, Fig. 15(a)–(f) (element 9b).)
In this process, “[a] layer or titanium metal is sputter deposited . . . on top of all the circuitry.”
(Ex. 1017, 5:61–63.) Then, “[a] sintering step causes the titanium to react with all unoxidized
silicon (i.e., all gates and source/drain regions for both N-channel and P-channel transistors) to
form titanium silicide.” (Id., 5:63–66.) A chemical treatment “remove[s] all unreacted titanium.”
(Id., 5:66–6:1.)
A POSITA would have understood that the Lowrey-Noble combination teaches “a third
silicide layer formed on the interconnection.” (Ex. 1004, ¶¶130–33; see also supra §V.B.1.)
Claim 9 is obvious over Lowrey and Noble 6.
Claim 9 depends from claim 1 (see §V.B.2) and recites that “the trench isolation has an
upper surface higher than the surface of the active area.” The ’174 patent acknowledges this is
part of a “conventional trench isolation and a MOSFET.” (Ex. 1001, 3:53–55, 3:64–4:8, 4:45–
58, 4:16–19, Figs. 19, 20(a)–20(e) (colored below).)
41
Noble also discloses “the trench isolation has an upper surface higher than the surface of
the active area.” According to claim 1, the “active area” is the “active area of a semiconductor
substrate.”7 Noble states, “The term ‘raised trench’ refers to the fact that the trench extends
beyond the surface of substrate 10 to the top of the gate stack.” (Ex. 1015, 4:17–19; see also
Title, 1:7–10, Figs. 12, 13 (colored).) By definition, Noble’s raised trench must extend beyond
the surface of the active area of the semiconductor substrate. This is shown below in color and
annotated Figures 12 and 13 of Noble.
7 The raised source/drain 154 in Noble is a layer either deposited or grown on the silicon substrate; it is not
formed “of” the silicon substrate as the source/drain regions 138 are. (Ex. 1004, ¶137; Ex. 1015, 6:13–24.) Claim 5
of Noble confirms this by reciting: “said source and drain located in single crystal silicon, said transistor further
comp[ri]sing a raised source and drain.” (Ex. 1015, 7:21–23.) The raised source and drain are not “of” the single-
crystal silicon substrate.
42
Lowrey further teaches “the [LOCOS] isolation has an upper surface higher than the
surface of the active area.” This is shown below in colored Figure 12. (Compare also Ex. 1001,
Fig. 15(a)–(f).)
A POSITA would have understood that the Lowrey-Noble combination teaches that “the
trench isolation has an upper surface higher than the surface of
the active area.” (Ex. 1004, ¶¶134–38; see also supra §V.B.1.)
Claim 10 is obvious over Lowrey and Noble 7.
Claim 10 depends from claim 1 (see §V.B.2) and further recites “a lower portion of the
interconnection provided on the upper surface of the trench isolation is located higher than the
surface of the active area.” The ’174 patent acknowledges this is part of a “conventional trench
43
isolation and a MOSFET.” (Ex. 1001, 3:53–55, 3:64–4:8, 4:45–58, 4:16–19, Figs. 19, 20(a)–
20(e) (colored below).)
Noble also discloses “a lower portion of the interconnection provided on the upper
surface of the trench isolation is located higher than the surface of the active area.” According to
claim 1, the “active area” is the “active area of a semiconductor substrate.”8 Noble states, “The
term ‘raised trench’ refers to the fact that the trench extends beyond the surface of substrate 10 to
the top of the gate stack.” (Ex. 1015, 4:17–19; see also Title, 1:7–10, Figs. 12, 13, colored
below.) By definition, Noble’s raised trench must extend beyond the surface of the active area
[of the semiconductor substrate].
8 The raised source/drain 154 in Noble is a layer either deposited or grown on the silicon substrate; it is not
formed “of” the silicon substrate as the source/drain regions 138 are. (Ex. 1004, ¶142; Ex. 1015, 6:13–24.) Claim 5
of Noble confirms this by reciting: “said source and drain located in single crystal silicon, said transistor further
comp[ri]sing a raised source and drain.” (Ex. 1015, 7:21–23.) The raised source and drain are not “of” the single-
crystal silicon substrate.
44
Lowrey further teaches “a lower portion of the interconnection provided on the upper
surface of the [LOCOS] isolation is located higher than the surface of the active area.” This is
shown below in Figure 12 (colored below). (Compare also Ex. 1001, Fig. 15(a)–(f).)
A POSITA would have understood that the Lowrey-Noble combination teaches “a lower
portion of the interconnection provided on the upper surface of the trench isolation is located
45
higher than the surface of the active area.” (Ex. 1004, ¶¶139–44; see also supra §V.B.1.)
Claim 11 is obvious over Lowrey and Noble 8.
Claim 11 depends from claim 1 (see §V.B.2) and further recites “the interconnection is
composed of the same material as the gate electrode.” The ’174 patent acknowledges that “a
conventional semiconductor device” included “a gate interconnection 107b made of the same
polysilicon film as that for the gate electrode 107a.” (Ex. 1001, 3:66–67; see also 1:52–2:6,
3:53–4:3, 4:36–41, Figs. 17 (elements 4a, 4b, colored below), 20(c)–20(e) (elements 107a, 107b,
colored below).)
Lowrey also discloses that “the interconnection is composed of the same material as the
gate electrode.” Lowrey teaches the “deposition of a polysilicon layer, masking of the poly layer
with a fourth photomask, and a first etch of the poly layer to create gates [56] and interconnects
[57] for N-channel devices and an unbroken layer of poly in the N-well regions.” (Ex. 1017,
7:14–20; see also 8:42– 47, Figs. 5, 12 (colored below); compare also Ex. 1001, 21:57–61,
26:40–50, Fig. 15(a)–(f) (elements 4a, 4b).)
46
A POSITA would have understood the Lowrey-Noble combination teaches “the
interconnection is composed of the same material as the gate electrode.” (Ex. 1004, ¶¶145–48;
see also supra §V.B.1.)
Claim 12 is obvious over Lowrey and Noble 9.
Claim 12 depends from claim 1 (see §V.B.2) and further recites “the gate electrode and
the interconnection has at least a polysilicon film.” The ’174 patent acknowledges that “a
conventional semiconductor device” included “a gate interconnection 107b made of the same
polysilicon film as that for the gate electrode 107a.” (Ex. 1001, 3:66–67; see also 1:52–2:6,
3:53–4:3, 4:36–41, Figs. 17 (elements 4a, 4b colored below), 20(c)–20(e) (elements 107a, 107b
colored below).) A structure in which the gate electrode and the interconnection has at
least a polysilicon film is admitted prior art. (See id.)
47
Lowrey also discloses that “the gate electrode and the interconnection has at least a
polysilicon film.” Lowrey teaches the “deposition of a polysilicon layer, masking of the poly
layer with a fourth photomask, and a first etch of the poly layer to create gates [56] and
interconnects [57] for N-channel devices and an unbroken layer of poly in the N-well regions.”
(Ex. 1017, 7:14–20; see also 8:42– 47, Figs. 5, 12 (colored below); compare also Ex. 1001,
21:57–61, 26:40–50, Fig. 15(a)–(f) (elements 4a, 4b).)
A POSITA would have understood that the Lowrey-Noble combination teaches “the gate
electrode and the interconnection has at least a polysilicon film.” (Ex. 1004, ¶¶149–52; see also
supra §V.B.1.)
Claim 14 is obvious over Lowrey and Noble 10.
Claim 14 depends from claim 1 (see §V.B.2) and further recites “the first and second L-
shaped sidewalls are made of the same insulating film.” The ’174 patent acknowledges that “a
conventional semiconductor device” included sidewalls 7a and 7b on both the gate electrode and
interconnection. (Ex. 1001, 1:52–2:6, 2:55–62, Fig. 17 (colored below); see also supra
§§V.B.2.e, V.B.2.h.)
48
Lowrey discloses “the first and second L-shaped sidewalls are made of the same
insulating film” by teaching “thermal oxidation or chemical vapor deposition (CVD) to create a
mini-spacer oxide layer 62” (Ex. 1017, 8:58–9:2), which is “etched with a first anisotropic etch .
. . to form a first set of sidewall spacers 81 for N-channel transistor gates 56 [and] N-channel
interconnects 57” (id., 9:6–12). (See also id., 7:21–25, 11:28–29, Figs. 6, 12 (colored below);
compare also Ex. 1001, 26:45–47, 26:63–27:8, Fig. 15(a)–(f) (elements 32a, 32b).)
A POSITA would have understood that the Lowrey-Noble combination teaches “the first
and second L-shaped sidewalls are made of the same insulating film.” (Ex. 1004, ¶¶153–56; see
also supra §V.B.1.)
49
Claim 16 is obvious over Lowrey and Noble 11.
Claim 16 depends from claim 5 (see §V.B.4) and recites (1) “wherein the source/drain
regions include low-concentration source/drain regions and high-concentration source/drain
region” and (2) “the first silicide layers are formed on the high-concentration source/drain
regions.” The ’174 patent acknowledges “a conventional semiconductor device” included low-
concentration source/drain regions (6, 106a) and a high-concentration source/drain regions (8,
106b), including in “a semiconductor device including the conventional trench isolation and a
MOSFET having the salicide structure.” (Ex. 1001, 1:52–2:6, 2:51–67, 3:53–4:15, Figs. 17
(elements 6, 8), 20(e) (elements 106a, 106b); see also supra §§V.B.2.e, V.B.2.h.) As Figure 17
and 20(e) (both annotated and colored below) show, both limitations of claim 16 constitute
admitted prior art. This is the LDD (lightly-doped drain) structure. (Id., 14:60–67, Figs. 3(a)–
3(f).)
50
Lowrey also discloses “the source/drain regions include low-concentration source/drain
regions and high-concentration source/drain region.” Lowrey is directed to “high-performance
LDD-type N-channel transistors.” (Ex. 1017, 4:9–13; see also Abstract, 1:7–14.) A POSITA
would have understood LDD devices have source/drain regions with both low- and high-
concentration regions. (Ex. 1004, ¶159.)
Lowrey discloses “lightly-doped n-type source/drain regions 63 . . . offset from the
vertical boundaries of punch-through implant regions 61 by the vertical segments of mini-spacer
oxide layer 62.” (Ex. 1017, 8:66–9:2, Fig. 8 (element 61).) A POSITA would have understood
this constitutes a “low-concentration source/drain region” because it is lightly doped and
therefore contains a low concentration of dopant material. (Ex. 1004, ¶159.) Lowrey further
discloses “heavily doped n-type source/drain regions 82 for N-channel devices.” (Ex. 1017,
9:18–22, Fig. 8 (element 82)). A POSITA would have understood this constitutes a “high-
concentration source/drain region” because it is heavily doped and therefore contains a high
concentration of dopant material. (Ex. 1004, ¶159.) (See also id., 5:1–10, 11:41–47, Fig. 12
(below); compare also Ex. 1001, 23:8–11, 26:40–45, 27:9–15, Fig. 15(a)–(f) (elements 6, 8).)
Lowrey also discloses “the first silicide layers are formed on the high-concentration
source/drain regions.” Lowrey teaches that “all exposed conductive regions (i.e., . . . active areas
51
121 for both N and P-channel devices) have been silicided.” (Ex. 1017, 8:53-9:2, 10:3–15, Fig.
12 (below).) As seen from Figure 12 below, the silicide forms on the high-concentration source-
drain regions, which is typical. (Ex. 1004, ¶160; Ex. 1001, 3:53–4:15, Fig. 20(e).) (See also Ex.
1017, 5:1–10, 11:41–47, Fig. 12 (colored and annotated below); compare also Ex. 1001, 27:20–
29, Fig. 15(a)–(f) (element 9c).)
A POSITA would have understood that the Lowrey-Noble combination teaches “the
source/drain regions include low-concentration source/drain regions and high-concentration
source/drain region, and the first silicide layers are formed on the high-concentration
source/drain regions.” (Ex. 1004, ¶¶157–62; see also supra §V.B.1.)
C. The Lowrey-Ogawa combination renders claims 1, 4, 5, 8–12, 14, and 16 obvious
As explained in Section V.B, Lowrey teaches every limitation of the challenged claims
except trench isolation. A POSITA would have understood that Ogawa’s trench isolation was a
known substitute for Lowrey’s LOCOS isolation. (Ex. 1004, ¶163; see also Ex. 1009, 1:31–2:24;
Ex. 1011, 4:8–16; Ex. 1012, 3:3–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1015, Title,
1:7–10, 2:53–57, 4:14–23, Figs. 12, 13.) The combined teachings discussed in this section refer
to the teachings of Lowrey, with its LOCOS isolation replaced by Ogawa’s trench isolation.
52
A POSITA would have combined the teachings of Lowrey and Ogawa 1.
Many of the same reasons that would have compelled a POSITA to replace Lowrey’s
LOCOS with Nobles’s STI also would have compelled a POSITA to replace Lowrey’s LOCOS
with Ogawa’s trench isolation. (Ex. 1004, ¶164; see also §§II.B, V.A.3, V.B.1.)
a. Admitted prior art teaches replacing LOCOS with known trench isolation
The ’174 patent acknowledges trench isolation, including trench isolation with a top
surface higher than the surface of the semiconductor substrate, as prior art. (See supra
§V.B.1.a.)
b. Contemporary references teach replacing LOCOS with a known trench isolation
Similar to the admitted prior art of the ’174 patent, other contemporary references also
describe the well-known transition away from LOCOS (as disclosed by Lowrey) toward trench
isolation (as disclosed by Ogawa). (See supra §V.B.1.b.)
c. Additional references teach that LOCOS and trench isolation were interchangeable
Other references also demonstrate that replacing Lowrey’s LOCOS with Ogawa’s trench
isolation would have constituted a simple substitution of one known element for another
according to known methods to achieve predictable results. (See supra §V.B.1.c.)
d. Lowrey and Ogawa are in the same field of endeavor and have similar structures
Lowrey and Ogawa are similar device structures. They are in the same field of
endeavor, as both disclose structures having MOSFETs in an active region and interconnections
on a raised isolation. (Ex. 1017, Abstract, 1:7–9, 1:17–21, 2:18–20, 8:31–52, Fig. 12; Ex. 1010,
5:39–56, 7:13–30, Figs. 5(a)–5(c), 6; Ex. 1004, ¶167.)
53
Both Lowrey and Ogawa also disclose many of the elements of the challenged claims: a
silicon substrate (Ex. 1017, 7:57–64; Ex. 1010, 7:43–47, Fig. 5(c)), a raised isolation region
(Ex. 1017, 1:64–2:32, 8:31–35; Ex. 1010, 7:43–47, Fig. 5(c)), gate dielectric (Ex. 1017, 8:37–
52; Ex. 1010, 7:43–47, Fig. 5(c)), gate electrode (Ex. 1017, 8:44–47, 10:3–15; Ex. 1010, 7:51–
56, 8:35–38, Fig. 5(c)), source/drain regions (Ex. 1017, 8:53–9:2, 9:18–22, 10:3–15; Ex. 1010,
8:3–7, Fig. 5(c)), silicide regions (Ex. 1017, 10:3–15; Ex. 1010, 7:51–56, 8:67–9:5, Fig. 5 (c)),
and interconnections (Ex. 1017, 7:14–20, 8:44–47, 9:6–12, 10:3–15; Ex. 1010, 7:51–56, 8:67–
9:5, Fig. 5(c)).
The illustrated embodiments of Lowrey (Figure 12) and Ogawa (Figure 5(c)) appear
below with annotations, demonstrating their similarities.
54
e. Combining Lowrey and Ogawa had known benefits
The combined disclosures of Lowrey and Ogawa provide numerous advantages.
Lowrey’s spacers mask the substrate during junction formation to more precisely control doping
profiles in the source/drain regions. Lowrey discloses L-shaped “mini-spacer oxide layer 62,”
which may be used “to coat the sides of transistor gates 56, so that when the wafer is subjected to
a low-dosage phosphorus implant, . . . source/drain regions 63 [are] offset from the vertical
boundaries of punch-through implant regions 61 by the vertical segments of mini-spacer oxide
layer 62.” (Ex. 1017, 8:62–9:2.) These mini-spacers similarly facilitate the formation of a self-
aligned silicide contact to lower interconnection resistivity and simplify processing. (Id., 9:68–
10:42, Fig. 12.)
Many benefits of Ogawa complement Lowrey’s device structures. Ogawa teaches
“buried insulating layers” that isolate MOSFETs in an integrated circuit. (Ex. 1010, 1:8–15,
5:39–56, Fig. 5(c).) Ogawa explains “a process which is called local oxidation of silicon
[LOCOS] is available, and it is well known that this process has various advantages in the
aspects of easy production of durable wiring which is free from potential discontinuation thereof
and the potential employment of self-alignment and the like.” (Id., 1:26–31.) But “this local
55
oxidation of silicon [LOCOS] has drawbacks,” such as the bird’s beak and others. (Id., 1:31–33,
1:42– 57, Fig. 1; see also supra §II.B.1.)
According to Ogawa, the bird’s beak of LOCOS “causes a degradation of dimensional
accuracy.” (Id., 1:40–42, Fig. 1.) Ogawa also notes, “There is now a tendency in which the
dimensions of each element is decreased in order to satisfy requirements for a larger quantity of
elements fabricated in a chip and also for a larger quantity of elements fabricated in the unit area
of a chip.” (Id., 1:17–21.) Although device densities had not yet reached the dimensional limits
of LOCOS by the early 1980s when the Ogawa application was filed, Ogawa illustrates that the
problem was already foreseeable by those of ordinary skill in the art. (Id., 1:17–21, 1:40–42,
1:58–60, Fig. 1; Ex. 1004, ¶172.) Ogawa even teaches that LOCOS is “not necessarily
satisfactory for the production of a semiconductor device having minute patterns.” (Ex. 1010,
1:58–60.)
To address the problems of LOCOS, Ogawa discloses “an improvement applicable to
methods for production of buried insulating layers.” (Id., 1:8–15.) A POSITA would have
understood that combining the processes of Lowrey and Ogawa would have been a simple matter
of replacing the LOCOS oxidation in Lowrey with the trench isolation of Ogawa. (Ex. 1004,
¶173; see also Ex. 1009, 2:20–22.)
A POSITA would have been motivated to combine these teachings of Lowrey and Ogawa
to improve the associated device structures. (Ex. 1004, ¶174.) The spacer layers of Lowrey teach
how to mask the substrate during junction formation to more precisely control doping profiles,
facilitate silicide contact formation to lower interconnection resistivity, and insulate electrodes
and interconnections to eliminate short-circuits. (Ex. 1017, 8:62–9:2, 9:68–10:42; Ex. 1004,
¶174.) Ogawa teaches a trench oxide to eliminate the bird’s beak and other problems caused by
56
LOCOS. (Ex. 1010, 1:32–66, 3:49–58, 5:39–54, 8:14–24, Fig. 1; Ex. 1004, ¶174.) A POSITA
also would have understood that replacing Lowrey’s LOCOS with Ogawa’s trench isolation
would have been entirely compatible and would not have affected gate formation, source/drain
formation, L-shaped sidewall formation, silicide formation, or any other aspect relevant to the
challenged claims. (Ex. 1004, ¶¶80, 93, 173.) The combined disclosures of Lowrey and Ogawa
thus improve the manufacturability, durability, scalability, and performance of the associated
device structures. (Ex. 1004, ¶174.) A POSITA would have been motivated to combine the
teachings of Lowrey and Ogawa. (Id., ¶¶163–74)
Claim 1 is obvious over Lowrey and Ogawa 2.
a. [1.1] Lowrey teaches the preamble
Claim 1 recites “a semiconductor device.” (See §V.B.2.a.) As explained in section
V.B.2.a, Lowrey discloses a semiconductor device. (See also Ex. 1010, Abstract, 1:6–10.) A
POSITA would have understood that the Lowrey-Ogawa combination teaches “a semiconductor
device.” (Ex. 1004, ¶175; see also §§V.A.3, V.C.1.)
b. [1.2] the Lowrey-Ogawa combination teaches the “trench isolation” limitation
Claim 1 recites “a trench isolation surrounding an active area of a semiconductor
substrate.” (See §V.B.2.b.)
Ogawa discloses “a trench isolation surrounding an active area of a semiconductor
substrate.” It teaches “a method for production of a semiconductor device having a plurality of
FET’s, each of which is fabricated in an element fabrication area of a silicon (Si) substrate
surrounded by a buried insulating layer.” (Ex. 1010, 5:45–56; see also Title, Abstract, 1:8–15,
1:60–68, 3:12–48, Fig. 5(c).) As Figure 5(c) below (colored) illustrates, one embodiment of
Ogawa includes a MOSFET surrounded by trench isolation [52] having a surface that extends
57
above the source/drain regions [58] and supports a silicide interconnect [57]. (Id., 7:43– 8:24,
Figs. 5(a)–5(c).)
As explained in section V.B.2.b, although Lowrey does not disclose “a trench isolation
surrounding an active area of a semiconductor substrate,” it discloses LOCOS isolation
surrounding an active area of a semiconductor substrate. A POSITA would have understood that
the Lowrey-Ogawa combination teaches “a trench isolation surrounding an active area of a
semiconductor substrate.” (Ex. 1004, ¶¶176–79; see also supra §V.C.1.)
c. [1.3] Lowrey teaches the “gate insulator” limitation
Claim 1 recites “a gate insulating film formed over the active area.” (See §V.B.2.c.) As
explained in section V.B.2.c, Lowrey discloses this limitation. A POSITA would have
understood that the Lowrey-Ogawa combination teaches this limitation. (Ex. 1004, ¶180; see
also supra §§V.A.3, V.C.1.)
d. [1.4] Lowrey teaches the “gate electrode” limitation
Claim 1 recites “a gate electrode formed over the gate insulating film.” (See §V.B.2.d.)
As explained in section V.B.2.d, Lowrey discloses this limitation. A POSITA would have
understood that the Lowrey-Ogawa combination teaches this limitation. (Ex. 1004, ¶181; see
also supra §§V.A.3, V.C.1.)
58
e. [1.5] Lowrey teaches the “first L-shaped sidewall” limitation
Claim 1 recites “first L-shaped sidewalls formed over the side surfaces of the gate
electrode.” (See §V.B.2.e.) As explained in section V.B.2.e, Lowrey discloses this limitation. A
POSITA would have understood that the Lowrey-Ogawa combination teaches this limitation.
(Ex. 1004, ¶182; see also §§V.A.3, V.C.1.)
f. [1.6] Lowrey teaches the “silicide layers” limitation
Claim 1 recites “first silicide layers formed on regions located on the sides of the first L-
shaped sidewalls within the active area.” (See §V.B.2.f.) As explained in section V.B.2.f,
Lowrey discloses this limitation. A POSITA would have understood that the Lowrey-Ogawa
combination teaches this limitation. (Ex. 1004, ¶183; see also supra §§V.A.3, V.C.1.)
g. [1.7] the Lowrey-Ogawa combination teaches the “interconnection” limitation
Claim 1 recites “an interconnection formed on the trench isolation.” (See §V.B.2.g.) As
explained in section V.B.2.g, Lowrey discloses this limitation, except for a trench isolation (using
LOCOS isolation instead). As explained in section V.C.2.b, Ogawa discloses trench isolation.
A POSITA would therefore have understood that the Lowrey-Ogawa combination teaches “an
interconnection formed on the trench isolation.” (Ex. 1004, ¶184; see also supra §§V.A.3,
V.C.1.)
h. [1.8] Lowrey teaches the “second L-shaped sidewall” limitation
Claim 1 recites “second L-shaped sidewalls formed over the side surfaces of the
interconnection.” (See §V.B.2.h.) As explained in section V.B.2.h, Lowrey discloses this
limitation. A POSITA would have understood that the Lowrey-Ogawa combination teaches this
limitation. (Ex. 1004, ¶185; see also supra §§V.A.3, V.C.1.)
59
Claim 4 is obvious over Lowrey and Ogawa 3.
Claim 4 depends from claim 1 (see §V.C.1) and recites “a second silicide layer formed on
the gate electrode.” (See §V.B.3.) As explained in section V.B.3, Lowrey discloses this
limitation. A POSITA would therefore have understood that the Lowrey-Ogawa combination
teaches this limitation. (Ex. 1004, ¶187; see also supra §§V.A.3, V.C.1.)
Claim 5 is obvious over Lowrey and Ogawa 4.
Claim 5 depends from claim 1 (see §V.C.1) and recites (1) “source/drain regions formed
on both sides of the gate electrode within the active area” and (2) “wherein the first silicide
layers are formed on the source/drain regions.” (See §§V.B.4.a, V.B.4.b.) As explained in
sections V.B.4.a and V.B.4.b, Lowrey discloses these limitations. A POSITA would have
understood that the Lowrey-Ogawa combination teaches these limitations. (Ex. 1004, ¶189; see
also supra §§V.A.3, V.C.1.)
Claim 8 is obvious over Lowrey and Ogawa 5.
Claim 8 depends from claim 1 (see §V.C.1) and recites “a third silicide layer formed on
the interconnection.” (See §V.B.5.) As explained in section V.B.5, Lowrey discloses this
limitation. A POSITA would have understood that the Lowrey-Ogawa combination teaches this
limitation. (Ex. 1004, ¶191; see also supra §§V.A.3, V.C.1.)
Claim 9 is obvious over Lowrey and Ogawa 6.
Claim 9 depends from claim 1 (see §V.C.1) and recites “the trench isolation has an upper
surface higher than the surface of the active area.” (See §V.B.6.)
Ogawa further discloses that “the trench isolation has an upper surface higher than the
surface of the active area.” This is shown below in Figure 5(c) (colored). (See also supra
§V.C.2.b.)
60
As explained in section V.B.6, Lowrey discloses a LOCOS isolation with an upper
surface higher than the surface of the active area.
A POSITA would have understood that the Lowrey-Ogawa combination teaches “the
trench isolation has an upper surface higher than the surface of the active area.” (See also supra
§V.C.1.)
Claim 10 is obvious over Lowrey and Ogawa 7.
Claim 10 depends from claim 1 (see §V.C.1) and recites “a lower portion of the
interconnection provided on the upper surface of the trench isolation is located higher than the
surface of the active area.” (See §V.B.7.)
Ogawa further discloses “a lower portion of the interconnection provided on the upper
surface of the trench isolation is located higher than the surface of the active area.” This is
shown below in Figure 5(c). (See also supra §V.C.2.b.)
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As explained in section V.B.7, Lowrey discloses that a lower portion of the
interconnection provided on the upper surface of the [LOCOS] isolation is located higher than
the surface of the active area.
A POSITA would have therefore understood that the Lowrey-Ogawa combination teaches
“a lower portion of the interconnection provided on the upper surface of the trench isolation is
located higher than the surface of the active area.” (See also §V.C.1.)
Claim 11 is obvious over Lowrey and Ogawa 8.
Claim 11 depends from claim 1 (see §V.C.1) and recites “the interconnection is
composed of the same material as the gate electrode.” (See §V.B.8.) As explained in section
V.B.8, Lowrey discloses this limitation. A POSITA would have understood that the Lowrey-
Ogawa combination teaches this limitation. (Ex. 1004, ¶203; see also supra §§V.A.3, V.C.1.)
Claim 12 is obvious over Lowrey and Ogawa 9.
Claim 12 depends from claim 1 (see §V.C.1) and recites “the gate electrode and the
interconnection has at least a polysilicon film.” (See supra §V.B.9.) As explained in section
V.B.9, Lowrey discloses this limitation. A POSITA would have understood that the Lowrey-
Ogawa combination teaches this limitation. (Ex. 1004, ¶205; see also supra §§V.A.3, V.C.1.)
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Claim 14 is obvious over Lowrey and Ogawa 10.
Claim 14 depends from claim 1 (see §V.C.1) and recites “the first and second L-shaped
sidewalls are made of the same insulating film.” (See §V.B.10.). As explained in section
V.B.10, Lowrey discloses this limitation. A POSITA would have understood that the Lowrey-
Ogawa combination teaches this limitation. (Ex. 1004, ¶207; see also supra §§V.A.3, V.C.1.)
Claim 16 is obvious over Lowrey and Ogawa 11.
Claim 16 depends from claim 5 (see §V.C.3) and recites (1) “wherein the source/drain
regions include low-concentration source/drain regions and high-concentration source/drain
region” and (2) “the first silicide layers are formed on the high-concentration source/drain
regions.” (See §V.B.11.) As explained in section V.B.11, Lowrey discloses these limitations. A
POSITA would have understood that the Lowrey-Ogawa combination teaches these limitations.
(Ex. 1004, ¶209; see also supra §§V.A.3, V.C.1.)
TRIAL SHOULD BE INSTITUTED ON BOTH GROUNDS VI.
Because the disclosures and teachings of Ogawa differ from those of Noble, Global
believes that trial should be instituted on both the Lowrey-Noble and Lowrey-Ogawa
combinations. Instituting trial on both proposed grounds would not hinder the “just, speedy, and
inexpensive resolution of [this] proceeding.” 37 C.F.R. §42.1(b); see also Liberty Mutual Inc.
Co. v. Progressive Casualty Ins. Co., CMB2012-00003, Paper 7, at 2 (Oct. 25, 2012). If the
Board deems institution on both grounds inappropriate or somehow redundant, Global
respectfully requests institution on the Lowrey-Noble combination.
MANDATORY NOTICES UNDER 37 C.F.R. §42.8 VII.
A. Real Parties-In-Interest
The real party in interest is GlobalFoundries, Inc. (“Global”).
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B. Related Matters
This Petition includes the same grounds and exhibits against the ‘174 patent as asserted in
IPR2016-01247, filed by Taiwan Semiconductor Manufacturing Company Limited (“TSMC”),
which was instituted on January 4, 2017.
Patent Owner Godo Kaisha IP Bridge 1 filed two recent lawsuits asserting infringement
of the ’174 patent.
In Case No. 2:16-cv-00134-JRG-RSP (E.D. Tex. Feb. 14, 2016), Patent Owner has sued
Avago Technologies Ltd., Avago Technologies US, Inc., Broadcom Corporation, Broadcom
Limited, and LSI Corporation.
In Case No. 1:16-cv-00290-SLR (D. Del. Apr. 22, 2016), Patent Owner has sued
Omnivision Technologies, Inc.
In Case No. 2:10-cv-01668-JLL-CCC (D.N.J. Apr. 1, 2010), Panasonic Corporation,
Patent Owner’s predecessor-in-interest to the patent, previously asserted the ’174 patent against
Freescale Semiconductor. Inc.
TSMC concurrently filed, with IPR2016-01247, related inter partes petition IPR2016-
01246 challenging claims 1–3, 5–7, 9–12, and 14–18 of the ’174 patent on different grounds.
The present petition asserts that each of these claims is rendered obvious over Lowrey in view of
Noble, for example, because it would have been obvious to substitute Noble’s trench isolation for
Lowrey’s LOCOS isolation. In contrast, the related petition provides alternative and equally
compelling invalidity grounds based on Lee in view of Noble, for example, because it would have
been obvious to substitute Noble’s STI for Lee’s LOCOCS isolation.
The Petitioner is concurrently filing an inter partes petition that has the same grounds and
exhibits as asserted in IPR2016-01246 against the ‘174 patent. IPR2016-01246 was also filed by
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TSMC and was instituted on January 4, 2017.
As previously asserted by TSMC, Petitioner finds itself with two prior-art references that
disclose every element of the challenged claims.
Petitioner therefore respectfully requests that trial be instituted for this Global petition,
which is related substantively to TSMC petitions IPR2016-01246 and IPR2016-01247. Further,
Petitioner submits that instituting trial for this Global petition would result in no loss of efficiency
because this petition is substantively the same of TSMC petition IPR2016-01247.
C. Lead and Back-Up Counsel
Lead Counsel: Kent J. Cooper (Reg. No. 37,296; Tel. (512) 854-8091;
[email protected]), attorney at Law Office of Kent J. Cooper, 9407 Scenic Bluff
Drive, Austin, TX 78733.
Back-Up Counsel: Adam Floyd (Reg. No. 39,192; Tel. (303) 629-3410;
[email protected]), Dorsey & Whitney LLP, 1400 Wewatta Street, Suite 400, Denver,
CO 80202-5549.
D. Service Information
Global consents to service by e-mail at the following addresses:
[email protected] and [email protected].
CERTIFICATION UNDER 37 C.F.R. §42.24(D) VIII.
This Petition complies with 37 C.F.R. §42.24. As calculated by the “Word Count”
feature of Microsoft Word 2010, it contains 11,679 words, excluding the words contained in the
following: Table of Contents, Table of Authorities, List of Exhibits, Mandatory Notices Under
37 C.F.R. §42.8, Certification Under §42.24(d), and Certificate of Service.
PAYMENT OF FEES IX.
The required fees are submitted electronically under 37 C.F.R. §§42.103(a) and 42.15(a).
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If any additional fees are due during this proceeding, the Office may charge such fees to Deposit
Account No. 50-6826.
TIME FOR FILING PETITION X.
This Petition is being filed within one month after the date that institution of IPR2016-
01247 was granted on January 4, 2017. See 37 C.F.R. §42.122(b).
GROUNDS FOR STANDING XI.
Under 37 C.F.R. §42.104(a), Global certifies that the ’174 patent is available for inter
partes review and that Global is not barred or estopped from requesting inter partes review of
the ’174 patent to challenge the claims on the grounds identified in this Petition.
CONCLUSION XII.
For the reasons set forth above, the challenged claims are unpatentable. Trial should be
instituted, and the claims should be cancelled.
Respectfully submitted,
Dated: February 3, 2017 By: Kent J. Cooper, Reg. No. 37,296
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CERTIFICATE OF SERVICE
The undersigned certifies that the foregoing Petition for Inter Partes Review, the
associated Power of Attorney, and Exhibits 1001 through 1023 were served on February 3, 2017,
by express mail at the following address of record and addresses known to the petitioner as likely
to effect service and the address of record for the ’174 patent:
Address of Record Addresses Likely to Effect Service
Attn: Robert W. Zelnick Attn: Michael J. Fink MCDERMOTT, WILL & EMORY LLC GREENBLUM & BERNSTEIN, P.L.C. The McDermott Building 1950 Roland Clarke Place 500 North Capitol Street, NW Reston, VA 20191 Washington, DC 20001
Address of Courtesy Copies Attn: E. Robert Yoches
Finnegan, Henderson, Farabow, Garrett & Dunner LLP
901 New York Avenue, NW Washington DC 20001-4413
Kent J. Cooper Law Office of Kent J. Cooper 9407 Scenic Bluff Drive Austin, TX 78733 Telephone: (512) 854-8091