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Intel Architecture:Intel Architecture:Features & FuturesFeatures & Futures

For Servers & WorkstationsFor Servers & Workstations

Stephen L. SmithStephen L. SmithCorporate Vice President, Microprocessor Products GroupCorporate Vice President, Microprocessor Products GroupGeneral Manager, Santa Clara Processor DivisionGeneral Manager, Santa Clara Processor DivisionIntel Corporation Intel Corporation

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AgendaAgenda

ll High End IA Roadmap overviewHigh End IA Roadmap overviewll Foster Processor previewFoster Processor previewll MercedMercedTMTM Processor features & status Processor features & statusll McKinley Processor previewMcKinley Processor previewll SummarySummary

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High End IA RoadmapHigh End IA Roadmap

*Intel code name

. . .

FosterFosterMercedMercedTMTM

ProcessorProcessor

McKinleyMcKinley

‘98 ‘02

Per

form

ance

‘00 ‘01‘99

Pentium® IIPentium® IIXeonXeonTMTM

ProcessorProcessor

TannerTannerCascadesCascades

.25.25mm .18.18mm .13.13mm

FutureFutureIA-32IA-32

. . .

World class Server and Workstation Roadmap World class Server and Workstation Roadmap

Extends IA Headroom with 64 bit capabilityand scalability for high performance computing

Extends IA Headroom with 64 bit capabilityand scalability for high performance computing

Outstanding performance for 32 bit volume apps

Outstanding performance for 32 bit volume apps

. . .. . .

MadisonMadisonIA-64IA-64 Perf Perf

DeerfieldDeerfieldIA-64 Price/IA-64 Price/PerfPerf

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Solutions FocusSolutions Focus

*Intel code name

Server AppsServer Apps Workstation AppsWorkstation Apps

IA-32 deliversIA-32 delivers outstanding outstanding

performance andperformance andprice-performanceprice-performance

High end DCCHigh end DCC

MDAMDA

EDAEDA

DCC creation/designDCC creation/design

Entry DCCEntry DCC

Desktop PublishingDesktop Publishing

Mechanical DesignMechanical Design

IA-32 SoftwareIA-32 Software Eng Eng

Data Warehouse/DSSData Warehouse/DSSHigh Capacity OLTPHigh Capacity OLTPLOB/ERPLOB/ERPSecuritySecurityDirectory ServicesDirectory ServicesMessage TransactionMessage TransactionCollaborativeCollaborativePublicationPublicationFile & PrintFile & Print

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Solutions FocusSolutions Focus

*Intel code name

Server AppsServer Apps Workstation AppsWorkstation Apps

IA-32 deliversIA-32 delivers outstanding outstanding

performance andperformance andprice-performanceprice-performance

High end DCCHigh end DCC

MDAMDA

EDAEDA

DCC creation/designDCC creation/design

Entry DCCEntry DCC

Desktop PublishingDesktop Publishing

Mechanical DesignMechanical Design

IA-32 SoftwareIA-32 Software Eng Eng

Data Warehouse/DSSData Warehouse/DSSHigh Capacity OLTPHigh Capacity OLTPLOB/ERPLOB/ERPSecuritySecurityDirectory ServicesDirectory ServicesMessage TransactionMessage TransactionCollaborativeCollaborativePublicationPublicationFile & PrintFile & Print

High performance technical computingHigh performance technical computingVery large memoryVery large memory DB DBHighest-capacity OLTPHighest-capacity OLTPHighest end DSS SolutionsHighest end DSS Solutions

Highest end CAE AnalysisHighest end CAE Analysis

High end SoftwareHigh end Software Eng Eng

EDA verification/synthesisEDA verification/synthesis

High end technical analysisHigh end technical analysis

IA-64 extendsIA-64 extends IA features into IA features into

highest performancehighest performancecommercial &commercial &

technical computingtechnical computing

Complementing IA-32 and IA-64 products enableComplementing IA-32 and IA-64 products enablefull range of Server/Workstation solutionsfull range of Server/Workstation solutions

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Continuous IA-32Continuous IA-32InnovationsInnovations

Greater IPCGreater IPC

Frequency Boost Frequency Boost••Dual IndependentDual Independent

Bus ArchitectureBus Architecture

••Full speed cache busFull speed cache bus••Extended memory archExtended memory arch

••KatmaiKatmai New Instructions New Instructions

PerformancePerformance

19971997 19981998 19991999 20002000 20012001

FosterFoster

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Continuous IA-32Continuous IA-32InnovationsInnovations

Greater IPCGreater IPC

Frequency Boost Frequency Boost••Dual IndependentDual Independent

Bus ArchitectureBus Architecture

••Full speed cache busFull speed cache bus••Extended memory archExtended memory arch

••KatmaiKatmai New Instructions New Instructions

New 32-bit microarchitecture–Implements trace cache forinstruction decode–Enhances branch prediction

New 32-bitNew 32-bit microarchitecture microarchitecture––Implements trace cache forImplements trace cache forinstruction decodeinstruction decode––Enhances branch predictionEnhances branch prediction

Faster frequencytargeting 1GHzand beyond

Faster frequencyFaster frequencytargeting 1GHztargeting 1GHzand beyondand beyond

Large on-chipL1 and L2cache

Large on-chipLarge on-chipL1 and L2L1 and L2cachecache

Improved system throughput–Bus bandwidth of 3.2 GB/sec–Cache bandwidth increases

–L1 at 32 GB/sec, L2 at 8 GB/sec

Improved system throughputImproved system throughput––Bus bandwidth of 3.2 GB/secBus bandwidth of 3.2 GB/sec––Cache bandwidth increasesCache bandwidth increases

––L1 at 32 GB/sec, L2 at 8 GB/secL1 at 32 GB/sec, L2 at 8 GB/sec

PerformancePerformance

19971997 19981998 19991999 20002000 20012001

FosterFoster

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Merced™ Processor FPUMerced™ Processor FPU

ll 2 Extended Precision (EP)2 Extended Precision (EP) FMACs FMACs, 2 SP, 2 SP FMACs FMACs–– Execution of up to 8 SPExecution of up to 8 SP FLOPs FLOPs / cycle / cycle–– 4 EP4 EP FLOPs FLOPs / cycle / cycle

ll > 20x Pentium® Pro processor and ~3x Tanner> 20x Pentium® Pro processor and ~3x Tannerperformance on 3D graphicsperformance on 3D graphics

MemoryMemory128 FP128 FP

RegisterRegisterFileFile

Multiple read ports

Multiple write ports

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IA-32 Hardware ExecutionIA-32 Hardware Execution

InstructionInstructionCacheCache

ExecutionExecutionResourcesResources

IA-64 InstructionIA-64 InstructionDelivery & ControlDelivery & Control

IA-32 InstructionIA-32 InstructionDelivery & ControlDelivery & Control

IA-32 Engine:IA-32 Engine:•• IA-32 Instruction set decoderIA-32 Instruction set decoder•• Dynamic executionDynamic execution

Shared resources:Shared resources:•• ALUsALUs•• RegistersRegisters•• Data cacheData cache

The only 64-bit processor with completeThe only 64-bit processor with complete IA-32 binary compatibility IA-32 binary compatibility

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Merced™ Processor ManagesMerced™ Processor ManagesMemory LatencyMemory Latencyll Innovative three level cache hierarchy Innovative three level cache hierarchy

–– Separate instruction & data L0 cachesSeparate instruction & data L0 caches–– Larger, unified L1 cache on dieLarger, unified L1 cache on die–– L2 off die provides large overall capacityL2 off die provides large overall capacity

ll Highly efficient bus and memory utilizationHighly efficient bus and memory utilization–– Enhanced deferred transaction supportEnhanced deferred transaction support–– Cache line size optimized to conserve bandwidthCache line size optimized to conserve bandwidth–– Dedicated, full speed L2 bus frees system bus for MPDedicated, full speed L2 bus frees system bus for MP–– Increased page size up to 256MBIncreased page size up to 256MB

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Merced™ ProcessorMerced™ ProcessorError HandlingError Handlingll Extensive ECC coverage on processor and busExtensive ECC coverage on processor and bus

–– L1 cache, L2 cache, L2 bus, system bus dataL1 cache, L2 cache, L2 bus, system bus data

–– Full hardware support for correcting single bit ECC errorsFull hardware support for correcting single bit ECC errors

ll Enhanced machine check architectureEnhanced machine check architecture–– Processor and platform error correction via HW/ FWProcessor and platform error correction via HW/ FW

handshake and OShandshake and OS–– Data poisoning provides greater system availability throughData poisoning provides greater system availability through

process level error containmentprocess level error containment

ll Comprehensive error loggingComprehensive error logging–– Error type, cache level, cache tag/data, corrected errors,Error type, cache level, cache tag/data, corrected errors,

transaction type, etc.transaction type, etc.

Supplements numerous processor, platform andSupplements numerous processor, platform andOS features for enterprise-class RASOS features for enterprise-class RAS

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MercedMercedTMTM Processor Progress Processor Progress

On-track for samples targeted for mid-1999On-track for samples targeted for mid-1999

ll MicroarchitectureMicroarchitecture definition complete definition complete

ll Final stages of functional RTL validation-Final stages of functional RTL validation-booting OS kernelbooting OS kernel

ll Timing convergence exceeding goalsTiming convergence exceeding goals

ll Validation of circuit design making goodValidation of circuit design making goodprogressprogress

ll Comprehensive pre-silicon MP validation usingComprehensive pre-silicon MP validation usingthorough RTL co-simulation environmentthorough RTL co-simulation environment

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MercedMercedTMTM Cartridge Preview Cartridge Preview

EfficientEfficientheatheatdissipationdissipationtechnologytechnology

IntelInteldesigneddesignedstatic cachestatic cacheRAMRAMSeparateSeparate

signal &signal &powerpowerconnectionsconnectionsfor signalfor signalintegrityintegrity

Full speedFull speedcache buscache bus

Cost effective,Cost effective,performanceperformancesubstratesubstrate

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MercedMercedTMTM Platform Program Platform Program

Industry converging on IA to reapIndustry converging on IA to reapcommon hardware foundation benefitscommon hardware foundation benefits

ll Key server & workstation vendors with multiple designsKey server & workstation vendors with multiple designs–– Fault tolerant, massively parallel and technical computing designsFault tolerant, massively parallel and technical computing designs–– 4 to 512 MP servers and 2/4 MP workstations4 to 512 MP servers and 2/4 MP workstations

ll MultipleMultiple OSes OSes making good progress: UNIX and NT making good progress: UNIX and NT–– HP-UX, Solaris, SCO, SGI IRIX, Digital Unix, Novell Modesto, Win64HP-UX, Solaris, SCO, SGI IRIX, Digital Unix, Novell Modesto, Win64

ll Intel and industry shipping 64 bit SDKs andIntel and industry shipping 64 bit SDKs and pre-siliconpre-siliconsoftware development toolssoftware development tools

ll TopTop ISVs ISVs porting server and workstation applications porting server and workstation applicationsll Executing on PlanExecuting on Plan

–– Compiler optimization meeting key milestonesCompiler optimization meeting key milestones–– Multiple IA-64Multiple IA-64 OSes OSes and apps booting on Merced simulator and apps booting on Merced simulator–– Chipsets and systems designs on track for first samplesChipsets and systems designs on track for first samples

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McKinley ProcessorMcKinley Processor

ll McKinley extendsMcKinley extends Merced MercedTMTM processor processortechnologytechnology–– EnhancedEnhanced microarchitecture microarchitecture doubles IA-64 software doubles IA-64 software

performanceperformance>> Frequency : Target > 1Frequency : Target > 1 GHz GHz>> IPC : Increased number of execution unitsIPC : Increased number of execution units>> Very large, high speed on chip cachesVery large, high speed on chip caches

–– Bus is superset of Merced bus: ~3X bus bandwidthBus is superset of Merced bus: ~3X bus bandwidth

ll Full Merced & IA-32 software compatibilityFull Merced & IA-32 software compatibilityll Target production : Late ‘01Target production : Late ‘01

McKinley extends Merced processor benefitsMcKinley extends Merced processor benefits

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SummarySummaryll High performance IA server and workstation roadmapHigh performance IA server and workstation roadmap

–– Foster delivers outstanding performance for 32- bit appsFoster delivers outstanding performance for 32- bit apps

–– MercedMercedTMTM processor adds 64 bits, increased headroom/ scalability processor adds 64 bits, increased headroom/ scalability

–– McKinley extends Merced processor benefits with 2X performanceMcKinley extends Merced processor benefits with 2X performance

–– Future IA-64Future IA-64 proliferations proliferations planned for .13 planned for .13mm technology technology

ll Merced processor is on track for mid 2000 productionMerced processor is on track for mid 2000 production–– Systems, OS, Applications, Tools alignedSystems, OS, Applications, Tools aligned

ll Common IA foundation brings greater choice to highCommon IA foundation brings greater choice to highperformance segmentsperformance segments

–– Variety of hardware, software and channel choicesVariety of hardware, software and channel choices

IA is the Unifying ArchitectureIA is the Unifying Architecture