innovative processing for gan power devices

Compact Power Supplies Based on Heterojunction Switching in Wide Band Gap Semiconductors

NC STATE UNIVERSITY UCSB

Innovative Processing for GaN Power Devices

Ilan Ben-Yaacov, Yan Gao, Sarah E. Monteith, S. DenBaars, U. Mishra, E.L. Hu

University of California, Santa Barbara

with thanks to

Andrew Huntington, Stacia Keller, Andreas Stonas (UCSB)



Outline

• Next steps for (Al)GaAs-GaN HBTs– Wafer fusion

• Current Aperture Vertical Electron Transistor (CAVET)– Through MOCVD regrowth

– Through selective etching



Structure• AlGaAs-GaAs emitter-base

– high mobility carriers– well-understood emitter-base interface– p contacts to GaAs base (rather than top GaN)

• n-GaN collector– High-breakdown voltages possible

n-GaN Collector

n-AlGaAs Emitter

p-GaAs Basefused

interface

In previous reviews• demonstrated reliable fusion of GaAs-GaN : 500 -750 oC, 0.5-2 hours• used SIMS, TEM, I-V measurements to characterize fused interface• Carried out initial electrical characterization of (Al)GaAs-GaN HBT

Formation of (Al)GaAs-GaN HBT



5 nm

Fused at 750oC for 15 minutes

Ex situ fusion and the fused interface

Spray etch to removeGaAs substrate

StartingMaterials

GaN

GaAs

Fuse under 2MPa pressureat 500-750°C for 0.25-2hr

GaAs

A uniform, relatively smooth interface

GaAs

GaN

Courtesy J. Jasinski

1 to 4monolayers



>2 m uid-GaN (~5x1016 Si)

(001) sapphire substrate

(1x1019 C)

120 nm n-AlxGa1-xAs(5x1017 Si, x = 0.3)

30 nm Graded AlxGa1-xAs(5x1017 Si, x = 0 - 0.3)

30 nm Graded AlxGa1-xAs(5x1017 Si, x = 0.3 – 0)

100 nm n-GaAs (1x1019 Si)

150 nm p-GaAs

Au/Ge/Ni415oC

Zn/Au

Al/Au

(Al)GaAs-GaN HBT Structure

GaAs/GaN Interfacefused at 750oC for 1 hour

Common Emitter Characteristic IB Step Size = 2mA

00.20.40.60.8

11.21.41.61.8

0 5 10 15 20 25 30

VEC (Volts)

Co

llec

tor

Cu

rren

t (m

A)

20 micron x 52 micron emitter mesa



(Al)GaAs-GaN HBT IV Characteristics

Common Emitter Characteristic IB Step Size = 2mA

00.20.40.60.8

11.21.41.61.8

0 5 10 15 20 25 30

VEC (Volts)

Co

llec

tor

Cu

rren

t (m

A)

• Relatively small VCE offset

(~1 V): can be improved with anneal p-GaAs contacts

• Reasonably good output conductance (~ mA; few hundred A/cm2)

• Low current gain (< 1)– large base width (150 nm)

– dopant profile after fusion? (AlGaAs-GaAs and GaAs-GaN)

– recombination at the fused interface?



Gummel Plot

Gummel PlotHBT Sample H10

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2

VEB (Volts)

Cur

rent

(m

A)

IB (mA) IC (mA)

Common Emitter CharacteristicHBT Sample H10

Small Step in Base Current [0.1mA]

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 2 4 6 8 10

VCE (Volts)

Col

lect

or C

urre

nt (

mA

)

IB = 0 IB = 0.1mA IB = 0.2mA IB = 0.3mA

IB = 0.4mA IB = 0.5mA IB = 0.6mA IB = 0.7mA

IB = 0.8mA IB = 0.9mA



(Al)GaAs-GaN HBT: Next Steps

-5

0

5

10

15

20

25

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Applied Bias (Volts)

Cu

rren

t D

ensi

ty (

A/c

m2)

6.5x10-3 Wcm2

Base-Emitter Junction

(pGaAs-nAlGaAs)

• Set fused interface slightly into collector region

- n-AlGaAs/p-GaAs/n-GaAs/n-GaN

- Allows for uncertainties in GaAs-GaN band lineups

- Previous experience indicates that n-AlGaAs/p-GaAs/n-GaAs structure will go through fusion process intact

• Reduce base layer thickness• Carry out fusion at lower temperatures

- Minimize dopant diffusion across fused interface

Same characteristicsbefore and after fusion

-3.5-3

-2.5-2

-1.5-1

-0.50

0.51

1.5

0 100 200 300 400 500 600 700 800

Depth from Emitter Surface (nm)

Ban

d E

nerg

y (e

V)

E B C

n-AlGaAsp-GaAs/ n-GaAs

GaN



• Current Aperture Vertical Electron Transistor

• Current flows vertically from sources to drain• Electron flow through aperture modulated by the gate• High-field region below the gate instead of at the surface (as in a HEMT)

• Higher breakdown voltages• When optimized, reduction in DC-RF dispersion

Source Source

Drain

AlGaN

Gate

225 Å

.25 m

2 m

GaN:Fe (semi-insulating) GaN:Fe.4 m

UID GaN

GaN:Si (n -type)

Sapphire Substrate

2DEG

High-Field Region

IDS

Regrown Channel GaN CAVET



1. MOCVD growth of drain and insulating regions

2. Cl2 RIE etch of aperture

region

3. MOCVD maskless regrowth of aperture and source region, pattern device mesa, and deposit metal contacts

CAVET Process Flow



CAVET: Theoretical Models

Ideal device, pinch-offoccurs between gate andaperture.

1.

When aperture regionis too insulating, pinch-off occurs across theaperture and currentdoes not saturate due toDIBL.

2.



CAVET: DC Electrical Results

For this device:• Ws = 2*Wg = 200 m, Lap = 0.6 m, and

Lgo = 2 m

• IDSS = 430 mA/mm, extrinsic gm = 100 mS/mm,

Vp = - 4 V

• Parasitic leakage current observed at pinch-off

For all devices:• IDSS and leakage current at pinch-off

independent of Lap

• IDSS and pinch-off leakage current increase

when Lgo is decreased



Etched-Aperture GaN CAVET

InxGa1-xN (600Å) x = 0.070.5 micron uid- GaN

InGaN

1.7 microns n- GaN

AlGaNAlGaNAl0.30Ga0.70N (220Å)

sapphire

sapphire

1000 W Hg/Xe lamp (~20 W/cm2)

Au wire

Sample

KOH:H2O

GaN filter

• Create an etched aperture • Use an etch process that rapidly

and selectively etches a sacrificial layer (InGaN) PhotoElectroChemical (PEC) Wet Etching

Pt coil



Bandgap-Selective PEC Etching

GaN Filter Transmission Spectra

0

0.2

0.4

0.6

0.8

1

320 360 400 440 480

Wavelength (nm)

Tra

nsm

issi

on

n-GaN Filter

p-GaN Filter

Approximate absorption edge of InGaN

h

GaN GaNInGaN

GaN filter will select wavelengths that only excite carriers in InGaN

GaN

sapphire

GaNInGaN

SiO2

Ni/Au

After Etching3 min, 1000 W, 2.2 M KOHI bias = 40 mA

PROBLEM: roughness of undercut etchRESPONSE: Taguchi experiment to identify most critical etch parameters



0.55M

2.2M

8.8M

2.71V

1.24V

0.62V

2.71V

1.24V

1.24V 2.71V 0.62V

170W 400W 600W

top view of undercutMRS

PEC etching

50µm

0.62V

Etched area Unetched area

Illuminationpower

KOH concentration• Systematically varied

- KOH concentration- illumination power- bias applied to

sample• Evaluated

- lateral etch rate- smoothness of etch

front- roughness of

etched surface• Overwhelming dependence on KOH concentration: lower concentration produced smoother etched surface

TOP-DOWN VIEWS OF ETCHED STRUCTURES

Optimization of Etch Conditions



Etched CAVET: future work

• Taguchi experiments helped to identify critical etch parameter: KOH concentration

• Samples etched at 0.001 M KOH, 1000W, no bias, showed smooth, well-controlled undercut

• Future work: fabricate full CAVET device, using optimized etch conditions



Summary

• Initial electrical characterization of first (Al)GaAs-GaN fused HBT– Try ‘setback’ of fused interface, lower fusion temperature,

thinner base region

• Initial CAVET device results for regrown structures– Optimize device structure and growth conditions

• Optimization of PEC etching for etched CAVET devices– Fabricate and characterize full CAVET device

innovative processing for gan power devices

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