imx6 dual-quad processor timing model creation ddr3l-1066

8/10/2019 IMX6 Dual-Quad Processor Timing Model Creation DDR3L-1066

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Edality

3-i Zagorodnyi lane4a - 411220036-BY, MinskRepublic of Belarus

Phone : +375 17 2569064Fax : +375 17 2569064

email : [email protected]

From : Alexander Karas Date : 23 August 2013

Phone : +375 29 5513955 Ref : iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066.doc

To Hans Klos (Sintecs) For info Tom Berends (Sintecs)

Subject : iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066

Classification: internal

iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066

DOCUMENT CHANGE & HISTORY RECORD

Maintainer Last update Status Version CommentAlexander Karas 06-04-2013 Draft 0.1 Timing analysis report

Reference documents

Ref. Title Document nameModified

dateStatus

1.1i.MX 6Dual/6Quad Automotive andInfotainment Applications Processors

IMX6DQxxEC.pdfRev. 1,

11/2012

1.2

1.3

Analyses performed with the Mentor Graphics high-speed board design analyses tooling (Hyperlynx).


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Date : 23 August 2013

Ref : iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066.docSubject: iMX6_Dual-Quad_DDR3L-1066 Classification: internal

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Index

1

i.MX6Solo processor timing analysis .................................................. 3

1.1 Introduction .......................................................................................................... 31.2 Project activities and deliverables ....................................................................... 31.3 Analysis software information .............................................................................. 31.4 Critical Net List .................................................................................................... 3

2

Timing model ........................................................................................ 4

3.1

DDR3 timing model i.MX6Dual/Quad Memory Controller (1066 MT/s) ............... 4

3.1.1 Deriving tCKAC(min) and tCKAC(max) ........................................................ 63.1.2 Deriving tCKCTL(min) and tCKCTL (max). 63.1.3 Deriving tCKDQS(min) and tCKDQS(max) .................................................. 63.1.4 Deriving tDQSDQ(min) and tDQSDQ(max) .................................................. 73.1.5 Deriving tDS and tDH ................................................................................... 73.1.6 Summary of DDRx Wizard Parameters ........................................................ 7

3.2 DDR3 timing model memory device (Micron, JEDEC DDR3-1066 model) ........ 11

3 Conclusion .......................................................................................... 13


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1 i.MX6Dual/Quad processor timing analysis

1.1 Introduction

A timing analysis is done for the i.MX6-Dual/Quad DDR3L Memory Controller. Thisdocument describes the results of these analyses.

In this chapter, all the information, needed for setting up the simulation database ismentioned.

1.2 Project activities and deliverables

For the Timing analyses of the i.MX6-Dual/Quad processor design, the following tasksand activities had to be done:

1. Collect i.MX6-Dual/Quad Memory Controller timing information

2. Creation timing model

3. Analysis document

1.3 Analysis software information

Simulator:

- Mentor Graphics HyperLynx Timing Model Wizard : 8.2.1

1.4 Critical Net List

GROUP NAME FREQ DESCRIPTION

DDR3L-1066 DRAM_DQS* 533 MHz DDR3 strobe

DRAM_DQ* 533 MHz DDR3 data

DRAM_CK* 533 MHz DDR3 clock

DRAM_ADDR* 266 MHz DDR3 address

DRAM_CMD* 266 MHz DDR3 command

DRAM_CTRL* 266 MHz DDR3 control


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2 Timing model

2.1 DDR3L timing model i.MX6-Dual/Quad (1066 MT/s)

Freescale iMX6-Dual/Quad Memory Controller Datasheet Parameters Timing Diagram


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Parameters Definitions ValuetIS Add/Cmd/Ctrl signals setup time with relative to MCK 500 pstIH Add/Cmd/Ctrl signals hold time with relative to MCK 400 pstDS DQ/DQM setup time with relative to DQS 240 pstDH DQ/DQM hold time with relative to DQS 240 pstDQSS(min) DQS to CK skew (min) - 0.25 tCKtDQSS(max)

DQS to CK skew (max) + 0.25 tCKtDQSDQ(min) DQS to DQ valid data, Read cycle -225 pstDQSDQ(max) DQS to DQ valid data, Read cycle 225 ps


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2.1.1 Deriving tCKAC(min) and tCKAC(max) for i.MX6Solo Memory Controller

SpeedGrade tCK tIS tIHDDR3L-1066 1/533 MHz =1876 ps 500 ps 400 ps

tCKAC(min) tCKAC(max)

tCK + tIH = 1876 ps + 500 ps = 1376 ps tCKAC(max) = tIS = 400 ps

2.1.2 Deriving tCKCTL(min) and tCKCTL (max) for i.MX6Solo Memory Controller

SpeedGrade tCK tIS tIH

DDR3L-1066 1876ps 500 ps 400 ps

tCKCTL(min) tCKCTL(max)

tCK + tIH = 1876 ps + 500 ps = 1376 ps tCKAC(max) = tIS = 400 ps

2.1.1 Deriving tCKDQS(min) and tCKDQS(max) for i.MX6Solo Memory ControllerSpeedGrade tCK tDQSS(min) tDQSS(max)

DDR3L-1066 1876 ps - 0.25 * tCK 0.25 * tCKtCKDQS(min) tCKDQS(max)

tCKDQS(min) = -0.25 * tCK = -469 ps tCKDQS(max) = 0.25 * tCK = 469 ps


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2.1.2 Deriving tDQSDQ(min) and tDQSDQ(max) for i.MX6Solo Memory Controller

SpeedGrade tCK tDS tDH

DDR3L-1066 1876 ps 240 ps 240 pstDQSDQ(min) tDQSDQ(max)

0.5*tCK + tDH = 0.5 * 1876 +240 = 698 ps tDS = 240 ps

2.1.3 Deriving tDS and tDH for i.MX6Solo Memory Controller

SpeedGrade tCK tDQSDQ(min) tDQSDQ(max)

DDR3L-1066 1876 ps 225 ps 225 pstDS tDH

|tCISKEW(max)| = tDQSShift tDQSDQ(max) = 469 225 = 244 ps

|tCISKEW(min)| = 0.5*tCK tDQSShift tDQSDQ(min) = 938

469 225 = 244

2.1.4 Summary of DDRx Wizard Parameters for i.MX6-Dual/Quad Controller

DDRx Wizard Required Parameters Min (ps) Max (ps)

tCKAC 1376 400

tCKCTL 1376 400

tCKDQS 469 469

tDQSDQ 698 240tDS 244

tDH 244

Timing model in Hyperlynx:


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Address/Command timing

Control timing


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Read data timing


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2.2 DDR3 timing model memory device (Micron, JEDEC DDR3-1066 model)

This model (values) is supplied by the JEDEC committee and Micron DDR3 devicescomply with the JEDEC specification.

Clock vs. address/command/control constraints

Strobe to clock constraints (write)


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Setup and Hold constraints

Strobe delay relative to the clock (read)


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Data delay relative to the Strobe (read)

Conclusion

No timing issues found in the DDR3 interface.

imx6 dual-quad processor timing model creation ddr3l-1066

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