IMPLEMENTATION OF MIPS 64IMPLEMENTATION OF MIPS 64WITHWITH

VERILOG HARDWARE DESIGN VERILOG HARDWARE DESIGN LANGUAGELANGUAGE

BYBY

PRAMOD MENONPRAMOD MENON

CET520 S’03CET520 S’03

GOALS FOR THE PROJECTGOALS FOR THE PROJECT

To implement the MIPS 64 architecture with Verilog To implement the MIPS 64 architecture with Verilog hardware design language. hardware design language. Follow the ASIC design flow for implementationFollow the ASIC design flow for implementationUnderstand Verilog coding styles and optimize code designUnderstand Verilog coding styles and optimize code designUsing Verilog implement the single cycle Implementation Using Verilog implement the single cycle Implementation schemeschemeImplement Pipelined scheme using VerilogImplement Pipelined scheme using VerilogImprove Pipelining by adding forwarding unit and Hazard Improve Pipelining by adding forwarding unit and Hazard detection to prevent hazardsdetection to prevent hazardsUse a Branch optimization technique in the pipeline with Use a Branch optimization technique in the pipeline with VerilogVerilogCompare and draw conclusions between the single cycle, Compare and draw conclusions between the single cycle, Pipeline and pipeline with branch optimization based on Pipeline and pipeline with branch optimization based on parameters obtained on synthesis parameters obtained on synthesis

ASIC DESIGN FLOWASIC DESIGN FLOW1. Design Specification

2. Design Partition

3. Design Entry VerilogBehavioral Modeling

4. Simulation/FunctionalVerification

5. Design Integration and Verification

7. Synthesize and Map Gate-Level Netlist

6. Presynthesis Sign-Off

8. Post-synthesis Design Validation

9. Post-synthesis Timing Validation

10. Test Generation and Fault Simulation

11. Cell Placement, Scan Chain & Clock Tree

Insertion. Cell Routing

12. Verify Physical andElectrical Design Rules

13. Extract Parasitic

14. Design Sign-Off

Production ready Masks

VERILOG INTRODUCTIONVERILOG INTRODUCTIONVerilog is a Verilog is a Hardware Description Language (HDL)Hardware Description Language (HDL). . 1980s,A company called Gateway Design Automation developed a logic simulator, Verilog-XL, and with it a hardware description language.Cadence Design Systems acquired Gateway in 1989, and with it the rights to the language and the simulator. In 1990, Cadence put the language (but not the simulator) into the public domain, with the intention that it should become a standard, non-proprietary language. The Verilog HDL is now maintained by a non-profit making organization, Open Verilog International (OVI). OVI had the task of taking the language through the IEEE 1364-1995 standardization procedure.A Hardware Description Language is a language used to describe a digital system or A Hardware Description Language is a language used to describe a digital system or a component a component Simulation of designs before it goes to fabrication. Simulation of designs before it goes to fabrication. Different Levels – Switch , Gate , RTLDifferent Levels – Switch , Gate , RTLWhy HDL?Why HDL?Millions of TransistorsMillions of TransistorsExplore Architectural alternativesExplore Architectural alternativesTake care of bottlenecksTake care of bottlenecks

BASIC VERILOGBASIC VERILOG

A chip contain many A chip contain many modulesmodules

A module is a basic blockA module is a basic block

A module uses predefined A module uses predefined cells (Mux, Adder)cells (Mux, Adder)

Everything is based on Everything is based on primitives (e.g. NAND)primitives (e.g. NAND)

Chip

Modules

Cells

Primitives

VERILOG LANGUAGEVERILOG LANGUAGE

Module <module name> (<port Module <module name> (<port list>); list>);

<declares> <declares> <module items><module items>

endmoduleendmodule

Module_tb(<port list>);Module_tb(<port list>);InitialInitialbeginbeginClk= 1’b0;Clk= 1’b0;#50 clk = ~clk; //clock toggles#50 clk = ~clk; //clock togglesendend

The The <module name><module name> is an is an identifier that uniquely names identifier that uniquely names the module. the module.

The The <port list><port list> is a list of is a list of input, in-out and output ports input, in-out and output ports which are used to connect to which are used to connect to other modules. other modules.

The The <declares><declares> section section specifies data objects as specifies data objects as registers, memories and wires registers, memories and wires as wells as procedural as wells as procedural constructs such as constructs such as functionfunctions s and and tasktasks.s.

Single Cycle Single Cycle

PIPELINED PIPELINED

PIPELINED WITH FORWARDINGPIPELINED WITH FORWARDING

PIPELINED WITH HAZARD UNIT PIPELINED WITH HAZARD UNIT

PIPELINE WITH BRANCHPIPELINE WITH BRANCH

PARAMETERS COMPAREDPARAMETERS COMPARED

CELLSCELLS

AREAAREA

DYNAMIC POWERDYNAMIC POWER

SLACKSLACK

CLOCKCLOCK

SYNTHESIS RESULTSSYNTHESIS RESULTS

SINGLESINGLE PIPELINEPIPELINE PIPELINE PIPELINE FWDFWD

PIPELINE PIPELINE HAZARD HAZARD UNITUNIT

PIPELINE PIPELINE WITH WITH BRANCHBRANCH

CELLSCELLS 3232 427427 510510 539539 715715

AREAAREA 3251432514 3410334103 3931239312 4173641736 4269842698

DYNAMIC DYNAMIC POWERPOWER

1.78mW1.78mW 2.39mW2.39mW 3.53mW3.53mW 3.9mW3.9mW 4.8 mW4.8 mW

SLACKSLACK -50-50 00 00 -2-2 + 3+ 3

CLOCKCLOCK 60ns60ns 32ns32ns 54ns54ns 72ns72ns 6262

CONCLUSIONCONCLUSION

Area TradeoffsArea Tradeoffs

Power dissipated Power dissipated

Clock CyclesClock Cycles